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-rw-r--r--contrib/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp39
1 files changed, 38 insertions, 1 deletions
diff --git a/contrib/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/contrib/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index 9acefe53ce4a..d6767d51f2cc 100644
--- a/contrib/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/contrib/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -33,6 +33,43 @@ extern "C" void LLVMInitializePowerPCTarget() {
RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
}
+/// Return the datalayout string of a subtarget.
+static std::string getDataLayoutString(const PPCSubtarget &ST) {
+ const Triple &T = ST.getTargetTriple();
+
+ // PPC is big endian
+ std::string Ret = "E";
+
+ // PPC64 has 64 bit pointers, PPC32 has 32 bit pointers.
+ if (ST.isPPC64())
+ Ret += "-p:64:64";
+ else
+ Ret += "-p:32:32";
+
+ // Note, the alignment values for f64 and i64 on ppc64 in Darwin
+ // documentation are wrong; these are correct (i.e. "what gcc does").
+ if (ST.isPPC64() || ST.isSVR4ABI())
+ Ret += "-f64:64:64-i64:64:64";
+ else
+ Ret += "-f64:32:64";
+
+ // Set support for 128 floats depending on the ABI.
+ if (!ST.isPPC64() && ST.isSVR4ABI())
+ Ret += "-f128:64:128";
+
+ // Some ABIs support 128 bit vectors.
+ if (ST.isPPC64() && ST.isSVR4ABI())
+ Ret += "-v128:128:128";
+
+ // PPC64 has 32 and 64 bit register, PPC32 has only 32 bit ones.
+ if (ST.isPPC64())
+ Ret += "-n32:64";
+ else
+ Ret += "-n32";
+
+ return Ret;
+}
+
PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
@@ -41,7 +78,7 @@ PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
bool is64Bit)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
Subtarget(TT, CPU, FS, is64Bit),
- DL(Subtarget.getDataLayoutString()), InstrInfo(*this),
+ DL(getDataLayoutString(Subtarget)), InstrInfo(*this),
FrameLowering(Subtarget), JITInfo(*this, is64Bit),
TLInfo(*this), TSInfo(*this),
InstrItins(Subtarget.getInstrItineraryData()) {