diff options
Diffstat (limited to 'gas/testsuite/gas/arm/neon-cond-bad.l')
-rw-r--r-- | gas/testsuite/gas/arm/neon-cond-bad.l | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/gas/testsuite/gas/arm/neon-cond-bad.l b/gas/testsuite/gas/arm/neon-cond-bad.l new file mode 100644 index 000000000000..a79f79d64f83 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cond-bad.l @@ -0,0 +1,29 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: instruction cannot be conditional -- `vmoveq q0,q1' +[^:]*:11: Error: instruction cannot be conditional -- `vmoveq d0,d1' +[^:]*:12: Error: instruction cannot be conditional -- `vmoveq\.i32 q0,#0' +[^:]*:13: Error: instruction cannot be conditional -- `vmoveq\.i32 d0,#0' +[^:]*:27: Error: instruction cannot be conditional -- `vmuleq\.f32 d0,d1,d2' +[^:]*:27: Error: instruction cannot be conditional -- `vmuleq\.f32 q0,q1,q2' +[^:]*:28: Error: instruction cannot be conditional -- `vmlaeq\.f32 d0,d1,d2' +[^:]*:28: Error: instruction cannot be conditional -- `vmlaeq\.f32 q0,q1,q2' +[^:]*:29: Error: instruction cannot be conditional -- `vmlseq\.f32 d0,d1,d2' +[^:]*:29: Error: instruction cannot be conditional -- `vmlseq\.f32 q0,q1,q2' +[^:]*:30: Error: instruction cannot be conditional -- `vaddeq\.f32 d0,d1,d2' +[^:]*:30: Error: instruction cannot be conditional -- `vaddeq\.f32 q0,q1,q2' +[^:]*:31: Error: instruction cannot be conditional -- `vsubeq\.f32 d0,d1,d2' +[^:]*:31: Error: instruction cannot be conditional -- `vsubeq\.f32 q0,q1,q2' +[^:]*:39: Error: instruction cannot be conditional -- `vabseq\.f32 d0,d1' +[^:]*:39: Error: instruction cannot be conditional -- `vabseq\.f32 q0,q1' +[^:]*:40: Error: instruction cannot be conditional -- `vnegeq\.f32 d0,d1' +[^:]*:40: Error: instruction cannot be conditional -- `vnegeq\.f32 q0,q1' +[^:]*:48: Error: instruction cannot be conditional -- `vcvteq\.s32\.f32 d0,d1' +[^:]*:48: Error: instruction cannot be conditional -- `vcvteq\.s32\.f32 q0,q1' +[^:]*:49: Error: instruction cannot be conditional -- `vcvteq\.u32\.f32 d0,d1' +[^:]*:49: Error: instruction cannot be conditional -- `vcvteq\.u32\.f32 q0,q1' +[^:]*:50: Error: instruction cannot be conditional -- `vcvteq\.f32\.s32 d0,d1' +[^:]*:50: Error: instruction cannot be conditional -- `vcvteq\.f32\.s32 q0,q1' +[^:]*:51: Error: instruction cannot be conditional -- `vcvteq\.f32\.u32 d0,d1' +[^:]*:51: Error: instruction cannot be conditional -- `vcvteq\.f32\.u32 q0,q1' +[^:]*:56: Error: instruction cannot be conditional -- `vdupeq\.32 d0,d1\[0\]' +[^:]*:57: Error: instruction cannot be conditional -- `vdupeq\.32 q0,d1\[1\]' |