1 files changed, 40 insertions, 29 deletions

diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h
index 3f5daea63ab5..4ce6d2ff5e26 100644
--- a/include/llvm/Target/TargetRegisterInfo.h
+++ b/include/llvm/Target/TargetRegisterInfo.h
@@ -40,13 +40,12 @@ class TargetRegisterClass {
 public:
   typedef const MCPhysReg* iterator;
   typedef const MCPhysReg* const_iterator;
-  typedef const MVT::SimpleValueType* vt_iterator;
   typedef const TargetRegisterClass* const * sc_iterator;
 
   // Instance variables filled by tablegen, do not use!
   const MCRegisterClass *MC;
   const uint16_t SpillSize, SpillAlignment;
-  const vt_iterator VTs;
+  const MVT::SimpleValueType *VTs;
   const uint32_t *SubClassMask;
   const uint16_t *SuperRegIndices;
   const LaneBitmask LaneMask;
@@ -93,13 +92,6 @@ public:
     return MC->contains(Reg1, Reg2);
   }
 
-  /// Return the size of the register in bytes, which is also the size
-  /// of a stack slot allocated to hold a spilled copy of this register.
-  unsigned getSize() const { return SpillSize; }
-
-  /// Return the minimum required alignment for a register of this class.
-  unsigned getAlignment() const { return SpillAlignment; }
-
   /// Return the cost of copying a value between two registers in this class.
   /// A negative number means the register class is very expensive
   /// to copy e.g. status flag register classes.
@@ -109,26 +101,6 @@ public:
   /// registers.
   bool isAllocatable() const { return MC->isAllocatable(); }
 
-  /// Return true if this TargetRegisterClass has the ValueType vt.
-  bool hasType(MVT vt) const {
-    for(int i = 0; VTs[i] != MVT::Other; ++i)
-      if (MVT(VTs[i]) == vt)
-        return true;
-    return false;
-  }
-
-  /// vt_begin / vt_end - Loop over all of the value types that can be
-  /// represented by values in this register class.
-  vt_iterator vt_begin() const {
-    return VTs;
-  }
-
-  vt_iterator vt_end() const {
-    vt_iterator I = VTs;
-    while (*I != MVT::Other) ++I;
-    return I;
-  }
-
   /// Return true if the specified TargetRegisterClass
   /// is a proper sub-class of this TargetRegisterClass.
   bool hasSubClass(const TargetRegisterClass *RC) const {
@@ -246,6 +218,7 @@ struct RegClassWeight {
 class TargetRegisterInfo : public MCRegisterInfo {
 public:
   typedef const TargetRegisterClass * const * regclass_iterator;
+  typedef const MVT::SimpleValueType* vt_iterator;
 private:
   const TargetRegisterInfoDesc *InfoDesc;     // Extra desc array for codegen
   const char *const *SubRegIndexNames;        // Names of subreg indexes.
@@ -327,6 +300,44 @@ public:
     return Index | (1u << 31);
   }
 
+  /// Return the size in bits of a register from class RC.
+  unsigned getRegSizeInBits(const TargetRegisterClass &RC) const {
+    return RC.SpillSize * 8;
+  }
+
+  /// Return the size in bytes of the stack slot allocated to hold a spilled
+  /// copy of a register from class RC.
+  unsigned getSpillSize(const TargetRegisterClass &RC) const {
+    return RC.SpillSize;
+  }
+
+  /// Return the minimum required alignment for a spill slot for a register
+  /// of this class.
+  unsigned getSpillAlignment(const TargetRegisterClass &RC) const {
+    return RC.SpillAlignment;
+  }
+
+  /// Return true if the given TargetRegisterClass has the ValueType T.
+  bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const {
+    for (int i = 0; RC.VTs[i] != MVT::Other; ++i)
+      if (MVT(RC.VTs[i]) == T)
+        return true;
+    return false;
+  }
+
+  /// Loop over all of the value types that can be represented by values
+  // in the given register class.
+  vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const {
+    return RC.VTs;
+  }
+
+  vt_iterator legalclasstypes_end(const TargetRegisterClass &RC) const {
+    vt_iterator I = RC.VTs;
+    while (*I != MVT::Other)
+      ++I;
+    return I;
+  }
+
   /// Returns the Register Class of a physical register of the given type,
   /// picking the most sub register class of the right type that contains this
   /// physreg.