diff options
Diffstat (limited to 'lib/Basic/Targets/PPC.h')
| -rw-r--r-- | lib/Basic/Targets/PPC.h | 87 |
1 files changed, 60 insertions, 27 deletions
diff --git a/lib/Basic/Targets/PPC.h b/lib/Basic/Targets/PPC.h index 058970a0e098..6e5df097921b 100644 --- a/lib/Basic/Targets/PPC.h +++ b/lib/Basic/Targets/PPC.h @@ -1,9 +1,8 @@ //===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -54,6 +53,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { static const char *const GCCRegNames[]; static const TargetInfo::GCCRegAlias GCCRegAliases[]; std::string CPU; + enum PPCFloatABI { HardFloat, SoftFloat } FloatABI; // Target cpu features. bool HasAltivec = false; @@ -132,19 +132,18 @@ public: ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) .Cases("power7", "pwr7", - ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 | - ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | - ArchDefinePpcgr | ArchDefinePpcsq) + ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | + ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | + ArchDefinePpcsq) // powerpc64le automatically defaults to at least power8. .Cases("power8", "pwr8", "ppc64le", - ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | - ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | - ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) + ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | + ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | + ArchDefinePpcgr | ArchDefinePpcsq) .Cases("power9", "pwr9", - ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | - ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | - ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | - ArchDefinePpcsq) + ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | + ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | + ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) .Default(ArchDefineNone); } return CPUKnown; @@ -185,8 +184,12 @@ public: return false; case 'O': // Zero break; - case 'b': // Base register case 'f': // Floating point register + // Don't use floating point registers on soft float ABI. + if (FloatABI == SoftFloat) + return false; + LLVM_FALLTHROUGH; + case 'b': // Base register Info.setAllowsRegister(); break; // FIXME: The following are added to allow parsing. @@ -194,13 +197,18 @@ public: // Also, is more specific checking needed? I.e. specific registers? case 'd': // Floating point register (containing 64-bit value) case 'v': // Altivec vector register + // Don't use floating point and altivec vector registers + // on soft float ABI + if (FloatABI == SoftFloat) + return false; Info.setAllowsRegister(); break; case 'w': switch (Name[1]) { case 'd': // VSX vector register to hold vector double data case 'f': // VSX vector register to hold vector float data - case 's': // VSX vector register to hold scalar float data + case 's': // VSX vector register to hold scalar double data + case 'w': // VSX vector register to hold scalar double data case 'a': // Any VSX register case 'c': // An individual CR bit case 'i': // FP or VSX register to hold 64-bit integers data @@ -306,11 +314,14 @@ public: bool hasSjLjLowering() const override { return true; } - bool useFloat128ManglingForLongDouble() const override { - return LongDoubleWidth == 128 && - LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() && - getTriple().isOSBinFormatELF(); + const char *getLongDoubleMangling() const override { + if (LongDoubleWidth == 64) + return "e"; + return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() + ? "g" + : "u9__ieee128"; } + const char *getFloat128Mangling() const override { return "u9__ieee128"; } }; class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo { @@ -327,11 +338,18 @@ public: PtrDiffType = SignedInt; IntPtrType = SignedInt; break; + case llvm::Triple::AIX: + SizeType = UnsignedLong; + PtrDiffType = SignedLong; + IntPtrType = SignedLong; + SuitableAlign = 64; + break; default: break; } - if (getTriple().isOSFreeBSD()) { + if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() || + Triple.getOS() == llvm::Triple::AIX || Triple.isMusl()) { LongDoubleWidth = LongDoubleAlign = 64; LongDoubleFormat = &llvm::APFloat::IEEEdouble(); } @@ -361,16 +379,16 @@ public: ABI = "elfv2"; } else { resetDataLayout("E-m:e-i64:64-n32:64"); - ABI = "elfv1"; + ABI = Triple.getEnvironment() == llvm::Triple::ELFv2 ? "elfv2" : "elfv1"; } - switch (getTriple().getOS()) { - case llvm::Triple::FreeBSD: + if (Triple.getOS() == llvm::Triple::AIX) + SuitableAlign = 64; + + if (Triple.isOSFreeBSD() || Triple.getOS() == llvm::Triple::AIX || + Triple.isMusl()) { LongDoubleWidth = LongDoubleAlign = 64; LongDoubleFormat = &llvm::APFloat::IEEEdouble(); - break; - default: - break; } // PPC64 supports atomics up to 8 bytes. @@ -427,6 +445,21 @@ public: } }; +class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo : + public AIXTargetInfo<PPC32TargetInfo> { +public: + using AIXTargetInfo::AIXTargetInfo; + BuiltinVaListKind getBuiltinVaListKind() const override { + return TargetInfo::CharPtrBuiltinVaList; + } +}; + +class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo : + public AIXTargetInfo<PPC64TargetInfo> { +public: + using AIXTargetInfo::AIXTargetInfo; +}; + } // namespace targets } // namespace clang #endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H |