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Diffstat (limited to 'lib/CodeGen/MachineTraceMetrics.cpp')
-rw-r--r--lib/CodeGen/MachineTraceMetrics.cpp111
1 files changed, 57 insertions, 54 deletions
diff --git a/lib/CodeGen/MachineTraceMetrics.cpp b/lib/CodeGen/MachineTraceMetrics.cpp
index f7edacd5ebaf..86332c8a93a5 100644
--- a/lib/CodeGen/MachineTraceMetrics.cpp
+++ b/lib/CodeGen/MachineTraceMetrics.cpp
@@ -328,8 +328,10 @@ MinInstrCountEnsemble::pickTracePred(const MachineBasicBlock *MBB) {
continue;
// Pick the predecessor that would give this block the smallest InstrDepth.
unsigned Depth = PredTBI->InstrDepth + CurCount;
- if (!Best || Depth < BestDepth)
- Best = Pred, BestDepth = Depth;
+ if (!Best || Depth < BestDepth) {
+ Best = Pred;
+ BestDepth = Depth;
+ }
}
return Best;
}
@@ -356,8 +358,10 @@ MinInstrCountEnsemble::pickTraceSucc(const MachineBasicBlock *MBB) {
continue;
// Pick the successor that would give this block the smallest InstrHeight.
unsigned Height = SuccTBI->InstrHeight;
- if (!Best || Height < BestHeight)
- Best = Succ, BestHeight = Height;
+ if (!Best || Height < BestHeight) {
+ Best = Succ;
+ BestHeight = Height;
+ }
}
return Best;
}
@@ -621,16 +625,16 @@ struct DataDep {
// Get the input data dependencies that must be ready before UseMI can issue.
// Return true if UseMI has any physreg operands.
-static bool getDataDeps(const MachineInstr *UseMI,
+static bool getDataDeps(const MachineInstr &UseMI,
SmallVectorImpl<DataDep> &Deps,
const MachineRegisterInfo *MRI) {
// Debug values should not be included in any calculations.
- if (UseMI->isDebugValue())
+ if (UseMI.isDebugValue())
return false;
bool HasPhysRegs = false;
- for (MachineInstr::const_mop_iterator I = UseMI->operands_begin(),
- E = UseMI->operands_end(); I != E; ++I) {
+ for (MachineInstr::const_mop_iterator I = UseMI.operands_begin(),
+ E = UseMI.operands_end(); I != E; ++I) {
const MachineOperand &MO = *I;
if (!MO.isReg())
continue;
@@ -643,7 +647,7 @@ static bool getDataDeps(const MachineInstr *UseMI,
}
// Collect virtual register reads.
if (MO.readsReg())
- Deps.push_back(DataDep(MRI, Reg, UseMI->getOperandNo(I)));
+ Deps.push_back(DataDep(MRI, Reg, UseMI.getOperandNo(I)));
}
return HasPhysRegs;
}
@@ -651,17 +655,17 @@ static bool getDataDeps(const MachineInstr *UseMI,
// Get the input data dependencies of a PHI instruction, using Pred as the
// preferred predecessor.
// This will add at most one dependency to Deps.
-static void getPHIDeps(const MachineInstr *UseMI,
+static void getPHIDeps(const MachineInstr &UseMI,
SmallVectorImpl<DataDep> &Deps,
const MachineBasicBlock *Pred,
const MachineRegisterInfo *MRI) {
// No predecessor at the beginning of a trace. Ignore dependencies.
if (!Pred)
return;
- assert(UseMI->isPHI() && UseMI->getNumOperands() % 2 && "Bad PHI");
- for (unsigned i = 1; i != UseMI->getNumOperands(); i += 2) {
- if (UseMI->getOperand(i + 1).getMBB() == Pred) {
- unsigned Reg = UseMI->getOperand(i).getReg();
+ assert(UseMI.isPHI() && UseMI.getNumOperands() % 2 && "Bad PHI");
+ for (unsigned i = 1; i != UseMI.getNumOperands(); i += 2) {
+ if (UseMI.getOperand(i + 1).getMBB() == Pred) {
+ unsigned Reg = UseMI.getOperand(i).getReg();
Deps.push_back(DataDep(MRI, Reg, i));
return;
}
@@ -823,8 +827,8 @@ computeInstrDepths(const MachineBasicBlock *MBB) {
// Collect all data dependencies.
Deps.clear();
if (UseMI.isPHI())
- getPHIDeps(&UseMI, Deps, TBI.Pred, MTM.MRI);
- else if (getDataDeps(&UseMI, Deps, MTM.MRI))
+ getPHIDeps(UseMI, Deps, TBI.Pred, MTM.MRI);
+ else if (getDataDeps(UseMI, Deps, MTM.MRI))
updatePhysDepsDownwards(&UseMI, Deps, RegUnits, MTM.TRI);
// Filter and process dependencies, computing the earliest issue cycle.
@@ -861,15 +865,16 @@ computeInstrDepths(const MachineBasicBlock *MBB) {
// Identify physreg dependencies for MI when scanning instructions upwards.
// Return the issue height of MI after considering any live regunits.
// Height is the issue height computed from virtual register dependencies alone.
-static unsigned updatePhysDepsUpwards(const MachineInstr *MI, unsigned Height,
+static unsigned updatePhysDepsUpwards(const MachineInstr &MI, unsigned Height,
SparseSet<LiveRegUnit> &RegUnits,
const TargetSchedModel &SchedModel,
const TargetInstrInfo *TII,
const TargetRegisterInfo *TRI) {
SmallVector<unsigned, 8> ReadOps;
- for (MachineInstr::const_mop_iterator MOI = MI->operands_begin(),
- MOE = MI->operands_end(); MOI != MOE; ++MOI) {
+ for (MachineInstr::const_mop_iterator MOI = MI.operands_begin(),
+ MOE = MI.operands_end();
+ MOI != MOE; ++MOI) {
const MachineOperand &MO = *MOI;
if (!MO.isReg())
continue;
@@ -877,7 +882,7 @@ static unsigned updatePhysDepsUpwards(const MachineInstr *MI, unsigned Height,
if (!TargetRegisterInfo::isPhysicalRegister(Reg))
continue;
if (MO.readsReg())
- ReadOps.push_back(MI->getOperandNo(MOI));
+ ReadOps.push_back(MI.getOperandNo(MOI));
if (!MO.isDef())
continue;
// This is a def of Reg. Remove corresponding entries from RegUnits, and
@@ -887,11 +892,11 @@ static unsigned updatePhysDepsUpwards(const MachineInstr *MI, unsigned Height,
if (I == RegUnits.end())
continue;
unsigned DepHeight = I->Cycle;
- if (!MI->isTransient()) {
+ if (!MI.isTransient()) {
// We may not know the UseMI of this dependency, if it came from the
// live-in list. SchedModel can handle a NULL UseMI.
- DepHeight += SchedModel
- .computeOperandLatency(MI, MI->getOperandNo(MOI), I->MI, I->Op);
+ DepHeight += SchedModel.computeOperandLatency(&MI, MI.getOperandNo(MOI),
+ I->MI, I->Op);
}
Height = std::max(Height, DepHeight);
// This regunit is dead above MI.
@@ -901,13 +906,13 @@ static unsigned updatePhysDepsUpwards(const MachineInstr *MI, unsigned Height,
// Now we know the height of MI. Update any regunits read.
for (unsigned i = 0, e = ReadOps.size(); i != e; ++i) {
- unsigned Reg = MI->getOperand(ReadOps[i]).getReg();
+ unsigned Reg = MI.getOperand(ReadOps[i]).getReg();
for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
LiveRegUnit &LRU = RegUnits[*Units];
// Set the height to the highest reader of the unit.
- if (LRU.Cycle <= Height && LRU.MI != MI) {
+ if (LRU.Cycle <= Height && LRU.MI != &MI) {
LRU.Cycle = Height;
- LRU.MI = MI;
+ LRU.MI = &MI;
LRU.Op = ReadOps[i];
}
}
@@ -921,15 +926,14 @@ typedef DenseMap<const MachineInstr *, unsigned> MIHeightMap;
// Push the height of DefMI upwards if required to match UseMI.
// Return true if this is the first time DefMI was seen.
-static bool pushDepHeight(const DataDep &Dep,
- const MachineInstr *UseMI, unsigned UseHeight,
- MIHeightMap &Heights,
+static bool pushDepHeight(const DataDep &Dep, const MachineInstr &UseMI,
+ unsigned UseHeight, MIHeightMap &Heights,
const TargetSchedModel &SchedModel,
const TargetInstrInfo *TII) {
// Adjust height by Dep.DefMI latency.
if (!Dep.DefMI->isTransient())
- UseHeight += SchedModel.computeOperandLatency(Dep.DefMI, Dep.DefOp,
- UseMI, Dep.UseOp);
+ UseHeight += SchedModel.computeOperandLatency(Dep.DefMI, Dep.DefOp, &UseMI,
+ Dep.UseOp);
// Update Heights[DefMI] to be the maximum height seen.
MIHeightMap::iterator I;
@@ -1048,13 +1052,13 @@ computeInstrHeights(const MachineBasicBlock *MBB) {
if (!PHI.isPHI())
break;
Deps.clear();
- getPHIDeps(&PHI, Deps, MBB, MTM.MRI);
+ getPHIDeps(PHI, Deps, MBB, MTM.MRI);
if (!Deps.empty()) {
// Loop header PHI heights are all 0.
unsigned Height = TBI.Succ ? Cycles.lookup(&PHI).Height : 0;
DEBUG(dbgs() << "pred\t" << Height << '\t' << PHI);
- if (pushDepHeight(Deps.front(), &PHI, Height,
- Heights, MTM.SchedModel, MTM.TII))
+ if (pushDepHeight(Deps.front(), PHI, Height, Heights, MTM.SchedModel,
+ MTM.TII))
addLiveIns(Deps.front().DefMI, Deps.front().DefOp, Stack);
}
}
@@ -1063,12 +1067,12 @@ computeInstrHeights(const MachineBasicBlock *MBB) {
// Go through the block backwards.
for (MachineBasicBlock::const_iterator BI = MBB->end(), BB = MBB->begin();
BI != BB;) {
- const MachineInstr *MI = --BI;
+ const MachineInstr &MI = *--BI;
// Find the MI height as determined by virtual register uses in the
// trace below.
unsigned Cycle = 0;
- MIHeightMap::iterator HeightI = Heights.find(MI);
+ MIHeightMap::iterator HeightI = Heights.find(&MI);
if (HeightI != Heights.end()) {
Cycle = HeightI->second;
// We won't be seeing any more MI uses.
@@ -1078,27 +1082,27 @@ computeInstrHeights(const MachineBasicBlock *MBB) {
// Don't process PHI deps. They depend on the specific predecessor, and
// we'll get them when visiting the predecessor.
Deps.clear();
- bool HasPhysRegs = !MI->isPHI() && getDataDeps(MI, Deps, MTM.MRI);
+ bool HasPhysRegs = !MI.isPHI() && getDataDeps(MI, Deps, MTM.MRI);
// There may also be regunit dependencies to include in the height.
if (HasPhysRegs)
- Cycle = updatePhysDepsUpwards(MI, Cycle, RegUnits,
- MTM.SchedModel, MTM.TII, MTM.TRI);
+ Cycle = updatePhysDepsUpwards(MI, Cycle, RegUnits, MTM.SchedModel,
+ MTM.TII, MTM.TRI);
// Update the required height of any virtual registers read by MI.
for (const DataDep &Dep : Deps)
if (pushDepHeight(Dep, MI, Cycle, Heights, MTM.SchedModel, MTM.TII))
addLiveIns(Dep.DefMI, Dep.DefOp, Stack);
- InstrCycles &MICycles = Cycles[MI];
+ InstrCycles &MICycles = Cycles[&MI];
MICycles.Height = Cycle;
if (!TBI.HasValidInstrDepths) {
- DEBUG(dbgs() << Cycle << '\t' << *MI);
+ DEBUG(dbgs() << Cycle << '\t' << MI);
continue;
}
// Update critical path length.
TBI.CriticalPath = std::max(TBI.CriticalPath, Cycle + MICycles.Depth);
- DEBUG(dbgs() << TBI.CriticalPath << '\t' << Cycle << '\t' << *MI);
+ DEBUG(dbgs() << TBI.CriticalPath << '\t' << Cycle << '\t' << MI);
}
// Update virtual live-in heights. They were added by addLiveIns() with a 0
@@ -1143,26 +1147,25 @@ MachineTraceMetrics::Ensemble::getTrace(const MachineBasicBlock *MBB) {
}
unsigned
-MachineTraceMetrics::Trace::getInstrSlack(const MachineInstr *MI) const {
- assert(MI && "Not an instruction.");
- assert(getBlockNum() == unsigned(MI->getParent()->getNumber()) &&
+MachineTraceMetrics::Trace::getInstrSlack(const MachineInstr &MI) const {
+ assert(getBlockNum() == unsigned(MI.getParent()->getNumber()) &&
"MI must be in the trace center block");
InstrCycles Cyc = getInstrCycles(MI);
return getCriticalPath() - (Cyc.Depth + Cyc.Height);
}
unsigned
-MachineTraceMetrics::Trace::getPHIDepth(const MachineInstr *PHI) const {
+MachineTraceMetrics::Trace::getPHIDepth(const MachineInstr &PHI) const {
const MachineBasicBlock *MBB = TE.MTM.MF->getBlockNumbered(getBlockNum());
SmallVector<DataDep, 1> Deps;
getPHIDeps(PHI, Deps, MBB, TE.MTM.MRI);
assert(Deps.size() == 1 && "PHI doesn't have MBB as a predecessor");
DataDep &Dep = Deps.front();
- unsigned DepCycle = getInstrCycles(Dep.DefMI).Depth;
+ unsigned DepCycle = getInstrCycles(*Dep.DefMI).Depth;
// Add latency if DefMI is a real instruction. Transients get latency 0.
if (!Dep.DefMI->isTransient())
- DepCycle += TE.MTM.SchedModel
- .computeOperandLatency(Dep.DefMI, Dep.DefOp, PHI, Dep.UseOp);
+ DepCycle += TE.MTM.SchedModel.computeOperandLatency(Dep.DefMI, Dep.DefOp,
+ &PHI, Dep.UseOp);
return DepCycle;
}
@@ -1248,13 +1251,13 @@ unsigned MachineTraceMetrics::Trace::getResourceLength(
return std::max(Instrs, PRMax);
}
-bool MachineTraceMetrics::Trace::isDepInTrace(const MachineInstr *DefMI,
- const MachineInstr *UseMI) const {
- if (DefMI->getParent() == UseMI->getParent())
+bool MachineTraceMetrics::Trace::isDepInTrace(const MachineInstr &DefMI,
+ const MachineInstr &UseMI) const {
+ if (DefMI.getParent() == UseMI.getParent())
return true;
- const TraceBlockInfo &DepTBI = TE.BlockInfo[DefMI->getParent()->getNumber()];
- const TraceBlockInfo &TBI = TE.BlockInfo[UseMI->getParent()->getNumber()];
+ const TraceBlockInfo &DepTBI = TE.BlockInfo[DefMI.getParent()->getNumber()];
+ const TraceBlockInfo &TBI = TE.BlockInfo[UseMI.getParent()->getNumber()];
return DepTBI.isUsefulDominator(TBI);
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-16 13:27:22 +0000