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-rw-r--r--lib/CodeGen/TargetPassConfig.cpp115
1 files changed, 71 insertions, 44 deletions
diff --git a/lib/CodeGen/TargetPassConfig.cpp b/lib/CodeGen/TargetPassConfig.cpp
index 121bed5a79cb..3fca2f4ee4fe 100644
--- a/lib/CodeGen/TargetPassConfig.cpp
+++ b/lib/CodeGen/TargetPassConfig.cpp
@@ -41,6 +41,7 @@
#include "llvm/Support/Threading.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Transforms/Scalar.h"
+#include "llvm/Transforms/Utils.h"
#include "llvm/Transforms/Utils/SymbolRewriter.h"
#include <cassert>
#include <string>
@@ -80,6 +81,9 @@ static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
cl::desc("Disable Machine LICM"));
static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
cl::desc("Disable Machine Sinking"));
+static cl::opt<bool> DisablePostRAMachineSink("disable-postra-machine-sink",
+ cl::Hidden,
+ cl::desc("Disable PostRA Machine Sinking"));
static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
cl::desc("Disable Loop Strength Reduction Pass"));
static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
@@ -94,10 +98,9 @@ static cl::opt<bool> EnableImplicitNullChecks(
"enable-implicit-null-checks",
cl::desc("Fold null checks into faulting memory operations"),
cl::init(false), cl::Hidden);
-static cl::opt<bool>
- EnableMergeICmps("enable-mergeicmps",
- cl::desc("Merge ICmp chains into a single memcmp"),
- cl::init(false), cl::Hidden);
+static cl::opt<bool> DisableMergeICmps("disable-mergeicmps",
+ cl::desc("Disable MergeICmps Pass"),
+ cl::init(false), cl::Hidden);
static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
cl::desc("Print LLVM IR produced by the loop-reduce pass"));
static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
@@ -108,14 +111,16 @@ static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
cl::desc("Verify generated machine code"),
cl::init(false),
cl::ZeroOrMore);
-static cl::opt<bool> EnableMachineOutliner("enable-machine-outliner",
- cl::Hidden,
- cl::desc("Enable machine outliner"));
-static cl::opt<bool> EnableLinkOnceODROutlining(
- "enable-linkonceodr-outlining",
- cl::Hidden,
- cl::desc("Enable the machine outliner on linkonceodr functions"),
- cl::init(false));
+enum RunOutliner { AlwaysOutline, NeverOutline, TargetDefault };
+// Enable or disable the MachineOutliner.
+static cl::opt<RunOutliner> EnableMachineOutliner(
+ "enable-machine-outliner", cl::desc("Enable the machine outliner"),
+ cl::Hidden, cl::ValueOptional, cl::init(TargetDefault),
+ cl::values(clEnumValN(AlwaysOutline, "always",
+ "Run on all functions guaranteed to be beneficial"),
+ clEnumValN(NeverOutline, "never", "Disable all outlining"),
+ // Sentinel value for unspecified option.
+ clEnumValN(AlwaysOutline, "", "")));
// Enable or disable FastISel. Both options are needed, because
// FastISel is enabled by default with -fast, and we wish to be
// able to enable or disable fast-isel independently from -O0.
@@ -123,9 +128,9 @@ static cl::opt<cl::boolOrDefault>
EnableFastISelOption("fast-isel", cl::Hidden,
cl::desc("Enable the \"fast\" instruction selector"));
-static cl::opt<cl::boolOrDefault>
- EnableGlobalISel("global-isel", cl::Hidden,
- cl::desc("Enable the \"global\" instruction selector"));
+static cl::opt<cl::boolOrDefault> EnableGlobalISelOption(
+ "global-isel", cl::Hidden,
+ cl::desc("Enable the \"global\" instruction selector"));
static cl::opt<std::string> PrintMachineInstrs(
"print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"),
@@ -226,7 +231,7 @@ static IdentifyingPassPtr overridePass(AnalysisID StandardID,
if (StandardID == &TailDuplicateID)
return applyDisable(TargetID, DisableTailDuplicate);
- if (StandardID == &TargetPassConfig::EarlyTailDuplicateID)
+ if (StandardID == &EarlyTailDuplicateID)
return applyDisable(TargetID, DisableEarlyTailDup);
if (StandardID == &MachineBlockPlacementID)
@@ -241,18 +246,21 @@ static IdentifyingPassPtr overridePass(AnalysisID StandardID,
if (StandardID == &EarlyIfConverterID)
return applyDisable(TargetID, DisableEarlyIfConversion);
- if (StandardID == &MachineLICMID)
+ if (StandardID == &EarlyMachineLICMID)
return applyDisable(TargetID, DisableMachineLICM);
if (StandardID == &MachineCSEID)
return applyDisable(TargetID, DisableMachineCSE);
- if (StandardID == &TargetPassConfig::PostRAMachineLICMID)
+ if (StandardID == &MachineLICMID)
return applyDisable(TargetID, DisablePostRAMachineLICM);
if (StandardID == &MachineSinkingID)
return applyDisable(TargetID, DisableMachineSink);
+ if (StandardID == &PostRAMachineSinkingID)
+ return applyDisable(TargetID, DisablePostRAMachineSink);
+
if (StandardID == &MachineCopyPropagationID)
return applyDisable(TargetID, DisableCopyProp);
@@ -267,10 +275,6 @@ INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
"Target Pass Configuration", false, false)
char TargetPassConfig::ID = 0;
-// Pseudo Pass IDs.
-char TargetPassConfig::EarlyTailDuplicateID = 0;
-char TargetPassConfig::PostRAMachineLICMID = 0;
-
namespace {
struct InsertedPass {
@@ -366,10 +370,6 @@ TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm)
initializeBasicAAWrapperPassPass(*PassRegistry::getPassRegistry());
initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
- // Substitute Pseudo Pass IDs for real ones.
- substitutePass(&EarlyTailDuplicateID, &TailDuplicateID);
- substitutePass(&PostRAMachineLICMID, &MachineLICMID);
-
if (StringRef(PrintMachineInstrs.getValue()).equals(""))
TM.Options.PrintMachineCode = true;
@@ -604,7 +604,7 @@ void TargetPassConfig::addIRPasses() {
// loads and compares. ExpandMemCmpPass then tries to expand those calls
// into optimally-sized loads and compares. The transforms are enabled by a
// target lowering hook.
- if (EnableMergeICmps)
+ if (!DisableMergeICmps)
addPass(createMergeICmpsPass());
addPass(createExpandMemCmpPass());
}
@@ -662,6 +662,14 @@ void TargetPassConfig::addPassesToHandleExceptions() {
addPass(createWinEHPass());
addPass(createDwarfEHPass());
break;
+ case ExceptionHandling::Wasm:
+ // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
+ // on catchpads and cleanuppads because it does not outline them into
+ // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
+ // should remove PHIs there.
+ addPass(createWinEHPass(/*DemoteCatchSwitchPHIOnly=*/false));
+ addPass(createWasmEHPass());
+ break;
case ExceptionHandling::None:
addPass(createLowerInvokePass());
@@ -704,16 +712,20 @@ void TargetPassConfig::addISelPrepare() {
}
bool TargetPassConfig::addCoreISelPasses() {
- // Enable FastISel with -fast, but allow that to be overridden.
+ // Enable FastISel with -fast-isel, but allow that to be overridden.
TM->setO0WantsFastISel(EnableFastISelOption != cl::BOU_FALSE);
if (EnableFastISelOption == cl::BOU_TRUE ||
(TM->getOptLevel() == CodeGenOpt::None && TM->getO0WantsFastISel()))
TM->setFastISel(true);
- // Ask the target for an isel.
- // Enable GlobalISel if the target wants to, but allow that to be overriden.
- if (EnableGlobalISel == cl::BOU_TRUE ||
- (EnableGlobalISel == cl::BOU_UNSET && isGlobalISelEnabled())) {
+ // Ask the target for an instruction selector.
+ // Explicitly enabling fast-isel should override implicitly enabled
+ // global-isel.
+ if (EnableGlobalISelOption == cl::BOU_TRUE ||
+ (EnableGlobalISelOption == cl::BOU_UNSET &&
+ TM->Options.EnableGlobalISel && EnableFastISelOption != cl::BOU_TRUE)) {
+ TM->setFastISel(false);
+
if (addIRTranslator())
return true;
@@ -750,7 +762,7 @@ bool TargetPassConfig::addCoreISelPasses() {
}
bool TargetPassConfig::addISelPasses() {
- if (TM->Options.EmulatedTLS)
+ if (TM->useEmulatedTLS())
addPass(createLowerEmuTLSPass());
addPass(createPreISelIntrinsicLoweringPass());
@@ -839,8 +851,10 @@ void TargetPassConfig::addMachinePasses() {
addPostRegAlloc();
// Insert prolog/epilog code. Eliminate abstract frame index references...
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::None) {
+ addPass(&PostRAMachineSinkingID);
addPass(&ShrinkWrapID);
+ }
// Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
// do so if it hasn't been disabled, substituted, or overridden.
@@ -899,8 +913,17 @@ void TargetPassConfig::addMachinePasses() {
addPass(&XRayInstrumentationID, false);
addPass(&PatchableFunctionID, false);
- if (EnableMachineOutliner)
- PM->add(createMachineOutlinerPass(EnableLinkOnceODROutlining));
+ if (TM->Options.EnableMachineOutliner && getOptLevel() != CodeGenOpt::None &&
+ EnableMachineOutliner != NeverOutline) {
+ bool RunOnAllFunctions = (EnableMachineOutliner == AlwaysOutline);
+ bool AddOutliner = RunOnAllFunctions ||
+ TM->Options.SupportsDefaultOutlining;
+ if (AddOutliner)
+ addPass(createMachineOutlinerPass(RunOnAllFunctions));
+ }
+
+ // Add passes that directly emit MI after all other MI passes.
+ addPreEmitPass2();
AddingMachinePasses = false;
}
@@ -933,7 +956,7 @@ void TargetPassConfig::addMachineSSAOptimization() {
// loop info, just like LICM and CSE below.
addILPOpts();
- addPass(&MachineLICMID, false);
+ addPass(&EarlyMachineLICMID, false);
addPass(&MachineCSEID, false);
addPass(&MachineSinkingID);
@@ -1082,10 +1105,14 @@ void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
// kill markers.
addPass(&StackSlotColoringID);
+ // Copy propagate to forward register uses and try to eliminate COPYs that
+ // were not coalesced.
+ addPass(&MachineCopyPropagationID);
+
// Run post-ra machine LICM to hoist reloads / remats.
//
// FIXME: can this move into MachineLateOptimization?
- addPass(&PostRAMachineLICMID);
+ addPass(&MachineLICMID);
}
}
@@ -1127,13 +1154,13 @@ void TargetPassConfig::addBlockPlacement() {
//===---------------------------------------------------------------------===//
/// GlobalISel Configuration
//===---------------------------------------------------------------------===//
-
-bool TargetPassConfig::isGlobalISelEnabled() const {
- return false;
-}
-
bool TargetPassConfig::isGlobalISelAbortEnabled() const {
- return EnableGlobalISelAbort == 1;
+ if (EnableGlobalISelAbort.getNumOccurrences() > 0)
+ return EnableGlobalISelAbort == 1;
+
+ // When no abort behaviour is specified, we don't abort if the target says
+ // that GISel is enabled.
+ return !TM->Options.EnableGlobalISel;
}
bool TargetPassConfig::reportDiagnosticWhenGlobalISelFallback() const {
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-26 05:59:41 +0000