diff options
Diffstat (limited to 'lib/Headers/xmmintrin.h')
| -rw-r--r-- | lib/Headers/xmmintrin.h | 579 |
1 files changed, 329 insertions, 250 deletions
diff --git a/lib/Headers/xmmintrin.h b/lib/Headers/xmmintrin.h index 99cddb0fac82..dc31b85cfd7c 100644 --- a/lib/Headers/xmmintrin.h +++ b/lib/Headers/xmmintrin.h @@ -46,7 +46,7 @@ typedef unsigned int __v4su __attribute__((__vector_size__(16))); /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VADDSS / ADDSS instructions. +/// This intrinsic corresponds to the <c> VADDSS / ADDSS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing one of the source operands. @@ -69,7 +69,7 @@ _mm_add_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VADDPS / ADDPS instructions. +/// This intrinsic corresponds to the <c> VADDPS / ADDPS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing one of the source operands. @@ -88,7 +88,7 @@ _mm_add_ps(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VSUBSS / SUBSS instructions. +/// This intrinsic corresponds to the <c> VSUBSS / SUBSS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing the minuend. The lower 32 bits @@ -112,7 +112,7 @@ _mm_sub_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VSUBPS / SUBPS instructions. +/// This intrinsic corresponds to the <c> VSUBPS / SUBPS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing the minuend. @@ -131,7 +131,7 @@ _mm_sub_ps(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMULSS / MULSS instructions. +/// This intrinsic corresponds to the <c> VMULSS / MULSS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing one of the source operands. @@ -154,7 +154,7 @@ _mm_mul_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMULPS / MULPS instructions. +/// This intrinsic corresponds to the <c> VMULPS / MULPS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing one of the source operands. @@ -173,7 +173,7 @@ _mm_mul_ps(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VDIVSS / DIVSS instructions. +/// This intrinsic corresponds to the <c> VDIVSS / DIVSS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing the dividend. The lower 32 @@ -195,7 +195,7 @@ _mm_div_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VDIVPS / DIVPS instructions. +/// This intrinsic corresponds to the <c> VDIVPS / DIVPS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing the dividend. @@ -214,7 +214,7 @@ _mm_div_ps(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VSQRTSS / SQRTSS instructions. +/// This intrinsic corresponds to the <c> VSQRTSS / SQRTSS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are @@ -233,7 +233,7 @@ _mm_sqrt_ss(__m128 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VSQRTPS / SQRTPS instructions. +/// This intrinsic corresponds to the <c> VSQRTPS / SQRTPS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. @@ -250,7 +250,7 @@ _mm_sqrt_ps(__m128 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VRCPSS / RCPSS instructions. +/// This intrinsic corresponds to the <c> VRCPSS / RCPSS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are @@ -269,7 +269,7 @@ _mm_rcp_ss(__m128 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VRCPPS / RCPPS instructions. +/// This intrinsic corresponds to the <c> VRCPPS / RCPPS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. @@ -286,7 +286,7 @@ _mm_rcp_ps(__m128 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VRSQRTSS / RSQRTSS instructions. +/// This intrinsic corresponds to the <c> VRSQRTSS / RSQRTSS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are @@ -306,7 +306,7 @@ _mm_rsqrt_ss(__m128 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VRSQRTPS / RSQRTPS instructions. +/// This intrinsic corresponds to the <c> VRSQRTPS / RSQRTPS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. @@ -324,7 +324,7 @@ _mm_rsqrt_ps(__m128 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMINSS / MINSS instructions. +/// This intrinsic corresponds to the <c> VMINSS / MINSS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing one of the operands. The lower @@ -341,12 +341,12 @@ _mm_min_ss(__m128 __a, __m128 __b) return __builtin_ia32_minss((__v4sf)__a, (__v4sf)__b); } -/// \brief Compares two 128-bit vectors of [4 x float] and returns the -/// lesser of each pair of values. +/// \brief Compares two 128-bit vectors of [4 x float] and returns the lesser +/// of each pair of values. /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMINPS / MINPS instructions. +/// This intrinsic corresponds to the <c> VMINPS / MINPS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing one of the operands. @@ -361,12 +361,12 @@ _mm_min_ps(__m128 __a, __m128 __b) } /// \brief Compares two 32-bit float values in the low-order bits of both -/// operands and returns the greater value in the low-order bits of -/// a vector [4 x float]. +/// operands and returns the greater value in the low-order bits of a 128-bit +/// vector of [4 x float]. /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMAXSS / MAXSS instructions. +/// This intrinsic corresponds to the <c> VMAXSS / MAXSS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing one of the operands. The lower @@ -388,7 +388,7 @@ _mm_max_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMAXPS / MAXPS instructions. +/// This intrinsic corresponds to the <c> VMAXPS / MAXPS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing one of the operands. @@ -406,7 +406,7 @@ _mm_max_ps(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VANDPS / ANDPS instructions. +/// This intrinsic corresponds to the <c> VANDPS / ANDPS </c> instructions. /// /// \param __a /// A 128-bit vector containing one of the source operands. @@ -426,7 +426,7 @@ _mm_and_ps(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VANDNPS / ANDNPS instructions. +/// This intrinsic corresponds to the <c> VANDNPS / ANDNPS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing the first source operand. The @@ -446,7 +446,7 @@ _mm_andnot_ps(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VORPS / ORPS instructions. +/// This intrinsic corresponds to the <c> VORPS / ORPS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing one of the source operands. @@ -465,7 +465,7 @@ _mm_or_ps(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VXORPS / XORPS instructions. +/// This intrinsic corresponds to the <c> VXORPS / XORPS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing one of the source operands. @@ -485,7 +485,7 @@ _mm_xor_ps(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCMPEQSS / CMPEQSS instructions. +/// This intrinsic corresponds to the <c> VCMPEQSS / CMPEQSS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing one of the operands. The lower @@ -506,7 +506,7 @@ _mm_cmpeq_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCMPEQPS / CMPEQPS instructions. +/// This intrinsic corresponds to the <c> VCMPEQPS / CMPEQPS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. @@ -526,7 +526,7 @@ _mm_cmpeq_ps(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCMPLTSS / CMPLTSS instructions. +/// This intrinsic corresponds to the <c> VCMPLTSS / CMPLTSS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing one of the operands. The lower @@ -548,7 +548,7 @@ _mm_cmplt_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCMPLTPS / CMPLTPS instructions. +/// This intrinsic corresponds to the <c> VCMPLTPS / CMPLTPS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. @@ -569,7 +569,7 @@ _mm_cmplt_ps(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCMPLESS / CMPLESS instructions. +/// This intrinsic corresponds to the <c> VCMPLESS / CMPLESS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing one of the operands. The lower @@ -591,7 +591,7 @@ _mm_cmple_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCMPLEPS / CMPLEPS instructions. +/// This intrinsic corresponds to the <c> VCMPLEPS / CMPLEPS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. @@ -611,7 +611,7 @@ _mm_cmple_ps(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCMPLTSS / CMPLTSS instructions. +/// This intrinsic corresponds to the <c> VCMPLTSS / CMPLTSS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing one of the operands. The lower @@ -635,7 +635,7 @@ _mm_cmpgt_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCMPLTPS / CMPLTPS instructions. +/// This intrinsic corresponds to the <c> VCMPLTPS / CMPLTPS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. @@ -656,7 +656,7 @@ _mm_cmpgt_ps(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCMPLESS / CMPLESS instructions. +/// This intrinsic corresponds to the <c> VCMPLESS / CMPLESS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing one of the operands. The lower @@ -680,7 +680,7 @@ _mm_cmpge_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCMPLEPS / CMPLEPS instructions. +/// This intrinsic corresponds to the <c> VCMPLEPS / CMPLEPS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. @@ -699,7 +699,8 @@ _mm_cmpge_ps(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCMPNEQSS / CMPNEQSS instructions. +/// This intrinsic corresponds to the <c> VCMPNEQSS / CMPNEQSS </c> +/// instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing one of the operands. The lower @@ -720,7 +721,8 @@ _mm_cmpneq_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCMPNEQPS / CMPNEQPS instructions. +/// This intrinsic corresponds to the <c> VCMPNEQPS / CMPNEQPS </c> +/// instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. @@ -740,7 +742,8 @@ _mm_cmpneq_ps(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCMPNLTSS / CMPNLTSS instructions. +/// This intrinsic corresponds to the <c> VCMPNLTSS / CMPNLTSS </c> +/// instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing one of the operands. The lower @@ -762,7 +765,8 @@ _mm_cmpnlt_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCMPNLTPS / CMPNLTPS instructions. +/// This intrinsic corresponds to the <c> VCMPNLTPS / CMPNLTPS </c> +/// instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. @@ -783,7 +787,8 @@ _mm_cmpnlt_ps(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCMPNLESS / CMPNLESS instructions. +/// This intrinsic corresponds to the <c> VCMPNLESS / CMPNLESS </c> +/// instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing one of the operands. The lower @@ -805,7 +810,8 @@ _mm_cmpnle_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCMPNLEPS / CMPNLEPS instructions. +/// This intrinsic corresponds to the <c> VCMPNLEPS / CMPNLEPS </c> +/// instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. @@ -826,7 +832,8 @@ _mm_cmpnle_ps(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCMPNLTSS / CMPNLTSS instructions. +/// This intrinsic corresponds to the <c> VCMPNLTSS / CMPNLTSS </c> +/// instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing one of the operands. The lower @@ -850,7 +857,8 @@ _mm_cmpngt_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCMPNLTPS / CMPNLTPS instructions. +/// This intrinsic corresponds to the <c> VCMPNLTPS / CMPNLTPS </c> +/// instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. @@ -871,7 +879,8 @@ _mm_cmpngt_ps(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCMPNLESS / CMPNLESS instructions. +/// This intrinsic corresponds to the <c> VCMPNLESS / CMPNLESS </c> +/// instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing one of the operands. The lower @@ -895,7 +904,8 @@ _mm_cmpnge_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCMPNLEPS / CMPNLEPS instructions. +/// This intrinsic corresponds to the <c> VCMPNLEPS / CMPNLEPS </c> +/// instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. @@ -916,7 +926,8 @@ _mm_cmpnge_ps(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCMPORDSS / CMPORDSS instructions. +/// This intrinsic corresponds to the <c> VCMPORDSS / CMPORDSS </c> +/// instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing one of the operands. The lower @@ -938,7 +949,8 @@ _mm_cmpord_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCMPORDPS / CMPORDPS instructions. +/// This intrinsic corresponds to the <c> VCMPORDPS / CMPORDPS </c> +/// instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. @@ -959,7 +971,8 @@ _mm_cmpord_ps(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCMPUNORDSS / CMPUNORDSS instructions. +/// This intrinsic corresponds to the <c> VCMPUNORDSS / CMPUNORDSS </c> +/// instructions. /// /// \param __a /// A 128-bit vector of [4 x float] containing one of the operands. The lower @@ -981,7 +994,8 @@ _mm_cmpunord_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCMPUNORDPS / CMPUNORDPS instructions. +/// This intrinsic corresponds to the <c> VCMPUNORDPS / CMPUNORDPS </c> +/// instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. @@ -999,7 +1013,8 @@ _mm_cmpunord_ps(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCOMISS / COMISS instructions. +/// This intrinsic corresponds to the <c> VCOMISS / COMISS </c> +/// instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are @@ -1020,7 +1035,8 @@ _mm_comieq_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCOMISS / COMISS instructions. +/// This intrinsic corresponds to the <c> VCOMISS / COMISS </c> +/// instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are @@ -1041,7 +1057,7 @@ _mm_comilt_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCOMISS / COMISS instructions. +/// This intrinsic corresponds to the <c> VCOMISS / COMISS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are @@ -1062,7 +1078,7 @@ _mm_comile_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCOMISS / COMISS instructions. +/// This intrinsic corresponds to the <c> VCOMISS / COMISS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are @@ -1083,7 +1099,7 @@ _mm_comigt_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCOMISS / COMISS instructions. +/// This intrinsic corresponds to the <c> VCOMISS / COMISS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are @@ -1104,7 +1120,7 @@ _mm_comige_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCOMISS / COMISS instructions. +/// This intrinsic corresponds to the <c> VCOMISS / COMISS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are @@ -1125,7 +1141,7 @@ _mm_comineq_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VUCOMISS / UCOMISS instructions. +/// This intrinsic corresponds to the <c> VUCOMISS / UCOMISS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are @@ -1146,7 +1162,7 @@ _mm_ucomieq_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VUCOMISS / UCOMISS instructions. +/// This intrinsic corresponds to the <c> VUCOMISS / UCOMISS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are @@ -1162,13 +1178,13 @@ _mm_ucomilt_ss(__m128 __a, __m128 __b) } /// \brief Performs an unordered comparison of two 32-bit float values using -/// the low-order bits of both operands to determine if the first operand -/// is less than or equal to the second operand and returns the result of -/// the comparison. +/// the low-order bits of both operands to determine if the first operand is +/// less than or equal to the second operand and returns the result of the +/// comparison. /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VUCOMISS / UCOMISS instructions. +/// This intrinsic corresponds to the <c> VUCOMISS / UCOMISS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are @@ -1184,13 +1200,13 @@ _mm_ucomile_ss(__m128 __a, __m128 __b) } /// \brief Performs an unordered comparison of two 32-bit float values using -/// the low-order bits of both operands to determine if the first operand -/// is greater than the second operand and returns the result of the +/// the low-order bits of both operands to determine if the first operand is +/// greater than the second operand and returns the result of the /// comparison. /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VUCOMISS / UCOMISS instructions. +/// This intrinsic corresponds to the <c> VUCOMISS / UCOMISS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are @@ -1212,7 +1228,7 @@ _mm_ucomigt_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VUCOMISS / UCOMISS instructions. +/// This intrinsic corresponds to the <c> VUCOMISS / UCOMISS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are @@ -1233,7 +1249,7 @@ _mm_ucomige_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VUCOMISS / UCOMISS instructions. +/// This intrinsic corresponds to the <c> VUCOMISS / UCOMISS </c> instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are @@ -1253,7 +1269,8 @@ _mm_ucomineq_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCVTSS2SI / CVTSS2SI instructions. +/// This intrinsic corresponds to the <c> VCVTSS2SI / CVTSS2SI </c> +/// instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are @@ -1270,7 +1287,8 @@ _mm_cvtss_si32(__m128 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCVTSS2SI / CVTSS2SI instructions. +/// This intrinsic corresponds to the <c> VCVTSS2SI / CVTSS2SI </c> +/// instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are @@ -1289,7 +1307,8 @@ _mm_cvt_ss2si(__m128 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCVTSS2SI / CVTSS2SI instructions. +/// This intrinsic corresponds to the <c> VCVTSS2SI / CVTSS2SI </c> +/// instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are @@ -1308,7 +1327,7 @@ _mm_cvtss_si64(__m128 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c CVTPS2PI instruction. +/// This intrinsic corresponds to the <c> CVTPS2PI </c> instruction. /// /// \param __a /// A 128-bit vector of [4 x float]. @@ -1324,7 +1343,7 @@ _mm_cvtps_pi32(__m128 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c CVTPS2PI instruction. +/// This intrinsic corresponds to the <c> CVTPS2PI </c> instruction. /// /// \param __a /// A 128-bit vector of [4 x float]. @@ -1341,7 +1360,8 @@ _mm_cvt_ps2pi(__m128 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCVTTSS2SI / CVTTSS2SI instructions. +/// This intrinsic corresponds to the <c> VCVTTSS2SI / CVTTSS2SI </c> +/// instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are @@ -1359,7 +1379,8 @@ _mm_cvttss_si32(__m128 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCVTTSS2SI / CVTTSS2SI instructions. +/// This intrinsic corresponds to the <c> VCVTTSS2SI / CVTTSS2SI </c> +/// instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are @@ -1371,13 +1392,15 @@ _mm_cvtt_ss2si(__m128 __a) return _mm_cvttss_si32(__a); } +#ifdef __x86_64__ /// \brief Converts a float value contained in the lower 32 bits of a vector of /// [4 x float] into a 64-bit integer, truncating the result when it is /// inexact. /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCVTTSS2SI / CVTTSS2SI instructions. +/// This intrinsic corresponds to the <c> VCVTTSS2SI / CVTTSS2SI </c> +/// instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are @@ -1388,6 +1411,7 @@ _mm_cvttss_si64(__m128 __a) { return __builtin_ia32_cvttss2si64((__v4sf)__a); } +#endif /// \brief Converts two low-order float values in a 128-bit vector of /// [4 x float] into a 64-bit vector of [2 x i32], truncating the result @@ -1395,7 +1419,8 @@ _mm_cvttss_si64(__m128 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c CVTTPS2PI / VTTPS2PI instructions. +/// This intrinsic corresponds to the <c> CVTTPS2PI / VTTPS2PI </c> +/// instructions. /// /// \param __a /// A 128-bit vector of [4 x float]. @@ -1412,7 +1437,7 @@ _mm_cvttps_pi32(__m128 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c CVTTPS2PI instruction. +/// This intrinsic corresponds to the <c> CVTTPS2PI </c> instruction. /// /// \param __a /// A 128-bit vector of [4 x float]. @@ -1430,7 +1455,7 @@ _mm_cvtt_ps2pi(__m128 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCVTSI2SS / CVTSI2SS instruction. +/// This intrinsic corresponds to the <c> VCVTSI2SS / CVTSI2SS </c> instruction. /// /// \param __a /// A 128-bit vector of [4 x float]. @@ -1453,7 +1478,7 @@ _mm_cvtsi32_ss(__m128 __a, int __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCVTSI2SS / CVTSI2SS instruction. +/// This intrinsic corresponds to the <c> VCVTSI2SS / CVTSI2SS </c> instruction. /// /// \param __a /// A 128-bit vector of [4 x float]. @@ -1477,7 +1502,7 @@ _mm_cvt_si2ss(__m128 __a, int __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCVTSI2SS / CVTSI2SS instruction. +/// This intrinsic corresponds to the <c> VCVTSI2SS / CVTSI2SS </c> instruction. /// /// \param __a /// A 128-bit vector of [4 x float]. @@ -1502,7 +1527,7 @@ _mm_cvtsi64_ss(__m128 __a, long long __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c CVTPI2PS instruction. +/// This intrinsic corresponds to the <c> CVTPI2PS </c> instruction. /// /// \param __a /// A 128-bit vector of [4 x float]. @@ -1525,7 +1550,7 @@ _mm_cvtpi32_ps(__m128 __a, __m64 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c CVTPI2PS instruction. +/// This intrinsic corresponds to the <c> CVTPI2PS </c> instruction. /// /// \param __a /// A 128-bit vector of [4 x float]. @@ -1546,7 +1571,7 @@ _mm_cvt_pi2ps(__m128 __a, __m64 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMOVSS / MOVSS instruction. +/// This intrinsic corresponds to the <c> VMOVSS / MOVSS </c> instruction. /// /// \param __a /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are @@ -1558,13 +1583,13 @@ _mm_cvtss_f32(__m128 __a) return __a[0]; } -/// \brief Loads two packed float values from the address __p into the +/// \brief Loads two packed float values from the address \a __p into the /// high-order bits of a 128-bit vector of [4 x float]. The low-order bits /// are copied from the low-order bits of the first operand. /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMOVHPD / MOVHPD instruction. +/// This intrinsic corresponds to the <c> VMOVHPD / MOVHPD </c> instruction. /// /// \param __a /// A 128-bit vector of [4 x float]. Bits [63:0] are written to bits [63:0] @@ -1585,13 +1610,13 @@ _mm_loadh_pi(__m128 __a, const __m64 *__p) return __builtin_shufflevector(__a, __bb, 0, 1, 4, 5); } -/// \brief Loads two packed float values from the address __p into the low-order -/// bits of a 128-bit vector of [4 x float]. The high-order bits are copied -/// from the high-order bits of the first operand. +/// \brief Loads two packed float values from the address \a __p into the +/// low-order bits of a 128-bit vector of [4 x float]. The high-order bits +/// are copied from the high-order bits of the first operand. /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMOVLPD / MOVLPD instruction. +/// This intrinsic corresponds to the <c> VMOVLPD / MOVLPD </c> instruction. /// /// \param __a /// A 128-bit vector of [4 x float]. Bits [127:64] are written to bits @@ -1619,7 +1644,7 @@ _mm_loadl_pi(__m128 __a, const __m64 *__p) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMOVSS / MOVSS instruction. +/// This intrinsic corresponds to the <c> VMOVSS / MOVSS </c> instruction. /// /// \param __p /// A pointer to a 32-bit memory location containing a single-precision @@ -1642,13 +1667,13 @@ _mm_load_ss(const float *__p) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMOVSS / MOVSS + \c shuffling +/// This intrinsic corresponds to the <c> VMOVSS / MOVSS + shuffling </c> /// instruction. /// /// \param __p /// A pointer to a float value to be loaded and duplicated. -/// \returns A 128-bit vector of [4 x float] containing the loaded -/// and duplicated values. +/// \returns A 128-bit vector of [4 x float] containing the loaded and +/// duplicated values. static __inline__ __m128 __DEFAULT_FN_ATTRS _mm_load1_ps(const float *__p) { @@ -1666,7 +1691,7 @@ _mm_load1_ps(const float *__p) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMOVAPS / MOVAPS instruction. +/// This intrinsic corresponds to the <c> VMOVAPS / MOVAPS </c> instruction. /// /// \param __p /// A pointer to a 128-bit memory location. The address of the memory @@ -1683,7 +1708,7 @@ _mm_load_ps(const float *__p) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMOVUPS / MOVUPS instruction. +/// This intrinsic corresponds to the <c> VMOVUPS / MOVUPS </c> instruction. /// /// \param __p /// A pointer to a 128-bit memory location. The address of the memory @@ -1703,7 +1728,7 @@ _mm_loadu_ps(const float *__p) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMOVAPS / MOVAPS + \c shuffling +/// This intrinsic corresponds to the <c> VMOVAPS / MOVAPS + shuffling </c> /// instruction. /// /// \param __p @@ -1725,7 +1750,6 @@ _mm_loadr_ps(const float *__p) /// This intrinsic has no corresponding instruction. /// /// \returns A 128-bit vector of [4 x float] containing undefined values. - static __inline__ __m128 __DEFAULT_FN_ATTRS _mm_undefined_ps(void) { @@ -1738,7 +1762,7 @@ _mm_undefined_ps(void) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMOVSS / MOVSS instruction. +/// This intrinsic corresponds to the <c> VMOVSS / MOVSS </c> instruction. /// /// \param __w /// A single-precision floating-point value used to initialize the lower 32 @@ -1758,7 +1782,7 @@ _mm_set_ss(float __w) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VPERMILPS / PERMILPS instruction. +/// This intrinsic corresponds to the <c> VPERMILPS / PERMILPS </c> instruction. /// /// \param __w /// A single-precision floating-point value used to initialize each vector @@ -1777,7 +1801,7 @@ _mm_set1_ps(float __w) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VPERMILPS / PERMILPS instruction. +/// This intrinsic corresponds to the <c> VPERMILPS / PERMILPS </c> instruction. /// /// \param __w /// A single-precision floating-point value used to initialize each vector @@ -1849,7 +1873,7 @@ _mm_setr_ps(float __z, float __y, float __x, float __w) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VXORPS / XORPS instruction. +/// This intrinsic corresponds to the <c> VXORPS / XORPS </c> instruction. /// /// \returns An initialized 128-bit floating-point vector of [4 x float] with /// all elements set to zero. @@ -1864,7 +1888,7 @@ _mm_setzero_ps(void) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VPEXTRQ / MOVQ instruction. +/// This intrinsic corresponds to the <c> VPEXTRQ / MOVQ </c> instruction. /// /// \param __p /// A pointer to a 64-bit memory location. @@ -1881,7 +1905,7 @@ _mm_storeh_pi(__m64 *__p, __m128 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMOVLPS / MOVLPS instruction. +/// This intrinsic corresponds to the <c> VMOVLPS / MOVLPS </c> instruction. /// /// \param __p /// A pointer to a memory location that will receive the float values. @@ -1898,7 +1922,7 @@ _mm_storel_pi(__m64 *__p, __m128 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMOVSS / MOVSS instruction. +/// This intrinsic corresponds to the <c> VMOVSS / MOVSS </c> instruction. /// /// \param __p /// A pointer to a 32-bit memory location. @@ -1913,12 +1937,12 @@ _mm_store_ss(float *__p, __m128 __a) ((struct __mm_store_ss_struct*)__p)->__u = __a[0]; } -/// \brief Stores float values from a 128-bit vector of [4 x float] to an -/// unaligned memory location. +/// \brief Stores a 128-bit vector of [4 x float] to an unaligned memory +/// location. /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMOVUPS / MOVUPS instruction. +/// This intrinsic corresponds to the <c> VMOVUPS / MOVUPS </c> instruction. /// /// \param __p /// A pointer to a 128-bit memory location. The address of the memory @@ -1934,19 +1958,18 @@ _mm_storeu_ps(float *__p, __m128 __a) ((struct __storeu_ps*)__p)->__v = __a; } -/// \brief Stores the lower 32 bits of a 128-bit vector of [4 x float] into -/// four contiguous elements in an aligned memory location. +/// \brief Stores a 128-bit vector of [4 x float] into an aligned memory +/// location. /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to \c VMOVAPS / MOVAPS + \c shuffling -/// instruction. +/// This intrinsic corresponds to the <c> VMOVAPS / MOVAPS </c> instruction. /// /// \param __p -/// A pointer to a 128-bit memory location. +/// A pointer to a 128-bit memory location. The address of the memory +/// location has to be 16-byte aligned. /// \param __a -/// A 128-bit vector of [4 x float] whose lower 32 bits are stored to each -/// of the four contiguous elements pointed by __p. +/// A 128-bit vector of [4 x float] containing the values to be stored. static __inline__ void __DEFAULT_FN_ATTRS _mm_store_ps(float *__p, __m128 __a) { @@ -1958,14 +1981,14 @@ _mm_store_ps(float *__p, __m128 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to \c VMOVAPS / MOVAPS + \c shuffling +/// This intrinsic corresponds to <c> VMOVAPS / MOVAPS + shuffling </c> /// instruction. /// /// \param __p /// A pointer to a 128-bit memory location. /// \param __a /// A 128-bit vector of [4 x float] whose lower 32 bits are stored to each -/// of the four contiguous elements pointed by __p. +/// of the four contiguous elements pointed by \a __p. static __inline__ void __DEFAULT_FN_ATTRS _mm_store1_ps(float *__p, __m128 __a) { @@ -1973,18 +1996,19 @@ _mm_store1_ps(float *__p, __m128 __a) _mm_store_ps(__p, __a); } -/// \brief Stores float values from a 128-bit vector of [4 x float] to an -/// aligned memory location. +/// \brief Stores the lower 32 bits of a 128-bit vector of [4 x float] into +/// four contiguous elements in an aligned memory location. /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMOVAPS / MOVAPS instruction. +/// This intrinsic corresponds to <c> VMOVAPS / MOVAPS + shuffling </c> +/// instruction. /// /// \param __p -/// A pointer to a 128-bit memory location. The address of the memory -/// location has to be 128-bit aligned. +/// A pointer to a 128-bit memory location. /// \param __a -/// A 128-bit vector of [4 x float] containing the values to be stored. +/// A 128-bit vector of [4 x float] whose lower 32 bits are stored to each +/// of the four contiguous elements pointed by \a __p. static __inline__ void __DEFAULT_FN_ATTRS _mm_store_ps1(float *__p, __m128 __a) { @@ -1996,7 +2020,7 @@ _mm_store_ps1(float *__p, __m128 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMOVAPS / MOVAPS + \c shuffling +/// This intrinsic corresponds to the <c> VMOVAPS / MOVAPS + shuffling </c> /// instruction. /// /// \param __p @@ -2029,20 +2053,21 @@ _mm_storer_ps(float *__p, __m128 __a) /// void _mm_prefetch(const void * a, const int sel); /// \endcode /// -/// This intrinsic corresponds to the \c PREFETCHNTA instruction. +/// This intrinsic corresponds to the <c> PREFETCHNTA </c> instruction. /// /// \param a /// A pointer to a memory location containing a cache line of data. /// \param sel -/// A predefined integer constant specifying the type of prefetch operation: -/// _MM_HINT_NTA: Move data using the non-temporal access (NTA) hint. -/// The PREFETCHNTA instruction will be generated. +/// A predefined integer constant specifying the type of prefetch +/// operation: \n +/// _MM_HINT_NTA: Move data using the non-temporal access (NTA) hint. The +/// PREFETCHNTA instruction will be generated. \n /// _MM_HINT_T0: Move data using the T0 hint. The PREFETCHT0 instruction will -/// be generated. +/// be generated. \n /// _MM_HINT_T1: Move data using the T1 hint. The PREFETCHT1 instruction will -/// be generated. +/// be generated. \n /// _MM_HINT_T2: Move data using the T2 hint. The PREFETCHT2 instruction will -/// be generated. +/// be generated. #define _mm_prefetch(a, sel) (__builtin_prefetch((void *)(a), 0, (sel))) #endif @@ -2052,7 +2077,7 @@ _mm_storer_ps(float *__p, __m128 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c MOVNTQ instruction. +/// This intrinsic corresponds to the <c> MOVNTQ </c> instruction. /// /// \param __p /// A pointer to an aligned memory location used to store the register value. @@ -2070,7 +2095,7 @@ _mm_stream_pi(__m64 *__p, __m64 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMOVNTPS / MOVNTPS instruction. +/// This intrinsic corresponds to the <c> VMOVNTPS / MOVNTPS </c> instruction. /// /// \param __p /// A pointer to a 128-bit aligned memory location that will receive the @@ -2083,6 +2108,10 @@ _mm_stream_ps(float *__p, __m128 __a) __builtin_nontemporal_store((__v4sf)__a, (__v4sf*)__p); } +#if defined(__cplusplus) +extern "C" { +#endif + /// \brief Forces strong memory ordering (serialization) between store /// instructions preceding this instruction and store instructions following /// this instruction, ensuring the system completes all previous stores @@ -2090,28 +2119,32 @@ _mm_stream_ps(float *__p, __m128 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c SFENCE instruction. +/// This intrinsic corresponds to the <c> SFENCE </c> instruction. /// -static __inline__ void __DEFAULT_FN_ATTRS -_mm_sfence(void) -{ - __builtin_ia32_sfence(); -} +void _mm_sfence(void); + +#if defined(__cplusplus) +} // extern "C" +#endif /// \brief Extracts 16-bit element from a 64-bit vector of [4 x i16] and /// returns it, as specified by the immediate integer operand. /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VPEXTRW / PEXTRW instruction. +/// \code +/// void _mm_extract_pi(__m64 a, int n); +/// \endcode /// -/// \param __a +/// This intrinsic corresponds to the <c> VPEXTRW / PEXTRW </c> instruction. +/// +/// \param a /// A 64-bit vector of [4 x i16]. -/// \param __n -/// An immediate integer operand that determines which bits are extracted: -/// 0: Bits [15:0] are copied to the destination. -/// 1: Bits [31:16] are copied to the destination. -/// 2: Bits [47:32] are copied to the destination. +/// \param n +/// An immediate integer operand that determines which bits are extracted: \n +/// 0: Bits [15:0] are copied to the destination. \n +/// 1: Bits [31:16] are copied to the destination. \n +/// 2: Bits [47:32] are copied to the destination. \n /// 3: Bits [63:48] are copied to the destination. /// \returns A 16-bit integer containing the extracted 16 bits of packed data. #define _mm_extract_pi16(a, n) __extension__ ({ \ @@ -2119,26 +2152,30 @@ _mm_sfence(void) /// \brief Copies data from the 64-bit vector of [4 x i16] to the destination, /// and inserts the lower 16-bits of an integer operand at the 16-bit offset -/// specified by the immediate operand __n. +/// specified by the immediate operand \a n. /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VPINSRW / PINSRW instruction. +/// \code +/// void _mm_insert_pi(__m64 a, int d, int n); +/// \endcode /// -/// \param __a +/// This intrinsic corresponds to the <c> VPINSRW / PINSRW </c> instruction. +/// +/// \param a /// A 64-bit vector of [4 x i16]. -/// \param __d +/// \param d /// An integer. The lower 16-bit value from this operand is written to the -/// destination at the offset specified by operand __n. -/// \param __n +/// destination at the offset specified by operand \a n. +/// \param n /// An immediate integer operant that determines which the bits to be used -/// in the destination. -/// 0: Bits [15:0] are copied to the destination. -/// 1: Bits [31:16] are copied to the destination. -/// 2: Bits [47:32] are copied to the destination. -/// 3: Bits [63:48] are copied to the destination. +/// in the destination. \n +/// 0: Bits [15:0] are copied to the destination. \n +/// 1: Bits [31:16] are copied to the destination. \n +/// 2: Bits [47:32] are copied to the destination. \n +/// 3: Bits [63:48] are copied to the destination. \n /// The remaining bits in the destination are copied from the corresponding -/// bits in operand __a. +/// bits in operand \a a. /// \returns A 64-bit integer vector containing the copied packed data from the /// operands. #define _mm_insert_pi16(a, d, n) __extension__ ({ \ @@ -2150,7 +2187,7 @@ _mm_sfence(void) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c PMAXSW instruction. +/// This intrinsic corresponds to the <c> PMAXSW </c> instruction. /// /// \param __a /// A 64-bit integer vector containing one of the source operands. @@ -2169,7 +2206,7 @@ _mm_max_pi16(__m64 __a, __m64 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c PMAXUB instruction. +/// This intrinsic corresponds to the <c> PMAXUB </c> instruction. /// /// \param __a /// A 64-bit integer vector containing one of the source operands. @@ -2188,7 +2225,7 @@ _mm_max_pu8(__m64 __a, __m64 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c PMINSW instruction. +/// This intrinsic corresponds to the <c> PMINSW </c> instruction. /// /// \param __a /// A 64-bit integer vector containing one of the source operands. @@ -2207,7 +2244,7 @@ _mm_min_pi16(__m64 __a, __m64 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c PMINUB instruction. +/// This intrinsic corresponds to the <c> PMINUB </c> instruction. /// /// \param __a /// A 64-bit integer vector containing one of the source operands. @@ -2226,7 +2263,7 @@ _mm_min_pu8(__m64 __a, __m64 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c PMOVMSKB instruction. +/// This intrinsic corresponds to the <c> PMOVMSKB </c> instruction. /// /// \param __a /// A 64-bit integer vector containing the values with bits to be extracted. @@ -2244,7 +2281,7 @@ _mm_movemask_pi8(__m64 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c PMULHUW instruction. +/// This intrinsic corresponds to the <c> PMULHUW </c> instruction. /// /// \param __a /// A 64-bit integer vector containing one of the source operands. @@ -2262,27 +2299,31 @@ _mm_mulhi_pu16(__m64 __a, __m64 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c PSHUFW instruction. -/// /// \code /// __m64 _mm_shuffle_pi16(__m64 a, const int n); /// \endcode /// +/// This intrinsic corresponds to the <c> PSHUFW </c> instruction. +/// /// \param a /// A 64-bit integer vector containing the values to be shuffled. /// \param n /// An immediate value containing an 8-bit value specifying which elements to -/// copy from a. The destinations within the 64-bit destination are assigned -/// values as follows: -/// Bits [1:0] are used to assign values to bits [15:0] in the destination. -/// Bits [3:2] are used to assign values to bits [31:16] in the destination. -/// Bits [5:4] are used to assign values to bits [47:32] in the destination. -/// Bits [7:6] are used to assign values to bits [63:48] in the destination. -/// Bit value assignments: -/// 00: assigned from bits [15:0] of a. -/// 01: assigned from bits [31:16] of a. -/// 10: assigned from bits [47:32] of a. -/// 11: assigned from bits [63:48] of a. +/// copy from \a a. The destinations within the 64-bit destination are +/// assigned values as follows: \n +/// Bits [1:0] are used to assign values to bits [15:0] in the +/// destination. \n +/// Bits [3:2] are used to assign values to bits [31:16] in the +/// destination. \n +/// Bits [5:4] are used to assign values to bits [47:32] in the +/// destination. \n +/// Bits [7:6] are used to assign values to bits [63:48] in the +/// destination. \n +/// Bit value assignments: \n +/// 00: assigned from bits [15:0] of \a a. \n +/// 01: assigned from bits [31:16] of \a a. \n +/// 10: assigned from bits [47:32] of \a a. \n +/// 11: assigned from bits [63:48] of \a a. /// \returns A 64-bit integer vector containing the shuffled values. #define _mm_shuffle_pi16(a, n) __extension__ ({ \ (__m64)__builtin_ia32_pshufw((__v4hi)(__m64)(a), (n)); }) @@ -2295,15 +2336,15 @@ _mm_mulhi_pu16(__m64 __a, __m64 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c MASKMOVQ instruction. +/// This intrinsic corresponds to the <c> MASKMOVQ </c> instruction. /// /// \param __d /// A 64-bit integer vector containing the values with elements to be copied. /// \param __n /// A 64-bit integer vector operand. The most significant bit from each 8-bit -/// element determines whether the corresponding element in operand __d is -/// copied. If the most significant bit of a given element is 1, the -/// corresponding element in operand __d is copied. +/// element determines whether the corresponding element in operand \a __d +/// is copied. If the most significant bit of a given element is 1, the +/// corresponding element in operand \a __d is copied. /// \param __p /// A pointer to a 64-bit memory location that will receive the conditionally /// copied integer values. The address of the memory location does not have @@ -2320,7 +2361,7 @@ _mm_maskmove_si64(__m64 __d, __m64 __n, char *__p) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c PAVGB instruction. +/// This intrinsic corresponds to the <c> PAVGB </c> instruction. /// /// \param __a /// A 64-bit integer vector containing one of the source operands. @@ -2339,7 +2380,7 @@ _mm_avg_pu8(__m64 __a, __m64 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c PAVGW instruction. +/// This intrinsic corresponds to the <c> PAVGW </c> instruction. /// /// \param __a /// A 64-bit integer vector containing one of the source operands. @@ -2359,7 +2400,7 @@ _mm_avg_pu16(__m64 __a, __m64 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c PSADBW instruction. +/// This intrinsic corresponds to the <c> PSADBW </c> instruction. /// /// \param __a /// A 64-bit integer vector containing one of the source operands. @@ -2374,24 +2415,42 @@ _mm_sad_pu8(__m64 __a, __m64 __b) return (__m64)__builtin_ia32_psadbw((__v8qi)__a, (__v8qi)__b); } +#if defined(__cplusplus) +extern "C" { +#endif + /// \brief Returns the contents of the MXCSR register as a 32-bit unsigned -/// integer value. There are several groups of macros associated with this +/// integer value. +/// +/// There are several groups of macros associated with this /// intrinsic, including: -/// * For checking exception states: _MM_EXCEPT_INVALID, _MM_EXCEPT_DIV_ZERO, +/// <ul> +/// <li> +/// For checking exception states: _MM_EXCEPT_INVALID, _MM_EXCEPT_DIV_ZERO, /// _MM_EXCEPT_DENORM, _MM_EXCEPT_OVERFLOW, _MM_EXCEPT_UNDERFLOW, /// _MM_EXCEPT_INEXACT. There is a convenience wrapper /// _MM_GET_EXCEPTION_STATE(). -/// * For checking exception masks: _MM_MASK_UNDERFLOW, _MM_MASK_OVERFLOW, +/// </li> +/// <li> +/// For checking exception masks: _MM_MASK_UNDERFLOW, _MM_MASK_OVERFLOW, /// _MM_MASK_INVALID, _MM_MASK_DENORM, _MM_MASK_DIV_ZERO, _MM_MASK_INEXACT. /// There is a convenience wrapper _MM_GET_EXCEPTION_MASK(). -/// * For checking rounding modes: _MM_ROUND_NEAREST, _MM_ROUND_DOWN, +/// </li> +/// <li> +/// For checking rounding modes: _MM_ROUND_NEAREST, _MM_ROUND_DOWN, /// _MM_ROUND_UP, _MM_ROUND_TOWARD_ZERO. There is a convenience wrapper /// _MM_GET_ROUNDING_MODE(x) where x is one of these macros. -/// * For checking flush-to-zero mode: _MM_FLUSH_ZERO_ON, _MM_FLUSH_ZERO_OFF. +/// </li> +/// <li> +/// For checking flush-to-zero mode: _MM_FLUSH_ZERO_ON, _MM_FLUSH_ZERO_OFF. /// There is a convenience wrapper _MM_GET_FLUSH_ZERO_MODE(). -/// * For checking denormals-are-zero mode: _MM_DENORMALS_ZERO_ON, +/// </li> +/// <li> +/// For checking denormals-are-zero mode: _MM_DENORMALS_ZERO_ON, /// _MM_DENORMALS_ZERO_OFF. There is a convenience wrapper /// _MM_GET_DENORMALS_ZERO_MODE(). +/// </li> +/// </ul> /// /// For example, the expression below checks if an overflow exception has /// occurred: @@ -2402,35 +2461,45 @@ _mm_sad_pu8(__m64 __a, __m64 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VSTMXCSR / STMXCSR instruction. +/// This intrinsic corresponds to the <c> VSTMXCSR / STMXCSR </c> instruction. /// /// \returns A 32-bit unsigned integer containing the contents of the MXCSR /// register. -static __inline__ unsigned int __DEFAULT_FN_ATTRS -_mm_getcsr(void) -{ - return __builtin_ia32_stmxcsr(); -} - -/// \brief Sets the MXCSR register with the 32-bit unsigned integer value. There -/// are several groups of macros associated with this intrinsic, including: -/// * For setting exception states: _MM_EXCEPT_INVALID, _MM_EXCEPT_DIV_ZERO, +unsigned int _mm_getcsr(void); + +/// \brief Sets the MXCSR register with the 32-bit unsigned integer value. +/// +/// There are several groups of macros associated with this intrinsic, +/// including: +/// <ul> +/// <li> +/// For setting exception states: _MM_EXCEPT_INVALID, _MM_EXCEPT_DIV_ZERO, /// _MM_EXCEPT_DENORM, _MM_EXCEPT_OVERFLOW, _MM_EXCEPT_UNDERFLOW, /// _MM_EXCEPT_INEXACT. There is a convenience wrapper /// _MM_SET_EXCEPTION_STATE(x) where x is one of these macros. -/// * For setting exception masks: _MM_MASK_UNDERFLOW, _MM_MASK_OVERFLOW, +/// </li> +/// <li> +/// For setting exception masks: _MM_MASK_UNDERFLOW, _MM_MASK_OVERFLOW, /// _MM_MASK_INVALID, _MM_MASK_DENORM, _MM_MASK_DIV_ZERO, _MM_MASK_INEXACT. /// There is a convenience wrapper _MM_SET_EXCEPTION_MASK(x) where x is one /// of these macros. -/// * For setting rounding modes: _MM_ROUND_NEAREST, _MM_ROUND_DOWN, +/// </li> +/// <li> +/// For setting rounding modes: _MM_ROUND_NEAREST, _MM_ROUND_DOWN, /// _MM_ROUND_UP, _MM_ROUND_TOWARD_ZERO. There is a convenience wrapper /// _MM_SET_ROUNDING_MODE(x) where x is one of these macros. -/// * For setting flush-to-zero mode: _MM_FLUSH_ZERO_ON, _MM_FLUSH_ZERO_OFF. +/// </li> +/// <li> +/// For setting flush-to-zero mode: _MM_FLUSH_ZERO_ON, _MM_FLUSH_ZERO_OFF. /// There is a convenience wrapper _MM_SET_FLUSH_ZERO_MODE(x) where x is /// one of these macros. -/// * For setting denormals-are-zero mode: _MM_DENORMALS_ZERO_ON, +/// </li> +/// <li> +/// For setting denormals-are-zero mode: _MM_DENORMALS_ZERO_ON, /// _MM_DENORMALS_ZERO_OFF. There is a convenience wrapper /// _MM_SET_DENORMALS_ZERO_MODE(x) where x is one of these macros. +/// </li> +/// </ul> /// /// For example, the following expression causes subsequent floating-point /// operations to round up: @@ -2444,15 +2513,15 @@ _mm_getcsr(void) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VLDMXCSR / LDMXCSR instruction. +/// This intrinsic corresponds to the <c> VLDMXCSR / LDMXCSR </c> instruction. /// /// \param __i /// A 32-bit unsigned integer value to be written to the MXCSR register. -static __inline__ void __DEFAULT_FN_ATTRS -_mm_setcsr(unsigned int __i) -{ - __builtin_ia32_ldmxcsr(__i); -} +void _mm_setcsr(unsigned int); + +#if defined(__cplusplus) +} // extern "C" +#endif /// \brief Selects 4 float values from the 128-bit operands of [4 x float], as /// specified by the immediate value operand. @@ -2463,7 +2532,7 @@ _mm_setcsr(unsigned int __i) /// __m128 _mm_shuffle_ps(__m128 a, __m128 b, const int mask); /// \endcode /// -/// This intrinsic corresponds to the \c VSHUFPS / SHUFPS instruction. +/// This intrinsic corresponds to the <c> VSHUFPS / SHUFPS </c> instruction. /// /// \param a /// A 128-bit vector of [4 x float]. @@ -2471,18 +2540,23 @@ _mm_setcsr(unsigned int __i) /// A 128-bit vector of [4 x float]. /// \param mask /// An immediate value containing an 8-bit value specifying which elements to -/// copy from a and b. -/// Bits [3:0] specify the values copied from operand a. -/// Bits [7:4] specify the values copied from operand b. The destinations -/// within the 128-bit destination are assigned values as follows: -/// Bits [1:0] are used to assign values to bits [31:0] in the destination. -/// Bits [3:2] are used to assign values to bits [63:32] in the destination. -/// Bits [5:4] are used to assign values to bits [95:64] in the destination. -/// Bits [7:6] are used to assign values to bits [127:96] in the destination. -/// Bit value assignments: -/// 00: Bits [31:0] copied from the specified operand. -/// 01: Bits [63:32] copied from the specified operand. -/// 10: Bits [95:64] copied from the specified operand. +/// copy from \ a and \a b. \n +/// Bits [3:0] specify the values copied from operand \a a. \n +/// Bits [7:4] specify the values copied from operand \a b. \n +/// The destinations within the 128-bit destination are assigned values as +/// follows: \n +/// Bits [1:0] are used to assign values to bits [31:0] in the +/// destination. \n +/// Bits [3:2] are used to assign values to bits [63:32] in the +/// destination. \n +/// Bits [5:4] are used to assign values to bits [95:64] in the +/// destination. \n +/// Bits [7:6] are used to assign values to bits [127:96] in the +/// destination. \n +/// Bit value assignments: \n +/// 00: Bits [31:0] copied from the specified operand. \n +/// 01: Bits [63:32] copied from the specified operand. \n +/// 10: Bits [95:64] copied from the specified operand. \n /// 11: Bits [127:96] copied from the specified operand. /// \returns A 128-bit vector of [4 x float] containing the shuffled values. #define _mm_shuffle_ps(a, b, mask) __extension__ ({ \ @@ -2493,20 +2567,19 @@ _mm_setcsr(unsigned int __i) 4 + (((mask) >> 6) & 0x3)); }) /// \brief Unpacks the high-order (index 2,3) values from two 128-bit vectors of -/// [4 x float] and interleaves them into a 128-bit vector of [4 x -/// float]. +/// [4 x float] and interleaves them into a 128-bit vector of [4 x float]. /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VUNPCKHPS / UNPCKHPS instruction. +/// This intrinsic corresponds to the <c> VUNPCKHPS / UNPCKHPS </c> instruction. /// /// \param __a -/// A 128-bit vector of [4 x float]. -/// Bits [95:64] are written to bits [31:0] of the destination. +/// A 128-bit vector of [4 x float]. \n +/// Bits [95:64] are written to bits [31:0] of the destination. \n /// Bits [127:96] are written to bits [95:64] of the destination. /// \param __b /// A 128-bit vector of [4 x float]. -/// Bits [95:64] are written to bits [63:32] of the destination. +/// Bits [95:64] are written to bits [63:32] of the destination. \n /// Bits [127:96] are written to bits [127:96] of the destination. /// \returns A 128-bit vector of [4 x float] containing the interleaved values. static __inline__ __m128 __DEFAULT_FN_ATTRS @@ -2516,20 +2589,19 @@ _mm_unpackhi_ps(__m128 __a, __m128 __b) } /// \brief Unpacks the low-order (index 0,1) values from two 128-bit vectors of -/// [4 x float] and interleaves them into a 128-bit vector of [4 x -/// float]. +/// [4 x float] and interleaves them into a 128-bit vector of [4 x float]. /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VUNPCKLPS / UNPCKLPS instruction. +/// This intrinsic corresponds to the <c> VUNPCKLPS / UNPCKLPS </c> instruction. /// /// \param __a -/// A 128-bit vector of [4 x float]. -/// Bits [31:0] are written to bits [31:0] of the destination. +/// A 128-bit vector of [4 x float]. \n +/// Bits [31:0] are written to bits [31:0] of the destination. \n /// Bits [63:32] are written to bits [95:64] of the destination. /// \param __b -/// A 128-bit vector of [4 x float]. -/// Bits [31:0] are written to bits [63:32] of the destination. +/// A 128-bit vector of [4 x float]. \n +/// Bits [31:0] are written to bits [63:32] of the destination. \n /// Bits [63:32] are written to bits [127:96] of the destination. /// \returns A 128-bit vector of [4 x float] containing the interleaved values. static __inline__ __m128 __DEFAULT_FN_ATTRS @@ -2544,7 +2616,7 @@ _mm_unpacklo_ps(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMOVSS / MOVSS instruction. +/// This intrinsic corresponds to the <c> VMOVSS / MOVSS </c> instruction. /// /// \param __a /// A 128-bit floating-point vector of [4 x float]. The upper 96 bits are @@ -2565,7 +2637,7 @@ _mm_move_ss(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VUNPCKHPD / UNPCKHPD instruction. +/// This intrinsic corresponds to the <c> VUNPCKHPD / UNPCKHPD </c> instruction. /// /// \param __a /// A 128-bit floating-point vector of [4 x float]. The upper 64 bits are @@ -2586,7 +2658,7 @@ _mm_movehl_ps(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VUNPCKLPD / UNPCKLPD instruction. +/// This intrinsic corresponds to the <c> VUNPCKLPD / UNPCKLPD </c> instruction. /// /// \param __a /// A 128-bit floating-point vector of [4 x float]. The lower 64 bits are @@ -2606,7 +2678,8 @@ _mm_movelh_ps(__m128 __a, __m128 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c CVTPI2PS + \c COMPOSITE instruction. +/// This intrinsic corresponds to the <c> CVTPI2PS + \c COMPOSITE </c> +/// instruction. /// /// \param __a /// A 64-bit vector of [4 x i16]. The elements of the destination are copied @@ -2636,7 +2709,8 @@ _mm_cvtpi16_ps(__m64 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c CVTPI2PS + \c COMPOSITE instruction. +/// This intrinsic corresponds to the <c> CVTPI2PS + \c COMPOSITE </c> +/// instruction. /// /// \param __a /// A 64-bit vector of 16-bit unsigned integer values. The elements of the @@ -2665,7 +2739,8 @@ _mm_cvtpu16_ps(__m64 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c CVTPI2PS + \c COMPOSITE instruction. +/// This intrinsic corresponds to the <c> CVTPI2PS + \c COMPOSITE </c> +/// instruction. /// /// \param __a /// A 64-bit vector of [8 x i8]. The elements of the destination are copied @@ -2689,7 +2764,8 @@ _mm_cvtpi8_ps(__m64 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c CVTPI2PS + \c COMPOSITE instruction. +/// This intrinsic corresponds to the <c> CVTPI2PS + \c COMPOSITE </c> +/// instruction. /// /// \param __a /// A 64-bit vector of unsigned 8-bit integer values. The elements of the @@ -2713,7 +2789,8 @@ _mm_cvtpu8_ps(__m64 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c CVTPI2PS + \c COMPOSITE instruction. +/// This intrinsic corresponds to the <c> CVTPI2PS + \c COMPOSITE </c> +/// instruction. /// /// \param __a /// A 64-bit vector of [2 x i32]. The lower elements of the destination are @@ -2741,12 +2818,13 @@ _mm_cvtpi32x2_ps(__m64 __a, __m64 __b) /// packs the results into a 64-bit integer vector of [4 x i16]. If the /// floating-point element is NaN or infinity, or if the floating-point /// element is greater than 0x7FFFFFFF or less than -0x8000, it is converted -/// to 0x8000. Otherwise if the floating-point element is greater -/// than 0x7FFF, it is converted to 0x7FFF. +/// to 0x8000. Otherwise if the floating-point element is greater than +/// 0x7FFF, it is converted to 0x7FFF. /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c CVTPS2PI + \c COMPOSITE instruction. +/// This intrinsic corresponds to the <c> CVTPS2PI + \c COMPOSITE </c> +/// instruction. /// /// \param __a /// A 128-bit floating-point vector of [4 x float]. @@ -2770,12 +2848,13 @@ _mm_cvtps_pi16(__m128 __a) /// [8 x i8]. The upper 32 bits of the vector are set to 0. If the /// floating-point element is NaN or infinity, or if the floating-point /// element is greater than 0x7FFFFFFF or less than -0x80, it is converted -/// to 0x80. Otherwise if the floating-point element is greater -/// than 0x7F, it is converted to 0x7F. +/// to 0x80. Otherwise if the floating-point element is greater than 0x7F, +/// it is converted to 0x7F. /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c CVTPS2PI + \c COMPOSITE instruction. +/// This intrinsic corresponds to the <c> CVTPS2PI + \c COMPOSITE </c> +/// instruction. /// /// \param __a /// 128-bit floating-point vector of [4 x float]. @@ -2799,7 +2878,7 @@ _mm_cvtps_pi8(__m128 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMOVMSKPS / MOVMSKPS instruction. +/// This intrinsic corresponds to the <c> VMOVMSKPS / MOVMSKPS </c> instruction. /// /// \param __a /// A 128-bit floating-point vector of [4 x float]. |