diff options
Diffstat (limited to 'lib/Target/AMDGPU/SIISelLowering.h')
| -rw-r--r-- | lib/Target/AMDGPU/SIISelLowering.h | 38 |
1 files changed, 32 insertions, 6 deletions
diff --git a/lib/Target/AMDGPU/SIISelLowering.h b/lib/Target/AMDGPU/SIISelLowering.h index b48e67f7563a..ad049f2a71c3 100644 --- a/lib/Target/AMDGPU/SIISelLowering.h +++ b/lib/Target/AMDGPU/SIISelLowering.h @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief SI DAG Lowering interface definition +/// SI DAG Lowering interface definition // //===----------------------------------------------------------------------===// @@ -22,12 +22,15 @@ namespace llvm { class SITargetLowering final : public AMDGPUTargetLowering { +private: + const GCNSubtarget *Subtarget; + SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL, SDValue Chain, uint64_t Offset) const; SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const; SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Chain, - uint64_t Offset, bool Signed, + uint64_t Offset, unsigned Align, bool Signed, const ISD::InputArg *Arg = nullptr) const; SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA, @@ -42,10 +45,14 @@ class SITargetLowering final : public AMDGPUTargetLowering { SelectionDAG &DAG) const override; SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op, MVT VT, unsigned Offset) const; + SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr, + SelectionDAG &DAG) const; SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; + + SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const; SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const; @@ -60,7 +67,13 @@ class SITargetLowering final : public AMDGPUTargetLowering { SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; - /// \brief Converts \p Op, which must be of floating point type, to the + SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M, + SelectionDAG &DAG, + bool IsIntrinsic = false) const; + + SDValue handleD16VData(SDValue VData, SelectionDAG &DAG) const; + + /// Converts \p Op, which must be of floating point type, to the /// floating point type \p VT, by either extending or truncating it. SDValue getFPExtOrFPTrunc(SelectionDAG &DAG, SDValue Op, @@ -71,7 +84,7 @@ class SITargetLowering final : public AMDGPUTargetLowering { SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val, bool Signed, const ISD::InputArg *Arg = nullptr) const; - /// \brief Custom lowering for ISD::FP_ROUND for MVT::f16. + /// Custom lowering for ISD::FP_ROUND for MVT::f16. SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; SDValue getSegmentAperture(unsigned AS, const SDLoc &DL, @@ -80,7 +93,9 @@ class SITargetLowering final : public AMDGPUTargetLowering { SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const; SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const; SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const; @@ -121,8 +136,11 @@ class SITargetLowering final : public AMDGPUTargetLowering { SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; + SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const; + SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const; + SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const; bool isLegalFlatAddressingMode(const AddrMode &AM) const; bool isLegalGlobalAddressingMode(const AddrMode &AM) const; @@ -145,9 +163,11 @@ class SITargetLowering final : public AMDGPUTargetLowering { bool shouldEmitPCReloc(const GlobalValue *GV) const; public: - SITargetLowering(const TargetMachine &tm, const SISubtarget &STI); + SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI); - const SISubtarget *getSubtarget() const; + const GCNSubtarget *getSubtarget() const; + + bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const override; bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override; @@ -255,7 +275,10 @@ public: EVT VT) const override; MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override; bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; + SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const; + SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const; SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; + void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const override; @@ -284,6 +307,9 @@ public: const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth = 0) const override; + + bool isSDNodeSourceOfDivergence(const SDNode *N, + FunctionLoweringInfo *FLI, DivergenceAnalysis *DA) const override; }; } // End namespace llvm |