diff options
Diffstat (limited to 'lib/Target/ARM/ARMInstrThumb.td')
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb.td | 28 |
1 files changed, 18 insertions, 10 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index e17f73af03ec..cc953c637cb4 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -311,7 +311,7 @@ def tHLT : T1I<(outs), (ins imm0_63:$val), NoItinerary, "hlt\t$val", } def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end", - []>, T1Encoding<0b101101>, Deprecated<HasV8Ops> { + []>, T1Encoding<0b101101>, Requires<[IsNotMClass]>, Deprecated<HasV8Ops> { bits<1> end; // A8.6.156 let Inst{9-5} = 0b10010; @@ -360,6 +360,14 @@ def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm), let DecoderMethod = "DecodeThumbAddSpecialReg"; } +// Thumb1 frame lowering is rather fragile, we hope to be able to use +// tADDrSPi, but we may need to insert a sequence that clobbers CPSR. +def tADDframe : PseudoInst<(outs tGPR:$dst), (ins i32imm:$base, i32imm:$offset), + NoItinerary, []>, + Requires<[IsThumb, IsThumb1Only]> { + let Defs = [CPSR]; +} + // ADD sp, sp, #<imm7> def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), IIC_iALUi, "add", "\t$Rdn, $imm", []>, @@ -466,7 +474,7 @@ let isCall = 1, (outs), (ins pred:$p, t_blxtarget:$func), IIC_Br, "blx${p}\t$func", [(ARMcall tglobaladdr:$func)]>, - Requires<[IsThumb, HasV5T]>, Sched<[WriteBrL]> { + Requires<[IsThumb, HasV5T, IsNotMClass]>, Sched<[WriteBrL]> { bits<24> func; let Inst{26} = func{23}; let Inst{25-16} = func{20-11}; @@ -706,7 +714,7 @@ def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i, // // These require base address to be written back or one of the loaded regs. -let neverHasSideEffects = 1 in { +let hasSideEffects = 0 in { let mayLoad = 1, hasExtraDefRegAllocReq = 1 in def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), @@ -746,7 +754,7 @@ def tSTMIA_UPD : Thumb1I<(outs GPR:$wb), let Inst{7-0} = regs; } -} // neverHasSideEffects +} // hasSideEffects def : InstAlias<"ldm${p} $Rn!, $regs", (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>, @@ -880,7 +888,7 @@ def tADDrr : // A8.6.6 T1 "add", "\t$Rd, $Rn, $Rm", [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; -let neverHasSideEffects = 1 in +let hasSideEffects = 0 in def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr, "add", "\t$Rdn, $Rm", []>, T1Special<{0,0,?,?}>, Sched<[WriteALU]> { @@ -1040,7 +1048,7 @@ def : tInstAlias <"movs $Rdn, $imm", // A7-73: MOV(2) - mov setting flag. -let neverHasSideEffects = 1 in { +let hasSideEffects = 0 in { def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone, 2, IIC_iMOVr, "mov", "\t$Rd, $Rm", "", []>, @@ -1062,7 +1070,7 @@ def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr, let Inst{5-3} = Rm; let Inst{2-0} = Rd; } -} // neverHasSideEffects +} // hasSideEffects // Multiply register let isCommutable = 1 in @@ -1240,7 +1248,7 @@ def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p), let DecoderMethod = "DecodeThumbAddSpecialReg"; } -let neverHasSideEffects = 1, isReMaterializable = 1 in +let hasSideEffects = 0, isReMaterializable = 1 in def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p), 2, IIC_iALUi, []>, Sched<[WriteALU]>; @@ -1289,7 +1297,7 @@ def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch), AddrModeNone, 0, IndexModeNone, Pseudo, NoItinerary, "", "", [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, - Requires<[IsThumb, IsIOS]>; + Requires<[IsThumb]>; //===----------------------------------------------------------------------===// // Non-Instruction Patterns @@ -1355,7 +1363,7 @@ def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>, Requires<[IsThumb]>; def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>, - Requires<[IsThumb, HasV5T]>; + Requires<[IsThumb, HasV5T, IsNotMClass]>; // Indirect calls to ARM routines def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>, |