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-rw-r--r--lib/Target/ARM/ARMScheduleA9.td4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td
index 21d32bde4710..3f0b71afd977 100644
--- a/lib/Target/ARM/ARMScheduleA9.td
+++ b/lib/Target/ARM/ARMScheduleA9.td
@@ -2239,9 +2239,9 @@ def A9WriteLMfpPostRA : SchedWriteVariant<[
// Distinguish between our multiple MI-level forms of the same
// VLDM/VSTM instructions.
def A9PreRA : SchedPredicate<
- "TargetRegisterInfo::isVirtualRegister(MI->getOperand(0).getReg())">;
+ "Register::isVirtualRegister(MI->getOperand(0).getReg())">;
def A9PostRA : SchedPredicate<
- "TargetRegisterInfo::isPhysicalRegister(MI->getOperand(0).getReg())">;
+ "Register::isPhysicalRegister(MI->getOperand(0).getReg())">;
// VLDM represents all destination registers as a single register
// tuple, unlike LDM. So the number of write operands is not variadic.