diff options
Diffstat (limited to 'lib/Target/Blackfin/BlackfinInstrInfo.cpp')
-rw-r--r-- | lib/Target/Blackfin/BlackfinInstrInfo.cpp | 108 |
1 files changed, 55 insertions, 53 deletions
diff --git a/lib/Target/Blackfin/BlackfinInstrInfo.cpp b/lib/Target/Blackfin/BlackfinInstrInfo.cpp index 73924b750a1c..a74d42d59549 100644 --- a/lib/Target/Blackfin/BlackfinInstrInfo.cpp +++ b/lib/Target/Blackfin/BlackfinInstrInfo.cpp @@ -104,10 +104,8 @@ unsigned BlackfinInstrInfo:: InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl<MachineOperand> &Cond) const { - // FIXME this should probably have a DebugLoc operand - DebugLoc DL; - + const SmallVectorImpl<MachineOperand> &Cond, + DebugLoc DL) const { // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 1 || Cond.size() == 0) && @@ -124,69 +122,73 @@ InsertBranch(MachineBasicBlock &MBB, llvm_unreachable("Implement conditional branches!"); } -static bool inClass(const TargetRegisterClass &Test, - unsigned Reg, - const TargetRegisterClass *RC) { - if (TargetRegisterInfo::isPhysicalRegister(Reg)) - return Test.contains(Reg); - else - return &Test==RC || Test.hasSubClass(RC); -} - -bool BlackfinInstrInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned DestReg, - unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC, - DebugLoc DL) const { - if (inClass(BF::ALLRegClass, DestReg, DestRC) && - inClass(BF::ALLRegClass, SrcReg, SrcRC)) { - BuildMI(MBB, I, DL, get(BF::MOVE), DestReg).addReg(SrcReg); - return true; +void BlackfinInstrInfo::copyPhysReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, DebugLoc DL, + unsigned DestReg, unsigned SrcReg, + bool KillSrc) const { + if (BF::ALLRegClass.contains(DestReg, SrcReg)) { + BuildMI(MBB, I, DL, get(BF::MOVE), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)); + return; } - if (inClass(BF::D16RegClass, DestReg, DestRC) && - inClass(BF::D16RegClass, SrcReg, SrcRC)) { - BuildMI(MBB, I, DL, get(BF::SLL16i), DestReg).addReg(SrcReg).addImm(0); - return true; + if (BF::D16RegClass.contains(DestReg, SrcReg)) { + BuildMI(MBB, I, DL, get(BF::SLL16i), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)) + .addImm(0); + return; } - if (inClass(BF::AnyCCRegClass, SrcReg, SrcRC) && - inClass(BF::DRegClass, DestReg, DestRC)) { - if (inClass(BF::NotCCRegClass, SrcReg, SrcRC)) { - BuildMI(MBB, I, DL, get(BF::MOVENCC_z), DestReg).addReg(SrcReg); + if (BF::DRegClass.contains(DestReg)) { + if (SrcReg == BF::NCC) { + BuildMI(MBB, I, DL, get(BF::MOVENCC_z), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)); BuildMI(MBB, I, DL, get(BF::BITTGL), DestReg).addReg(DestReg).addImm(0); - } else { - BuildMI(MBB, I, DL, get(BF::MOVECC_zext), DestReg).addReg(SrcReg); + return; + } + if (SrcReg == BF::CC) { + BuildMI(MBB, I, DL, get(BF::MOVECC_zext), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)); + return; } - return true; } - if (inClass(BF::AnyCCRegClass, DestReg, DestRC) && - inClass(BF::DRegClass, SrcReg, SrcRC)) { - if (inClass(BF::NotCCRegClass, DestReg, DestRC)) - BuildMI(MBB, I, DL, get(BF::SETEQri_not), DestReg).addReg(SrcReg); - else - BuildMI(MBB, I, DL, get(BF::MOVECC_nz), DestReg).addReg(SrcReg); - return true; + if (BF::DRegClass.contains(SrcReg)) { + if (DestReg == BF::NCC) { + BuildMI(MBB, I, DL, get(BF::SETEQri_not), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)).addImm(0); + return; + } + if (DestReg == BF::CC) { + BuildMI(MBB, I, DL, get(BF::MOVECC_nz), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)); + return; + } } - if (inClass(BF::NotCCRegClass, DestReg, DestRC) && - inClass(BF::JustCCRegClass, SrcReg, SrcRC)) { - BuildMI(MBB, I, DL, get(BF::MOVE_ncccc), DestReg).addReg(SrcReg); - return true; + + if (DestReg == BF::NCC && SrcReg == BF::CC) { + BuildMI(MBB, I, DL, get(BF::MOVE_ncccc), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)); + return; } - if (inClass(BF::JustCCRegClass, DestReg, DestRC) && - inClass(BF::NotCCRegClass, SrcReg, SrcRC)) { - BuildMI(MBB, I, DL, get(BF::MOVE_ccncc), DestReg).addReg(SrcReg); - return true; + if (DestReg == BF::CC && SrcReg == BF::NCC) { + BuildMI(MBB, I, DL, get(BF::MOVE_ccncc), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)); + return; } - llvm_unreachable((std::string("Bad regclasses for reg-to-reg copy: ")+ - SrcRC->getName() + " -> " + DestRC->getName()).c_str()); - return false; + llvm_unreachable("Bad reg-to-reg copy"); +} + +static bool inClass(const TargetRegisterClass &Test, + unsigned Reg, + const TargetRegisterClass *RC) { + if (TargetRegisterInfo::isPhysicalRegister(Reg)) + return Test.contains(Reg); + else + return &Test==RC || Test.hasSubClass(RC); } void |