diff options
Diffstat (limited to 'lib/Target/Mips/Disassembler/MipsDisassembler.cpp')
| -rw-r--r-- | lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 510 |
1 files changed, 289 insertions, 221 deletions
diff --git a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index d42b948cc615..eb97c93ac196 100644 --- a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -30,41 +30,22 @@ typedef MCDisassembler::DecodeStatus DecodeStatus; namespace { -/// A disasembler class for Mips. -class MipsDisassemblerBase : public MCDisassembler { +class MipsDisassembler : public MCDisassembler { + bool IsMicroMips; + bool IsBigEndian; public: - MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx, - bool IsBigEndian) + MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) : MCDisassembler(STI, Ctx), - IsGP64Bit(STI.getFeatureBits() & Mips::FeatureGP64Bit), + IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), IsBigEndian(IsBigEndian) {} - virtual ~MipsDisassemblerBase() {} - - bool isGP64Bit() const { return IsGP64Bit; } - -private: - bool IsGP64Bit; -protected: - bool IsBigEndian; -}; - -/// A disasembler class for Mips32. -class MipsDisassembler : public MipsDisassemblerBase { - bool IsMicroMips; -public: - MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian) - : MipsDisassemblerBase(STI, Ctx, bigEndian) { - IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips; - } - - bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; } - bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; } + bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } + bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } bool hasMips32r6() const { - return STI.getFeatureBits() & Mips::FeatureMips32r6; + return STI.getFeatureBits()[Mips::FeatureMips32r6]; } - bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; } + bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } bool hasCOP3() const { // Only present in MIPS-I and MIPS-II @@ -77,19 +58,6 @@ public: raw_ostream &CStream) const override; }; -/// A disasembler class for Mips64. -class Mips64Disassembler : public MipsDisassemblerBase { -public: - Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx, - bool bigEndian) : - MipsDisassemblerBase(STI, Ctx, bigEndian) {} - - DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, - ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &VStream, - raw_ostream &CStream) const override; -}; - } // end anonymous namespace // Forward declare these because the autogenerated code will reference them. @@ -114,6 +82,11 @@ static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, @@ -235,6 +208,13 @@ static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, uint64_t Address, const void *Decoder); +// DecodeBranchTarget10MM - Decode microMIPS branch offset, which is +// shifted left by 1 bit. +static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, + unsigned Offset, + uint64_t Address, + const void *Decoder); + // DecodeBranchTargetMM - Decode microMIPS branch offset, which is // shifted left by 1 bit. static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, @@ -287,6 +267,16 @@ static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, @@ -375,6 +365,9 @@ static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't /// handle. template <typename InsnType> @@ -419,6 +412,10 @@ static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); + namespace llvm { extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, TheMips64elTarget; @@ -438,20 +435,6 @@ static MCDisassembler *createMipselDisassembler( return new MipsDisassembler(STI, Ctx, false); } -static MCDisassembler *createMips64Disassembler( - const Target &T, - const MCSubtargetInfo &STI, - MCContext &Ctx) { - return new Mips64Disassembler(STI, Ctx, true); -} - -static MCDisassembler *createMips64elDisassembler( - const Target &T, - const MCSubtargetInfo &STI, - MCContext &Ctx) { - return new Mips64Disassembler(STI, Ctx, false); -} - extern "C" void LLVMInitializeMipsDisassembler() { // Register the disassembler. TargetRegistry::RegisterMCDisassembler(TheMipsTarget, @@ -459,15 +442,15 @@ extern "C" void LLVMInitializeMipsDisassembler() { TargetRegistry::RegisterMCDisassembler(TheMipselTarget, createMipselDisassembler); TargetRegistry::RegisterMCDisassembler(TheMips64Target, - createMips64Disassembler); + createMipsDisassembler); TargetRegistry::RegisterMCDisassembler(TheMips64elTarget, - createMips64elDisassembler); + createMipselDisassembler); } #include "MipsGenDisassemblerTables.inc" static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { - const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D); + const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); return *(RegInfo->getRegClass(RC).begin() + RegNo); } @@ -507,13 +490,13 @@ static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, return MCDisassembler::Fail; // $n tmp = fieldFromInstruction(insn, 16, NSize); - MI.addOperand(MCOperand::CreateImm(tmp)); + MI.addOperand(MCOperand::createImm(tmp)); // $ws tmp = fieldFromInstruction(insn, 11, 5); if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) return MCDisassembler::Fail; // $n2 - MI.addOperand(MCOperand::CreateImm(0)); + MI.addOperand(MCOperand::createImm(0)); return MCDisassembler::Success; } @@ -547,12 +530,12 @@ static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, MI.setOpcode(Mips::BEQZALC); if (HasRs) - MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); - MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); - MI.addOperand(MCOperand::CreateImm(Imm)); + MI.addOperand(MCOperand::createImm(Imm)); return MCDisassembler::Success; } @@ -586,12 +569,12 @@ static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, MI.setOpcode(Mips::BNEZALC); if (HasRs) - MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); - MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); - MI.addOperand(MCOperand::CreateImm(Imm)); + MI.addOperand(MCOperand::createImm(Imm)); return MCDisassembler::Success; } @@ -628,13 +611,13 @@ static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, } if (HasRs) - MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); - MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); - MI.addOperand(MCOperand::CreateImm(Imm)); + MI.addOperand(MCOperand::createImm(Imm)); return MCDisassembler::Success; } @@ -672,13 +655,13 @@ static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, } if (HasRs) - MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); - MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); - MI.addOperand(MCOperand::CreateImm(Imm)); + MI.addOperand(MCOperand::createImm(Imm)); return MCDisassembler::Success; } @@ -720,14 +703,14 @@ static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, } if (HasRs) - MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); if (HasRt) - MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); - MI.addOperand(MCOperand::CreateImm(Imm)); + MI.addOperand(MCOperand::createImm(Imm)); return MCDisassembler::Success; } @@ -764,12 +747,12 @@ static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, } if (HasRs) - MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); - MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); - MI.addOperand(MCOperand::CreateImm(Imm)); + MI.addOperand(MCOperand::createImm(Imm)); return MCDisassembler::Success; } @@ -854,10 +837,17 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, if (Result == MCDisassembler::Fail) return MCDisassembler::Fail; - DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); - // Calling the auto-generated decoder function. - Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, - this, STI); + if (hasMips32r6()) { + DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); + // Calling the auto-generated decoder function. + Result = decodeInstruction(DecoderTableMicroMips32r632, Instr, Insn, Address, + this, STI); + } else { + DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); + // Calling the auto-generated decoder function. + Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, + this, STI); + } if (Result != MCDisassembler::Fail) { Size = 4; return Result; @@ -899,39 +889,19 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, } } - DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); - // Calling the auto-generated decoder function. - Result = - decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); - if (Result != MCDisassembler::Fail) { - Size = 4; - return Result; + if (isGP64()) { + DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, + Address, this, STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } } - return MCDisassembler::Fail; -} - -DecodeStatus Mips64Disassembler::getInstruction(MCInst &Instr, uint64_t &Size, - ArrayRef<uint8_t> Bytes, - uint64_t Address, - raw_ostream &VStream, - raw_ostream &CStream) const { - uint32_t Insn; - - DecodeStatus Result = - readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); - if (Result == MCDisassembler::Fail) - return MCDisassembler::Fail; - + DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); // Calling the auto-generated decoder function. Result = - decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI); - if (Result != MCDisassembler::Fail) { - Size = 4; - return Result; - } - // If we fail to decode in Mips64 decoder space we can try in Mips32 - Result = decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) { Size = 4; @@ -959,7 +929,7 @@ static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -970,7 +940,7 @@ static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, if (RegNo > 7) return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -981,7 +951,18 @@ static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, if (RegNo > 7) return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + +static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo > 7) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); + Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -992,7 +973,7 @@ static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, if (RegNo > 31) return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -1000,7 +981,7 @@ static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { - if (static_cast<const MipsDisassembler *>(Decoder)->isGP64Bit()) + if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); @@ -1021,7 +1002,7 @@ static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -1033,7 +1014,7 @@ static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -1044,7 +1025,7 @@ static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, if (RegNo > 31) return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -1055,7 +1036,7 @@ static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, if (RegNo > 7) return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -1066,7 +1047,7 @@ static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -1083,12 +1064,12 @@ static DecodeStatus DecodeMem(MCInst &Inst, if(Inst.getOpcode() == Mips::SC || Inst.getOpcode() == Mips::SCD){ - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); } - Inst.addOperand(MCOperand::CreateReg(Reg)); - Inst.addOperand(MCOperand::CreateReg(Base)); - Inst.addOperand(MCOperand::CreateImm(Offset)); + Inst.addOperand(MCOperand::createReg(Reg)); + Inst.addOperand(MCOperand::createReg(Base)); + Inst.addOperand(MCOperand::createImm(Offset)); return MCDisassembler::Success; } @@ -1103,9 +1084,9 @@ static DecodeStatus DecodeCacheOp(MCInst &Inst, Base = getReg(Decoder, Mips::GPR32RegClassID, Base); - Inst.addOperand(MCOperand::CreateReg(Base)); - Inst.addOperand(MCOperand::CreateImm(Offset)); - Inst.addOperand(MCOperand::CreateImm(Hint)); + Inst.addOperand(MCOperand::createReg(Base)); + Inst.addOperand(MCOperand::createImm(Offset)); + Inst.addOperand(MCOperand::createImm(Hint)); return MCDisassembler::Success; } @@ -1120,9 +1101,9 @@ static DecodeStatus DecodeCacheOpMM(MCInst &Inst, Base = getReg(Decoder, Mips::GPR32RegClassID, Base); - Inst.addOperand(MCOperand::CreateReg(Base)); - Inst.addOperand(MCOperand::CreateImm(Offset)); - Inst.addOperand(MCOperand::CreateImm(Hint)); + Inst.addOperand(MCOperand::createReg(Base)); + Inst.addOperand(MCOperand::createImm(Offset)); + Inst.addOperand(MCOperand::createImm(Hint)); return MCDisassembler::Success; } @@ -1137,9 +1118,9 @@ static DecodeStatus DecodeCacheOpR6(MCInst &Inst, Base = getReg(Decoder, Mips::GPR32RegClassID, Base); - Inst.addOperand(MCOperand::CreateReg(Base)); - Inst.addOperand(MCOperand::CreateImm(Offset)); - Inst.addOperand(MCOperand::CreateImm(Hint)); + Inst.addOperand(MCOperand::createReg(Base)); + Inst.addOperand(MCOperand::createImm(Offset)); + Inst.addOperand(MCOperand::createImm(Hint)); return MCDisassembler::Success; } @@ -1153,8 +1134,8 @@ static DecodeStatus DecodeSyncI(MCInst &Inst, Base = getReg(Decoder, Mips::GPR32RegClassID, Base); - Inst.addOperand(MCOperand::CreateReg(Base)); - Inst.addOperand(MCOperand::CreateImm(Offset)); + Inst.addOperand(MCOperand::createReg(Base)); + Inst.addOperand(MCOperand::createImm(Offset)); return MCDisassembler::Success; } @@ -1168,8 +1149,8 @@ static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); Base = getReg(Decoder, Mips::GPR32RegClassID, Base); - Inst.addOperand(MCOperand::CreateReg(Reg)); - Inst.addOperand(MCOperand::CreateReg(Base)); + Inst.addOperand(MCOperand::createReg(Reg)); + Inst.addOperand(MCOperand::createReg(Base)); // The immediate field of an LD/ST instruction is scaled which means it must // be multiplied (when decoding) by the size (in bytes) of the instructions' @@ -1186,19 +1167,19 @@ static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, break; case Mips::LD_B: case Mips::ST_B: - Inst.addOperand(MCOperand::CreateImm(Offset)); + Inst.addOperand(MCOperand::createImm(Offset)); break; case Mips::LD_H: case Mips::ST_H: - Inst.addOperand(MCOperand::CreateImm(Offset * 2)); + Inst.addOperand(MCOperand::createImm(Offset * 2)); break; case Mips::LD_W: case Mips::ST_W: - Inst.addOperand(MCOperand::CreateImm(Offset * 4)); + Inst.addOperand(MCOperand::createImm(Offset * 4)); break; case Mips::LD_D: case Mips::ST_D: - Inst.addOperand(MCOperand::CreateImm(Offset * 8)); + Inst.addOperand(MCOperand::createImm(Offset * 8)); break; } @@ -1237,20 +1218,20 @@ static DecodeStatus DecodeMemMMImm4(MCInst &Inst, switch (Inst.getOpcode()) { case Mips::LBU16_MM: if (Offset == 0xf) - Inst.addOperand(MCOperand::CreateImm(-1)); + Inst.addOperand(MCOperand::createImm(-1)); else - Inst.addOperand(MCOperand::CreateImm(Offset)); + Inst.addOperand(MCOperand::createImm(Offset)); break; case Mips::SB16_MM: - Inst.addOperand(MCOperand::CreateImm(Offset)); + Inst.addOperand(MCOperand::createImm(Offset)); break; case Mips::LHU16_MM: case Mips::SH16_MM: - Inst.addOperand(MCOperand::CreateImm(Offset << 1)); + Inst.addOperand(MCOperand::createImm(Offset << 1)); break; case Mips::LW16_MM: case Mips::SW16_MM: - Inst.addOperand(MCOperand::CreateImm(Offset << 2)); + Inst.addOperand(MCOperand::createImm(Offset << 2)); break; } @@ -1266,9 +1247,41 @@ static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); - Inst.addOperand(MCOperand::CreateReg(Reg)); - Inst.addOperand(MCOperand::CreateReg(Mips::SP)); - Inst.addOperand(MCOperand::CreateImm(Offset << 2)); + Inst.addOperand(MCOperand::createReg(Reg)); + Inst.addOperand(MCOperand::createReg(Mips::SP)); + Inst.addOperand(MCOperand::createImm(Offset << 2)); + + return MCDisassembler::Success; +} + +static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder) { + unsigned Offset = Insn & 0x7F; + unsigned Reg = fieldFromInstruction(Insn, 7, 3); + + Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); + + Inst.addOperand(MCOperand::createReg(Reg)); + Inst.addOperand(MCOperand::createReg(Mips::GP)); + Inst.addOperand(MCOperand::createImm(Offset << 2)); + + return MCDisassembler::Success; +} + +static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder) { + int Offset = SignExtend32<4>(Insn & 0xf); + + if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) + == MCDisassembler::Fail) + return MCDisassembler::Fail; + + Inst.addOperand(MCOperand::createReg(Mips::SP)); + Inst.addOperand(MCOperand::createImm(Offset << 2)); return MCDisassembler::Success; } @@ -1290,19 +1303,19 @@ static DecodeStatus DecodeMemMMImm12(MCInst &Inst, if (DecodeRegListOperand(Inst, Insn, Address, Decoder) == MCDisassembler::Fail) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateReg(Base)); - Inst.addOperand(MCOperand::CreateImm(Offset)); + Inst.addOperand(MCOperand::createReg(Base)); + Inst.addOperand(MCOperand::createImm(Offset)); break; case Mips::SC_MM: - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); // fallthrough default: - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) - Inst.addOperand(MCOperand::CreateReg(Reg+1)); + Inst.addOperand(MCOperand::createReg(Reg+1)); - Inst.addOperand(MCOperand::CreateReg(Base)); - Inst.addOperand(MCOperand::CreateImm(Offset)); + Inst.addOperand(MCOperand::createReg(Base)); + Inst.addOperand(MCOperand::createImm(Offset)); } return MCDisassembler::Success; @@ -1319,9 +1332,9 @@ static DecodeStatus DecodeMemMMImm16(MCInst &Inst, Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); Base = getReg(Decoder, Mips::GPR32RegClassID, Base); - Inst.addOperand(MCOperand::CreateReg(Reg)); - Inst.addOperand(MCOperand::CreateReg(Base)); - Inst.addOperand(MCOperand::CreateImm(Offset)); + Inst.addOperand(MCOperand::createReg(Reg)); + Inst.addOperand(MCOperand::createReg(Base)); + Inst.addOperand(MCOperand::createImm(Offset)); return MCDisassembler::Success; } @@ -1337,9 +1350,9 @@ static DecodeStatus DecodeFMem(MCInst &Inst, Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); Base = getReg(Decoder, Mips::GPR32RegClassID, Base); - Inst.addOperand(MCOperand::CreateReg(Reg)); - Inst.addOperand(MCOperand::CreateReg(Base)); - Inst.addOperand(MCOperand::CreateImm(Offset)); + Inst.addOperand(MCOperand::createReg(Reg)); + Inst.addOperand(MCOperand::createReg(Base)); + Inst.addOperand(MCOperand::createImm(Offset)); return MCDisassembler::Success; } @@ -1355,9 +1368,9 @@ static DecodeStatus DecodeFMem2(MCInst &Inst, Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); Base = getReg(Decoder, Mips::GPR32RegClassID, Base); - Inst.addOperand(MCOperand::CreateReg(Reg)); - Inst.addOperand(MCOperand::CreateReg(Base)); - Inst.addOperand(MCOperand::CreateImm(Offset)); + Inst.addOperand(MCOperand::createReg(Reg)); + Inst.addOperand(MCOperand::createReg(Base)); + Inst.addOperand(MCOperand::createImm(Offset)); return MCDisassembler::Success; } @@ -1373,9 +1386,9 @@ static DecodeStatus DecodeFMem3(MCInst &Inst, Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); Base = getReg(Decoder, Mips::GPR32RegClassID, Base); - Inst.addOperand(MCOperand::CreateReg(Reg)); - Inst.addOperand(MCOperand::CreateReg(Base)); - Inst.addOperand(MCOperand::CreateImm(Offset)); + Inst.addOperand(MCOperand::createReg(Reg)); + Inst.addOperand(MCOperand::createReg(Base)); + Inst.addOperand(MCOperand::createImm(Offset)); return MCDisassembler::Success; } @@ -1391,9 +1404,9 @@ static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); Base = getReg(Decoder, Mips::GPR32RegClassID, Base); - Inst.addOperand(MCOperand::CreateReg(Reg)); - Inst.addOperand(MCOperand::CreateReg(Base)); - Inst.addOperand(MCOperand::CreateImm(Offset)); + Inst.addOperand(MCOperand::createReg(Reg)); + Inst.addOperand(MCOperand::createReg(Base)); + Inst.addOperand(MCOperand::createImm(Offset)); return MCDisassembler::Success; } @@ -1409,12 +1422,12 @@ static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, Base = getReg(Decoder, Mips::GPR32RegClassID, Base); if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ - Inst.addOperand(MCOperand::CreateReg(Rt)); + Inst.addOperand(MCOperand::createReg(Rt)); } - Inst.addOperand(MCOperand::CreateReg(Rt)); - Inst.addOperand(MCOperand::CreateReg(Base)); - Inst.addOperand(MCOperand::CreateImm(Offset)); + Inst.addOperand(MCOperand::createReg(Rt)); + Inst.addOperand(MCOperand::createReg(Base)); + Inst.addOperand(MCOperand::createImm(Offset)); return MCDisassembler::Success; } @@ -1426,7 +1439,7 @@ static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, // Currently only hardware register 29 is supported. if (RegNo != 29) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateReg(Mips::HWR29)); + Inst.addOperand(MCOperand::createReg(Mips::HWR29)); return MCDisassembler::Success; } @@ -1439,7 +1452,7 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, ; unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -1451,7 +1464,7 @@ static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -1463,7 +1476,7 @@ static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -1475,7 +1488,7 @@ static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -1487,7 +1500,7 @@ static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -1499,7 +1512,7 @@ static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -1511,7 +1524,7 @@ static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -1523,7 +1536,7 @@ static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -1535,7 +1548,7 @@ static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -1547,7 +1560,7 @@ static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -1556,7 +1569,7 @@ static DecodeStatus DecodeBranchTarget(MCInst &Inst, uint64_t Address, const void *Decoder) { int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; - Inst.addOperand(MCOperand::CreateImm(BranchOffset)); + Inst.addOperand(MCOperand::createImm(BranchOffset)); return MCDisassembler::Success; } @@ -1566,7 +1579,7 @@ static DecodeStatus DecodeJumpTarget(MCInst &Inst, const void *Decoder) { unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; - Inst.addOperand(MCOperand::CreateImm(JumpOffset)); + Inst.addOperand(MCOperand::createImm(JumpOffset)); return MCDisassembler::Success; } @@ -1576,7 +1589,7 @@ static DecodeStatus DecodeBranchTarget21(MCInst &Inst, const void *Decoder) { int32_t BranchOffset = SignExtend32<21>(Offset) * 4; - Inst.addOperand(MCOperand::CreateImm(BranchOffset)); + Inst.addOperand(MCOperand::createImm(BranchOffset)); return MCDisassembler::Success; } @@ -1586,7 +1599,7 @@ static DecodeStatus DecodeBranchTarget26(MCInst &Inst, const void *Decoder) { int32_t BranchOffset = SignExtend32<26>(Offset) * 4; - Inst.addOperand(MCOperand::CreateImm(BranchOffset)); + Inst.addOperand(MCOperand::createImm(BranchOffset)); return MCDisassembler::Success; } @@ -1595,7 +1608,16 @@ static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, uint64_t Address, const void *Decoder) { int32_t BranchOffset = SignExtend32<7>(Offset) << 1; - Inst.addOperand(MCOperand::CreateImm(BranchOffset)); + Inst.addOperand(MCOperand::createImm(BranchOffset)); + return MCDisassembler::Success; +} + +static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, + unsigned Offset, + uint64_t Address, + const void *Decoder) { + int32_t BranchOffset = SignExtend32<10>(Offset) << 1; + Inst.addOperand(MCOperand::createImm(BranchOffset)); return MCDisassembler::Success; } @@ -1604,7 +1626,7 @@ static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, uint64_t Address, const void *Decoder) { int32_t BranchOffset = SignExtend32<16>(Offset) * 2; - Inst.addOperand(MCOperand::CreateImm(BranchOffset)); + Inst.addOperand(MCOperand::createImm(BranchOffset)); return MCDisassembler::Success; } @@ -1613,7 +1635,7 @@ static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, uint64_t Address, const void *Decoder) { unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; - Inst.addOperand(MCOperand::CreateImm(JumpOffset)); + Inst.addOperand(MCOperand::createImm(JumpOffset)); return MCDisassembler::Success; } @@ -1622,11 +1644,11 @@ static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, uint64_t Address, const void *Decoder) { if (Value == 0) - Inst.addOperand(MCOperand::CreateImm(1)); + Inst.addOperand(MCOperand::createImm(1)); else if (Value == 0x7) - Inst.addOperand(MCOperand::CreateImm(-1)); + Inst.addOperand(MCOperand::createImm(-1)); else - Inst.addOperand(MCOperand::CreateImm(Value << 2)); + Inst.addOperand(MCOperand::createImm(Value << 2)); return MCDisassembler::Success; } @@ -1634,7 +1656,7 @@ static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) { - Inst.addOperand(MCOperand::CreateImm(Value << 2)); + Inst.addOperand(MCOperand::createImm(Value << 2)); return MCDisassembler::Success; } @@ -1643,9 +1665,9 @@ static DecodeStatus DecodeLiSimm7(MCInst &Inst, uint64_t Address, const void *Decoder) { if (Value == 0x7F) - Inst.addOperand(MCOperand::CreateImm(-1)); + Inst.addOperand(MCOperand::createImm(-1)); else - Inst.addOperand(MCOperand::CreateImm(Value)); + Inst.addOperand(MCOperand::createImm(Value)); return MCDisassembler::Success; } @@ -1653,7 +1675,7 @@ static DecodeStatus DecodeSimm4(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) { - Inst.addOperand(MCOperand::CreateImm(SignExtend32<4>(Value))); + Inst.addOperand(MCOperand::createImm(SignExtend32<4>(Value))); return MCDisassembler::Success; } @@ -1661,7 +1683,7 @@ static DecodeStatus DecodeSimm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { - Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn))); + Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn))); return MCDisassembler::Success; } @@ -1670,7 +1692,7 @@ static DecodeStatus DecodeLSAImm(MCInst &Inst, uint64_t Address, const void *Decoder) { // We add one to the immediate field as it was encoded as 'imm - 1'. - Inst.addOperand(MCOperand::CreateImm(Insn + 1)); + Inst.addOperand(MCOperand::createImm(Insn + 1)); return MCDisassembler::Success; } @@ -1681,7 +1703,7 @@ static DecodeStatus DecodeInsSize(MCInst &Inst, // First we need to grab the pos(lsb) from MCInst. int Pos = Inst.getOperand(2).getImm(); int Size = (int) Insn - Pos + 1; - Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size))); + Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); return MCDisassembler::Success; } @@ -1690,19 +1712,19 @@ static DecodeStatus DecodeExtSize(MCInst &Inst, uint64_t Address, const void *Decoder) { int Size = (int) Insn + 1; - Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size))); + Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); return MCDisassembler::Success; } static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { - Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4)); + Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); return MCDisassembler::Success; } static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { - Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8)); + Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); return MCDisassembler::Success; } @@ -1716,7 +1738,7 @@ static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, case 511: DecodedValue = -257; break; default: DecodedValue = SignExtend32<9>(Insn); break; } - Inst.addOperand(MCOperand::CreateImm(DecodedValue * 4)); + Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); return MCDisassembler::Success; } @@ -1726,13 +1748,13 @@ static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, assert(Insn < 16); int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535}; - Inst.addOperand(MCOperand::CreateImm(DecodedValues[Insn])); + Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); return MCDisassembler::Success; } static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { - Inst.addOperand(MCOperand::CreateImm(Insn << 2)); + Inst.addOperand(MCOperand::createImm(Insn << 2)); return MCDisassembler::Success; } @@ -1751,10 +1773,10 @@ static DecodeStatus DecodeRegListOperand(MCInst &Inst, RegNum = RegLst & 0xf; for (unsigned i = 0; i < RegNum; i++) - Inst.addOperand(MCOperand::CreateReg(Regs[i])); + Inst.addOperand(MCOperand::createReg(Regs[i])); if (RegLst & 0x10) - Inst.addOperand(MCOperand::CreateReg(Mips::RA)); + Inst.addOperand(MCOperand::createReg(Mips::RA)); return MCDisassembler::Success; } @@ -1763,18 +1785,64 @@ static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; - unsigned RegNum; - unsigned RegLst = fieldFromInstruction(Insn, 4, 2); - // Empty register lists are not allowed. - if (RegLst == 0) - return MCDisassembler::Fail; + unsigned RegNum = RegLst & 0x3; + + for (unsigned i = 0; i <= RegNum; i++) + Inst.addOperand(MCOperand::createReg(Regs[i])); + + Inst.addOperand(MCOperand::createReg(Mips::RA)); + + return MCDisassembler::Success; +} - RegNum = RegLst & 0x3; - for (unsigned i = 0; i < RegNum - 1; i++) - Inst.addOperand(MCOperand::CreateReg(Regs[i])); +static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { - Inst.addOperand(MCOperand::CreateReg(Mips::RA)); + unsigned RegPair = fieldFromInstruction(Insn, 7, 3); + switch (RegPair) { + default: + return MCDisassembler::Fail; + case 0: + Inst.addOperand(MCOperand::createReg(Mips::A1)); + Inst.addOperand(MCOperand::createReg(Mips::A2)); + break; + case 1: + Inst.addOperand(MCOperand::createReg(Mips::A1)); + Inst.addOperand(MCOperand::createReg(Mips::A3)); + break; + case 2: + Inst.addOperand(MCOperand::createReg(Mips::A2)); + Inst.addOperand(MCOperand::createReg(Mips::A3)); + break; + case 3: + Inst.addOperand(MCOperand::createReg(Mips::A0)); + Inst.addOperand(MCOperand::createReg(Mips::S5)); + break; + case 4: + Inst.addOperand(MCOperand::createReg(Mips::A0)); + Inst.addOperand(MCOperand::createReg(Mips::S6)); + break; + case 5: + Inst.addOperand(MCOperand::createReg(Mips::A0)); + Inst.addOperand(MCOperand::createReg(Mips::A1)); + break; + case 6: + Inst.addOperand(MCOperand::createReg(Mips::A0)); + Inst.addOperand(MCOperand::createReg(Mips::A2)); + break; + case 7: + Inst.addOperand(MCOperand::createReg(Mips::A0)); + Inst.addOperand(MCOperand::createReg(Mips::A3)); + break; + } + + return MCDisassembler::Success; +} + +static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + Inst.addOperand(MCOperand::createImm(SignExtend32<23>(Insn) << 2)); return MCDisassembler::Success; } |