diff options
Diffstat (limited to 'lib/Target/Mips/MicroMipsInstrFPU.td')
| -rw-r--r-- | lib/Target/Mips/MicroMipsInstrFPU.td | 350 |
1 files changed, 220 insertions, 130 deletions
diff --git a/lib/Target/Mips/MicroMipsInstrFPU.td b/lib/Target/Mips/MicroMipsInstrFPU.td index 49025cc1570a..84ae0eddf980 100644 --- a/lib/Target/Mips/MicroMipsInstrFPU.td +++ b/lib/Target/Mips/MicroMipsInstrFPU.td @@ -11,7 +11,18 @@ // //===----------------------------------------------------------------------===// -let isCodeGenOnly = 1 in { +multiclass ADDS_MMM<string opstr, InstrItinClass Itin, bit IsComm, + SDPatternOperator OpNode = null_frag> { + def _D32_MM : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, + FGR_32 { + string DecoderNamespace = "MicroMips"; + } + // FIXME: This needs to be part of the instruction mapping tables. + def _D64_MM : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 { + string DecoderNamespace = "MicroMipsFP64"; + } +} + def FADD_S_MM : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, ADDS_FM_MM<0, 0x30>, ISA_MICROMIPS; def FDIV_S_MM : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>, @@ -21,27 +32,27 @@ def FMUL_S_MM : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>, def FSUB_S_MM : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, ADDS_FM_MM<0, 0x70>, ISA_MICROMIPS; -def FADD_MM : MMRel, ADDS_FT<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>, - ADDS_FM_MM<1, 0x30>, ISA_MICROMIPS; -def FDIV_MM : MMRel, ADDS_FT<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>, - ADDS_FM_MM<1, 0xf0>, ISA_MICROMIPS; -def FMUL_MM : MMRel, ADDS_FT<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>, - ADDS_FM_MM<1, 0xb0>, ISA_MICROMIPS; -def FSUB_MM : MMRel, ADDS_FT<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>, - ADDS_FM_MM<1, 0x70>, ISA_MICROMIPS; - -def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, - LWXC1_FM_MM<0x48>, ISA_MICROMIPS32_NOT_MIPS32R6; -def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, - SWXC1_FM_MM<0x88>, ISA_MICROMIPS32_NOT_MIPS32R6; - -// FIXME: These instruction definitions are incorrect. They should be 64-bit -// FPU only. -def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, - LWXC1_FM_MM<0x148>, ISA_MICROMIPS32_NOT_MIPS32R6; -def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, - SWXC1_FM_MM<0x188>, ISA_MICROMIPS32_NOT_MIPS32R6; +defm FADD : ADDS_MMM<"add.d", II_ADD_D, 1, fadd>, + ADDS_FM_MM<1, 0x30>, ISA_MICROMIPS; +defm FDIV : ADDS_MMM<"div.d", II_DIV_D, 0, fdiv>, + ADDS_FM_MM<1, 0xf0>, ISA_MICROMIPS; +defm FMUL : ADDS_MMM<"mul.d", II_MUL_D, 1, fmul>, + ADDS_FM_MM<1, 0xb0>, ISA_MICROMIPS; +defm FSUB : ADDS_MMM<"sub.d", II_SUB_D, 0, fsub>, + ADDS_FM_MM<1, 0x70>, ISA_MICROMIPS; +let DecoderNamespace = "MicroMips" in { + def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, + LWXC1_FM_MM<0x48>, ISA_MICROMIPS32_NOT_MIPS32R6; + def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, + SWXC1_FM_MM<0x88>, ISA_MICROMIPS32_NOT_MIPS32R6; + + def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, + LWXC1_FM_MM<0x148>, FGR_64, ISA_MICROMIPS32_NOT_MIPS32R6; + def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, + SWXC1_FM_MM<0x188>, FGR_64, ISA_MICROMIPS32_NOT_MIPS32R6; +} +let isCodeGenOnly = 1 in { def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM_MM<0>, ISA_MICROMIPS32_NOT_MIPS32R6 { // FIXME: This is a required to work around the fact that these instructions @@ -65,130 +76,174 @@ let DecoderNamespace = "MicroMips" in { BC1F_FM_MM<0x1c>, ISA_MICROMIPS32_NOT_MIPS32R6; def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, II_BC1T, MIPS_BRANCH_T>, BC1F_FM_MM<0x1d>, ISA_MICROMIPS32_NOT_MIPS32R6; + def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, + ROUND_W_FM_MM<0, 0x24>, ISA_MICROMIPS; } -let isCodeGenOnly = 1 in { -def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, - ROUND_W_FM_MM<0, 0x24>, ISA_MICROMIPS; -def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, - II_ROUND>, ROUND_W_FM_MM<0, 0xec>, - ISA_MICROMIPS; - -def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>, - ROUND_W_FM_MM<1, 0x6c>, ISA_MICROMIPS, FGR_32; -def CVT_W_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>, - ROUND_W_FM_MM<1, 0x24>, ISA_MICROMIPS, FGR_32; -def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>, - ROUND_W_FM_MM<1, 0x2c>, ISA_MICROMIPS, FGR_32; -def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd, - II_ROUND>, ROUND_W_FM_MM<1, 0xec>, - ISA_MICROMIPS, FGR_32; -def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>, - ROUND_W_FM_MM<1, 0xac>, ISA_MICROMIPS, FGR_32; - -def FSQRT_MM : MMRel, ABSS_FT<"sqrt.d", AFGR64Opnd, AFGR64Opnd, II_SQRT_D, - fsqrt>, ROUND_W_FM_MM<1, 0x28>, - ISA_MICROMIPS, FGR_32; - -def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, - ROUND_W_FM_MM<0, 0x4>, ISA_MICROMIPS, FGR_64; -def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, - ROUND_W_FM_MM<1, 0x4>, ISA_MICROMIPS, FGR_64; +let DecoderNamespace = "MicroMips" in { + def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, + FGR32Opnd, II_ROUND>, + ROUND_W_FM_MM<0, 0xec>, ISA_MICROMIPS; + + def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>, + ROUND_W_FM_MM<1, 0x6c>, ISA_MICROMIPS, FGR_32; + def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>, + ROUND_W_FM_MM<1, 0x2c>, ISA_MICROMIPS, FGR_32; + def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd, + AFGR64Opnd, II_ROUND>, + ROUND_W_FM_MM<1, 0xec>, ISA_MICROMIPS, FGR_32; + def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>, + ROUND_W_FM_MM<1, 0xac>, ISA_MICROMIPS, FGR_32; + + def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, + ROUND_W_FM_MM<0, 0x4>, ISA_MICROMIPS, FGR_64; + def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, + ROUND_W_FM_MM<1, 0x4>, ISA_MICROMIPS, FGR_64; + + def CVT_W_D32_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>, + ROUND_W_FM_MM<1, 0x24>, ISA_MICROMIPS, FGR_32; +} +let DecoderNamespace = "MicroMipsFP64" in { + def CVT_W_D64_MM : ABSS_FT<"cvt.w.d", FGR32Opnd, FGR64Opnd, II_CVT>, + ROUND_W_FM_MM<1, 0x24>, ISA_MICROMIPS, FGR_64; +} +multiclass ABSS_MMM<string opstr, InstrItinClass Itin, + SDPatternOperator OpNode = null_frag> { + def _D32_MM : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>, + ISA_MICROMIPS, FGR_32 { + string DecoderNamespace = "MicroMips"; + } + // FIXME: This needs to be part of the instruction mapping tables. + def _D64_MM : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, + ISA_MICROMIPS, FGR_64 { + string DecoderNamespace = "MicroMipsFP64"; + } } +defm FSQRT : ABSS_MMM<"sqrt.d", II_SQRT_D, fsqrt>, ROUND_W_FM_MM<1, 0x28>; +defm FABS : ABSS_MMM<"abs.d", II_SQRT_D, fabs>, ABS_FM_MM<1, 0xd>; + let DecoderNamespace = "MicroMips" in { def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>, ABS_FM_MM<0, 0xd>, ISA_MICROMIPS; - def FABS_MM : MMRel, ABSS_FT<"abs.d", AFGR64Opnd, AFGR64Opnd, II_ABS, fabs>, - ABS_FM_MM<1, 0xd>, ISA_MICROMIPS, FGR_32; } -let isCodeGenOnly = 1 in { def FMOV_S_MM : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, - ABS_FM_MM<0, 0x1>, ISA_MICROMIPS; + ABS_FM_MM<0, 0x1>, ISA_MICROMIPS { + let isMoveReg = 1; +} def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, ABS_FM_MM<0, 0x2d>, ISA_MICROMIPS; -def CVT_D_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, - ABS_FM_MM<0, 0x4d>, ISA_MICROMIPS, FGR_32; -def CVT_D32_W_MM : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, - ABS_FM_MM<1, 0x4d>, ISA_MICROMIPS, FGR_32; -def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, - ABS_FM_MM<0, 0x6d>, ISA_MICROMIPS, FGR_32; -def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>, - ABS_FM_MM<1, 0x6d>, ISA_MICROMIPS; - -def FNEG_MM : MMRel, ABSS_FT<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>, - ABS_FM_MM<1, 0x2d>, ISA_MICROMIPS, FGR_32; - -def FMOV_D32_MM : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>, - ABS_FM_MM<1, 0x1>, ISA_MICROMIPS, FGR_32; - -def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, - II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>, - ISA_MICROMIPS32_NOT_MIPS32R6; -def MOVN_I_S_MM : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, + +let DecoderNamespace = "MicroMips" in { + def CVT_D32_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, + ABS_FM_MM<0, 0x4d>, ISA_MICROMIPS, FGR_32; + def CVT_D32_W_MM : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, + ABS_FM_MM<1, 0x4d>, ISA_MICROMIPS, FGR_32; +} + +let DecoderNamespace = "MicroMipsFP64" in { + def CVT_D64_S_MM : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>, + ABS_FM_MM<0, 0x4d>, ISA_MICROMIPS, FGR_64; + def CVT_D64_W_MM : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>, + ABS_FM_MM<1, 0x4d>, ISA_MICROMIPS, FGR_64; + def CVT_S_D64_MM : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>, + ABS_FM_MM<0, 0x6d>, ISA_MICROMIPS, FGR_64; +} + +let DecoderNamespace = "MicroMips" in { + def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, + ABS_FM_MM<0, 0x6d>, ISA_MICROMIPS, FGR_32; + def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>, + ABS_FM_MM<1, 0x6d>, ISA_MICROMIPS; +} + + +defm FNEG : ABSS_MMM<"neg.d", II_NEG, fneg>, ABS_FM_MM<1, 0x2d>; +defm FMOV : ABSS_MMM<"mov.d", II_MOV_D>, ABS_FM_MM<1, 0x1>; + +let DecoderNamespace = "MicroMips" in { + def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, + II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>, + ISA_MICROMIPS32_NOT_MIPS32R6; + def MOVN_I_S_MM : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, II_MOVN_S>, CMov_I_F_FM_MM<0x38, 0>, + ISA_MICROMIPS32_NOT_MIPS32R6; + def MOVZ_I_D32_MM : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd, + II_MOVZ_D>, CMov_I_F_FM_MM<0x78, 1>, + ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; + def MOVN_I_D32_MM : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd, + II_MOVN_D>, CMov_I_F_FM_MM<0x38, 1>, + ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; + + def MOVT_S_MM : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, + MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 0>, ISA_MICROMIPS32_NOT_MIPS32R6; -def MOVZ_I_D32_MM : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd, - II_MOVZ_D>, CMov_I_F_FM_MM<0x78, 1>, - ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; -def MOVN_I_D32_MM : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd, - II_MOVN_D>, CMov_I_F_FM_MM<0x38, 1>, - ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; - -def MOVT_S_MM : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, - MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 0>, - ISA_MICROMIPS32_NOT_MIPS32R6; -def MOVF_S_MM : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, - MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 0>, - ISA_MICROMIPS32_NOT_MIPS32R6; -def MOVT_D32_MM : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D, + def MOVF_S_MM : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, + MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 0>, + ISA_MICROMIPS32_NOT_MIPS32R6; + def MOVT_D32_MM : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D, MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 1>, - ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; -def MOVF_D32_MM : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D, - MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 1>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; -def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, - II_MFC1, bitconvert>, MFC1_FM_MM<0x80>, - ISA_MICROMIPS; -def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, - II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>, - ISA_MICROMIPS; - -def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, - MADDS_FM_MM<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6; -def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, - MADDS_FM_MM<0x21>, ISA_MICROMIPS32_NOT_MIPS32R6; -def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>, - MADDS_FM_MM<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6; -def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>, - MADDS_FM_MM<0x22>, ISA_MICROMIPS32_NOT_MIPS32R6; - -def MADD_D32_MM : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>, - MADDS_FM_MM<0x9>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; -def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>, - MADDS_FM_MM<0x29>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; -def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>, - MADDS_FM_MM<0xa>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; -def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>, - MADDS_FM_MM<0x2a>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; + def MOVF_D32_MM : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D, + MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 1>, + ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; + + def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, + II_MFC1, bitconvert>, MFC1_FM_MM<0x80>, + ISA_MICROMIPS; + def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, + II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>, + ISA_MICROMIPS; + + def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S>, + MADDS_FM_MM<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6, MADD4; + def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S>, + MADDS_FM_MM<0x21>, ISA_MICROMIPS32_NOT_MIPS32R6, MADD4; + let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in { + def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S>, + MADDS_FM_MM<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6; + def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S>, + MADDS_FM_MM<0x22>, ISA_MICROMIPS32_NOT_MIPS32R6; + } + def MADD_D32_MM : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D>, + MADDS_FM_MM<0x9>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32, + MADD4; + def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D>, + MADDS_FM_MM<0x29>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32, + MADD4; + let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in { + def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D>, + MADDS_FM_MM<0xa>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; + def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D>, + MADDS_FM_MM<0x2a>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; + } + + def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, + II_FLOOR>, ROUND_W_FM_MM<0, 0x2c>, + ISA_MICROMIPS; + def TRUNC_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, + FGR32Opnd, II_TRUNC>, + ROUND_W_FM_MM<0, 0xac>, ISA_MICROMIPS; + def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, + ROUND_W_FM_MM<0, 0x6c>, ISA_MICROMIPS; + + def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, + fsqrt>, ROUND_W_FM_MM<0, 0x28>, ISA_MICROMIPS; + + def MTHC1_D32_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, + MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_32; + def MFHC1_D32_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, + MFC1_FM_MM<0xc0>, ISA_MICROMIPS, FGR_32; } -def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, - II_FLOOR>, ROUND_W_FM_MM<0, 0x2c>, - ISA_MICROMIPS; -def TRUNC_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, - FGR32Opnd, II_TRUNC>, - ROUND_W_FM_MM<0, 0xac>, ISA_MICROMIPS; -def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, - ROUND_W_FM_MM<0, 0x6c>, ISA_MICROMIPS; -def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, - fsqrt>, ROUND_W_FM_MM<0, 0x28>, ISA_MICROMIPS; -def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, - MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_32; -def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, - MFC1_FM_MM<0xc0>, ISA_MICROMIPS, FGR_32; +let DecoderNamespace = "MicroMipsFP64" in { + def MTHC1_D64_MM : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>, + MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_64; + def MFHC1_D64_MM : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>, + MFC1_FM_MM<0xc0>, ISA_MICROMIPS, FGR_64; +} let DecoderNamespace = "MicroMips" in { def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, @@ -307,11 +362,13 @@ multiclass C_COND_MM<string TypeStr, RegisterOperand RC, bits<2> fmt, let BaseOpcode = "c.ngt."#NAME; } } +let DecoderNamespace = "MicroMips" in { + defm S : C_COND_MM<"s", FGR32Opnd, 0b00, II_C_CC_S>, + ISA_MICROMIPS32_NOT_MIPS32R6; + defm D32 : C_COND_MM<"d", AFGR64Opnd, 0b01, II_C_CC_D>, + ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; +} -defm S : C_COND_MM<"s", FGR32Opnd, 0b00, II_C_CC_S>, - ISA_MICROMIPS32_NOT_MIPS32R6; -defm D32 : C_COND_MM<"d", AFGR64Opnd, 0b01, II_C_CC_D>, - ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; let DecoderNamespace = "Mips64" in defm D64 : C_COND_MM<"d", FGR64Opnd, 0b01, II_C_CC_D>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_64; @@ -347,3 +404,36 @@ let AddedComplexity = 40 in { def : LoadRegImmPat<LWC1_MM, f32, load>, ISA_MICROMIPS; def : StoreRegImmPat<SWC1_MM, f32>, ISA_MICROMIPS; } + +def : MipsPat<(f32 fpimm0), (MTC1_MM ZERO)>, ISA_MICROMIPS32_NOT_MIPS32R6; +def : MipsPat<(f32 fpimm0neg), (FNEG_S_MM (MTC1_MM ZERO))>, + ISA_MICROMIPS32_NOT_MIPS32R6; + +def : MipsPat<(f32 (fpround FGR64Opnd:$src)), + (CVT_S_D64_MM FGR64Opnd:$src)>, ISA_MICROMIPS, FGR_64; +def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), + (CVT_D64_S_MM FGR32Opnd:$src)>, ISA_MICROMIPS, FGR_64; +def : MipsPat<(f32 (fpround AFGR64Opnd:$src)), + (CVT_S_D32_MM AFGR64Opnd:$src)>, ISA_MICROMIPS, FGR_32; +def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), + (CVT_D32_S_MM FGR32Opnd:$src)>, ISA_MICROMIPS, FGR_32; +def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src), + (TRUNC_W_MM AFGR64Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6, + FGR_32; + +// Selects +defm : MovzPats0<GPR32, FGR32, MOVZ_I_S_MM, SLT_MM, SLTu_MM, SLTi_MM, SLTiu_MM>, + ISA_MICROMIPS32_NOT_MIPS32R6; +defm : MovzPats1<GPR32, FGR32, MOVZ_I_S_MM, XOR_MM>, + ISA_MICROMIPS32_NOT_MIPS32R6; + +defm : MovnPats<GPR32, FGR32, MOVN_I_S_MM, XOR_MM>, + ISA_MICROMIPS32_NOT_MIPS32R6; + +defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32_MM, SLT_MM, SLTu_MM, SLTi_MM, + SLTiu_MM>, + ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; +defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32_MM, XOR_MM>, + ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; +defm : MovnPats<GPR32, AFGR64, MOVN_I_D32_MM, XOR_MM>, + ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; |