diff options
Diffstat (limited to 'lib/Target/Mips/MipsFastISel.cpp')
| -rw-r--r-- | lib/Target/Mips/MipsFastISel.cpp | 39 |
1 files changed, 26 insertions, 13 deletions
diff --git a/lib/Target/Mips/MipsFastISel.cpp b/lib/Target/Mips/MipsFastISel.cpp index e9eaf810637a..19c201d26b24 100644 --- a/lib/Target/Mips/MipsFastISel.cpp +++ b/lib/Target/Mips/MipsFastISel.cpp @@ -1,5 +1,18 @@ -//===-- MipsastISel.cpp - Mips FastISel implementation -//---------------------===// +//===-- MipsFastISel.cpp - Mips FastISel implementation --------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// \brief This file defines the MIPS-specific support for the FastISel class. +/// Some of the target-specific code is generated by tablegen in the file +/// MipsGenFastISel.inc, which is #included here. +/// +//===----------------------------------------------------------------------===// #include "MipsCCState.h" #include "MipsInstrInfo.h" @@ -192,9 +205,10 @@ public: TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) { MFI = funcInfo.MF->getInfo<MipsFunctionInfo>(); Context = &funcInfo.Fn->getContext(); - bool ISASupported = !Subtarget->hasMips32r6() && Subtarget->hasMips32(); + bool ISASupported = !Subtarget->hasMips32r6() && + !Subtarget->inMicroMipsMode() && Subtarget->hasMips32(); TargetSupported = - ISASupported && (TM.getRelocationModel() == Reloc::PIC_) && + ISASupported && TM.isPositionIndependent() && (static_cast<const MipsTargetMachine &>(TM).getABI().IsO32()); UnsupportedFPMode = Subtarget->isFP64bit(); } @@ -691,11 +705,10 @@ bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) { emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1); emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg( Mips::FCC0, RegState::ImplicitDefine); - MachineInstrBuilder MI = emitInst(CondMovOpc, ResultReg) - .addReg(RegWithOne) - .addReg(Mips::FCC0) - .addReg(RegWithZero, RegState::Implicit); - MI->tieOperands(0, 3); + emitInst(CondMovOpc, ResultReg) + .addReg(RegWithOne) + .addReg(Mips::FCC0) + .addReg(RegWithZero); break; } } @@ -802,7 +815,7 @@ bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr, unsigned Offset = Addr.getOffset(); MachineFrameInfo &MFI = *MF->getFrameInfo(); MachineMemOperand *MMO = MF->getMachineMemOperand( - MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad, + MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore, MFI.getObjectSize(FI), Align); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)) .addReg(SrcReg) @@ -943,7 +956,7 @@ bool MipsFastISel::selectFPExt(const Instruction *I) { return false; unsigned SrcReg = - getRegForValue(Src); // his must be a 32 bit floating point register class + getRegForValue(Src); // this must be a 32bit floating point register class // maybe we should handle this differently if (!SrcReg) return false; @@ -1180,7 +1193,7 @@ bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI, // for now (will return false). We need to determine the right alignment // based on the normal alignment for the underlying machine type. // - unsigned ArgSize = RoundUpToAlignment(ArgVT.getSizeInBits(), 4); + unsigned ArgSize = alignTo(ArgVT.getSizeInBits(), 4); unsigned BEAlign = 0; if (ArgSize < 8 && !Subtarget->isLittle()) @@ -1207,7 +1220,7 @@ bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI, bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes) { CallingConv::ID CC = CLI.CallConv; - emitInst(Mips::ADJCALLSTACKUP).addImm(16); + emitInst(Mips::ADJCALLSTACKUP).addImm(16).addImm(0); if (RetVT != MVT::isVoid) { SmallVector<CCValAssign, 16> RVLocs; CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context); |