diff options
Diffstat (limited to 'lib/Target/Mips/MipsTargetMachine.cpp')
| -rw-r--r-- | lib/Target/Mips/MipsTargetMachine.cpp | 34 |
1 files changed, 26 insertions, 8 deletions
diff --git a/lib/Target/Mips/MipsTargetMachine.cpp b/lib/Target/Mips/MipsTargetMachine.cpp index 3e638720e839..c248c3a50ac8 100644 --- a/lib/Target/Mips/MipsTargetMachine.cpp +++ b/lib/Target/Mips/MipsTargetMachine.cpp @@ -26,6 +26,7 @@ #include "MipsTargetObjectFile.h" #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/CodeGen/Passes.h" +#include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/IR/LegacyPassManager.h" #include "llvm/Support/Debug.h" #include "llvm/Support/TargetRegistry.h" @@ -77,6 +78,13 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU, return Ret; } +static Reloc::Model getEffectiveRelocModel(CodeModel::Model CM, + Optional<Reloc::Model> RM) { + if (!RM.hasValue() || CM == CodeModel::JITDefault) + return Reloc::Static; + return *RM; +} + // On function prologue, the stack is created by decrementing // its pointer. Once decremented, all references are done with positive // offset from the stack/frame pointer, using StackGrowsUp enables @@ -85,10 +93,12 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU, MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Reloc::Model RM, CodeModel::Model CM, - CodeGenOpt::Level OL, bool isLittle) + Optional<Reloc::Model> RM, + CodeModel::Model CM, CodeGenOpt::Level OL, + bool isLittle) : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, - CPU, FS, Options, RM, CM, OL), + CPU, FS, Options, getEffectiveRelocModel(CM, RM), CM, + OL), isLittle(isLittle), TLOF(make_unique<MipsTargetObjectFile>()), ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)), Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this), @@ -107,7 +117,8 @@ void MipsebTargetMachine::anchor() { } MipsebTargetMachine::MipsebTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Reloc::Model RM, CodeModel::Model CM, + Optional<Reloc::Model> RM, + CodeModel::Model CM, CodeGenOpt::Level OL) : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} @@ -116,7 +127,8 @@ void MipselTargetMachine::anchor() { } MipselTargetMachine::MipselTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Reloc::Model RM, CodeModel::Model CM, + Optional<Reloc::Model> RM, + CodeModel::Model CM, CodeGenOpt::Level OL) : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} @@ -217,8 +229,8 @@ void MipsPassConfig::addIRPasses() { // the ISelDag to gen Mips code. bool MipsPassConfig::addInstSelector() { addPass(createMipsModuleISelDagPass(getMipsTargetMachine())); - addPass(createMips16ISelDag(getMipsTargetMachine())); - addPass(createMipsSEISelDag(getMipsTargetMachine())); + addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel())); + addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel())); return false; } @@ -250,7 +262,13 @@ TargetIRAnalysis MipsTargetMachine::getTargetIRAnalysis() { // print out the code after the passes. void MipsPassConfig::addPreEmitPass() { MipsTargetMachine &TM = getMipsTargetMachine(); + + // The delay slot filler pass can potientially create forbidden slot (FS) + // hazards for MIPSR6 which the hazard schedule pass (HSP) will fix. Any + // (new) pass that creates compact branches after the HSP must handle FS + // hazards itself or be pipelined before the HSP. addPass(createMipsDelaySlotFillerPass(TM)); + addPass(createMipsHazardSchedule()); addPass(createMipsLongBranchPass(TM)); - addPass(createMipsConstantIslandPass(TM)); + addPass(createMipsConstantIslandPass()); } |