diff options
Diffstat (limited to 'lib/Target/PowerPC/PPCRegisterInfo.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.cpp | 54 |
1 files changed, 50 insertions, 4 deletions
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 6b62a82ef7bf..6647ceace5eb 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -65,6 +65,12 @@ static cl::opt<bool> EnableGPRToVecSpills("ppc-enable-gpr-to-vsr-spills", cl::Hidden, cl::init(false), cl::desc("Enable spills from gpr to vsr rather than stack")); +static cl::opt<bool> +StackPtrConst("ppc-stack-ptr-caller-preserved", + cl::desc("Consider R1 caller preserved so stack saves of " + "caller preserved registers can be LICM candidates"), + cl::init(true), cl::Hidden); + PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM) : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR, TM.isPPC64() ? 0 : 1, @@ -100,6 +106,12 @@ PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM) ImmToIdxMap[PPC::STXV] = PPC::STXVX; ImmToIdxMap[PPC::STXSD] = PPC::STXSDX; ImmToIdxMap[PPC::STXSSP] = PPC::STXSSPX; + + // SPE + ImmToIdxMap[PPC::EVLDD] = PPC::EVLDDX; + ImmToIdxMap[PPC::EVSTDD] = PPC::EVSTDDX; + ImmToIdxMap[PPC::SPESTW] = PPC::SPESTWX; + ImmToIdxMap[PPC::SPELWZ] = PPC::SPELWZX; } /// getPointerRegClass - Return the register class to use to hold pointers. @@ -141,9 +153,23 @@ PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { if (TM.isPPC64() && MF->getInfo<PPCFunctionInfo>()->isSplitCSR()) return CSR_SRV464_TLS_PE_SaveList; + if (Subtarget.hasSPE()) + return CSR_SVR432_SPE_SaveList; + // On PPC64, we might need to save r2 (but only if it is not reserved). bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2); + if (MF->getFunction().getCallingConv() == CallingConv::Cold) { + return TM.isPPC64() + ? (Subtarget.hasAltivec() + ? (SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList + : CSR_SVR64_ColdCC_Altivec_SaveList) + : (SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList + : CSR_SVR64_ColdCC_SaveList)) + : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_SaveList + : CSR_SVR32_ColdCC_SaveList); + } + return TM.isPPC64() ? (Subtarget.hasAltivec() ? (SaveR2 ? CSR_SVR464_R2_Altivec_SaveList @@ -196,6 +222,13 @@ PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_RegMask : CSR_Darwin32_RegMask); + if (CC == CallingConv::Cold) { + return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask + : CSR_SVR64_ColdCC_RegMask) + : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_RegMask + : CSR_SVR32_ColdCC_RegMask); + } + return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask : CSR_SVR464_RegMask) : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask @@ -286,15 +319,26 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { bool PPCRegisterInfo::isCallerPreservedPhysReg(unsigned PhysReg, const MachineFunction &MF) const { assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); - if (TM.isELFv2ABI() && PhysReg == PPC::X2) { + const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); + const MachineFrameInfo &MFI = MF.getFrameInfo(); + if (!TM.isPPC64()) + return false; + + if (!Subtarget.isSVR4ABI()) + return false; + if (PhysReg == PPC::X2) // X2 is guaranteed to be preserved within a function if it is reserved. // The reason it's reserved is that it's the TOC pointer (and the function // uses the TOC). In functions where it isn't reserved (i.e. leaf functions // with no TOC access), we can't claim that it is preserved. return (getReservedRegs(MF).test(PPC::X2)); - } else { - return false; - } + if (StackPtrConst && (PhysReg == PPC::X1) && !MFI.hasVarSizedObjects() + && !MFI.hasOpaqueSPAdjustment()) + // The value of the stack pointer does not change within a function after + // the prologue and before the epilogue if there are no dynamic allocations + // and no inline asm which clobbers X1. + return true; + return false; } unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, @@ -307,6 +351,8 @@ unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, return 0; case PPC::G8RC_NOX0RegClassID: case PPC::GPRC_NOR0RegClassID: + case PPC::SPERCRegClassID: + case PPC::SPE4RCRegClassID: case PPC::G8RCRegClassID: case PPC::GPRCRegClassID: { unsigned FP = TFI->hasFP(MF) ? 1 : 0; |