diff options
Diffstat (limited to 'lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp')
| -rw-r--r-- | lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp b/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp index 78776c11d75d..640de3f9fc84 100644 --- a/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp +++ b/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp @@ -14,9 +14,10 @@ //===----------------------------------------------------------------------===// #include "AMDGPU.h" -#include "MCTargetDesc/AMDGPUMCTargetDesc.h" -#include "MCTargetDesc/AMDGPUMCCodeEmitter.h" #include "MCTargetDesc/AMDGPUFixupKinds.h" +#include "MCTargetDesc/AMDGPUMCCodeEmitter.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" +#include "SIDefines.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCFixup.h" @@ -84,12 +85,10 @@ MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII, bool SIMCCodeEmitter::isSrcOperand(const MCInstrDesc &Desc, unsigned OpNo) const { + unsigned OpType = Desc.OpInfo[OpNo].OperandType; - unsigned RegClass = Desc.OpInfo[OpNo].RegClass; - return (AMDGPU::SSrc_32RegClassID == RegClass) || - (AMDGPU::SSrc_64RegClassID == RegClass) || - (AMDGPU::VSrc_32RegClassID == RegClass) || - (AMDGPU::VSrc_64RegClassID == RegClass); + return OpType == AMDGPU::OPERAND_REG_IMM32 || + OpType == AMDGPU::OPERAND_REG_INLINE_C; } uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO) const { |