diff options
Diffstat (limited to 'lib/Target/X86/X86InstrCMovSetCC.td')
| -rw-r--r-- | lib/Target/X86/X86InstrCMovSetCC.td | 68 |
1 files changed, 33 insertions, 35 deletions
diff --git a/lib/Target/X86/X86InstrCMovSetCC.td b/lib/Target/X86/X86InstrCMovSetCC.td index 8dd5e1c0626b..eda4ba5ae6f0 100644 --- a/lib/Target/X86/X86InstrCMovSetCC.td +++ b/lib/Target/X86/X86InstrCMovSetCC.td @@ -14,69 +14,67 @@ // CMOV instructions. -multiclass CMOV<bits<8> opc, string Mnemonic, PatLeaf CondNode> { +multiclass CMOV<bits<8> opc, string Mnemonic, X86FoldableSchedWrite Sched, + PatLeaf CondNode> { let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst", - isCommutable = 1, SchedRW = [WriteALU] in { + isCommutable = 1, SchedRW = [Sched] in { def NAME#16rr : I<opc, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"), [(set GR16:$dst, - (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))], - IIC_CMOV16_RR>, TB, OpSize16; + (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))]>, + TB, OpSize16; def NAME#32rr : I<opc, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"), [(set GR32:$dst, - (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))], - IIC_CMOV32_RR>, TB, OpSize32; + (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))]>, + TB, OpSize32; def NAME#64rr :RI<opc, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"), [(set GR64:$dst, - (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))], - IIC_CMOV32_RR>, TB; + (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))]>, TB; } let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst", - SchedRW = [WriteALULd, ReadAfterLd] in { + SchedRW = [Sched.Folded, ReadAfterLd] in { def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"), [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), - CondNode, EFLAGS))], IIC_CMOV16_RM>, - TB, OpSize16; + CondNode, EFLAGS))]>, TB, OpSize16; def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"), [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), - CondNode, EFLAGS))], IIC_CMOV32_RM>, - TB, OpSize32; + CondNode, EFLAGS))]>, TB, OpSize32; def NAME#64rm :RI<opc, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"), [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), - CondNode, EFLAGS))], IIC_CMOV32_RM>, TB; + CondNode, EFLAGS))]>, TB; } // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst" } // end multiclass // Conditional Moves. -defm CMOVO : CMOV<0x40, "cmovo" , X86_COND_O>; -defm CMOVNO : CMOV<0x41, "cmovno", X86_COND_NO>; -defm CMOVB : CMOV<0x42, "cmovb" , X86_COND_B>; -defm CMOVAE : CMOV<0x43, "cmovae", X86_COND_AE>; -defm CMOVE : CMOV<0x44, "cmove" , X86_COND_E>; -defm CMOVNE : CMOV<0x45, "cmovne", X86_COND_NE>; -defm CMOVBE : CMOV<0x46, "cmovbe", X86_COND_BE>; -defm CMOVA : CMOV<0x47, "cmova" , X86_COND_A>; -defm CMOVS : CMOV<0x48, "cmovs" , X86_COND_S>; -defm CMOVNS : CMOV<0x49, "cmovns", X86_COND_NS>; -defm CMOVP : CMOV<0x4A, "cmovp" , X86_COND_P>; -defm CMOVNP : CMOV<0x4B, "cmovnp", X86_COND_NP>; -defm CMOVL : CMOV<0x4C, "cmovl" , X86_COND_L>; -defm CMOVGE : CMOV<0x4D, "cmovge", X86_COND_GE>; -defm CMOVLE : CMOV<0x4E, "cmovle", X86_COND_LE>; -defm CMOVG : CMOV<0x4F, "cmovg" , X86_COND_G>; +defm CMOVO : CMOV<0x40, "cmovo" , WriteCMOV, X86_COND_O>; +defm CMOVNO : CMOV<0x41, "cmovno", WriteCMOV, X86_COND_NO>; +defm CMOVB : CMOV<0x42, "cmovb" , WriteCMOV, X86_COND_B>; +defm CMOVAE : CMOV<0x43, "cmovae", WriteCMOV, X86_COND_AE>; +defm CMOVE : CMOV<0x44, "cmove" , WriteCMOV, X86_COND_E>; +defm CMOVNE : CMOV<0x45, "cmovne", WriteCMOV, X86_COND_NE>; +defm CMOVBE : CMOV<0x46, "cmovbe", WriteCMOV2, X86_COND_BE>; +defm CMOVA : CMOV<0x47, "cmova" , WriteCMOV2, X86_COND_A>; +defm CMOVS : CMOV<0x48, "cmovs" , WriteCMOV, X86_COND_S>; +defm CMOVNS : CMOV<0x49, "cmovns", WriteCMOV, X86_COND_NS>; +defm CMOVP : CMOV<0x4A, "cmovp" , WriteCMOV, X86_COND_P>; +defm CMOVNP : CMOV<0x4B, "cmovnp", WriteCMOV, X86_COND_NP>; +defm CMOVL : CMOV<0x4C, "cmovl" , WriteCMOV, X86_COND_L>; +defm CMOVGE : CMOV<0x4D, "cmovge", WriteCMOV, X86_COND_GE>; +defm CMOVLE : CMOV<0x4E, "cmovle", WriteCMOV, X86_COND_LE>; +defm CMOVG : CMOV<0x4F, "cmovg" , WriteCMOV, X86_COND_G>; // SetCC instructions. @@ -84,12 +82,12 @@ multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> { let Uses = [EFLAGS] in { def r : I<opc, MRMXr, (outs GR8:$dst), (ins), !strconcat(Mnemonic, "\t$dst"), - [(set GR8:$dst, (X86setcc OpNode, EFLAGS))], - IIC_SET_R>, TB, Sched<[WriteALU]>; + [(set GR8:$dst, (X86setcc OpNode, EFLAGS))]>, + TB, Sched<[WriteSETCC]>; def m : I<opc, MRMXm, (outs), (ins i8mem:$dst), !strconcat(Mnemonic, "\t$dst"), - [(store (X86setcc OpNode, EFLAGS), addr:$dst)], - IIC_SET_M>, TB, Sched<[WriteALU, WriteStore]>; + [(store (X86setcc OpNode, EFLAGS), addr:$dst)]>, + TB, Sched<[WriteSETCCStore]>; } // Uses = [EFLAGS] } @@ -114,5 +112,5 @@ defm SETG : SETCC<0x9F, "setg", X86_COND_G>; // signed greater than // here http://www.rcollins.org/secrets/opcodes/SALC.html // Set AL if carry. let Uses = [EFLAGS], Defs = [AL], SchedRW = [WriteALU] in { - def SALC : I<0xD6, RawFrm, (outs), (ins), "salc", [], IIC_AHF>, Requires<[Not64BitMode]>; + def SALC : I<0xD6, RawFrm, (outs), (ins), "salc", []>, Requires<[Not64BitMode]>; } |