diff options
Diffstat (limited to 'lib/libpmc/pmu-events/arch/x86/sandybridge/other.json')
| -rw-r--r-- | lib/libpmc/pmu-events/arch/x86/sandybridge/other.json | 66 |
1 files changed, 33 insertions, 33 deletions
diff --git a/lib/libpmc/pmu-events/arch/x86/sandybridge/other.json b/lib/libpmc/pmu-events/arch/x86/sandybridge/other.json index 874eb40a2e0f..e251f535ec09 100644 --- a/lib/libpmc/pmu-events/arch/x86/sandybridge/other.json +++ b/lib/libpmc/pmu-events/arch/x86/sandybridge/other.json @@ -1,58 +1,58 @@ [ { - "EventCode": "0x17", + "BriefDescription": "Unhalted core cycles when the thread is in ring 0.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INSTS_WRITTEN_TO_IQ.INSTS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", + "EventName": "CPL_CYCLES.RING0", "SampleAfterValue": "2000003", - "BriefDescription": "Valid instructions written to IQ per cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x4E", + "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "HW_PRE_REQ.DL1_MISS", - "SampleAfterValue": "2000003", - "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5C", + "EventName": "CPL_CYCLES.RING0_TRANS", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "EventCode": "0x5C", + "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPL_CYCLES.RING0", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", + "EventName": "CPL_CYCLES.RING123", "SampleAfterValue": "2000003", - "BriefDescription": "Unhalted core cycles when the thread is in ring 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x5C", + "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .", "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "CPL_CYCLES.RING0_TRANS", - "SampleAfterValue": "100007", - "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4E", + "EventName": "HW_PRE_REQ.DL1_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x5C", + "BriefDescription": "Valid instructions written to IQ per cycle.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPL_CYCLES.RING123", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x17", + "EventName": "INSTS_WRITTEN_TO_IQ.INSTS", "SampleAfterValue": "2000003", - "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x63", + "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ]
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