diff options
Diffstat (limited to 'llvm/include/llvm/CodeGen/FastISel.h')
| -rw-r--r-- | llvm/include/llvm/CodeGen/FastISel.h | 36 |
1 files changed, 14 insertions, 22 deletions
diff --git a/llvm/include/llvm/CodeGen/FastISel.h b/llvm/include/llvm/CodeGen/FastISel.h index 81c1d6aad49a..9c7e688da6a7 100644 --- a/llvm/include/llvm/CodeGen/FastISel.h +++ b/llvm/include/llvm/CodeGen/FastISel.h @@ -274,7 +274,7 @@ public: /// This is a wrapper around getRegForValue that also takes care of /// truncating or sign-extending the given getelementptr index value. - std::pair<Register, bool> getRegForGEPIndex(const Value *Idx); + Register getRegForGEPIndex(const Value *Idx); /// We're checking to see if we can fold \p LI into \p FoldInst. Note /// that we could have a sequence where multiple LLVM IR instructions are @@ -347,27 +347,26 @@ protected: /// This method is called by target-independent code to request that an /// instruction with the given type, opcode, and register operand be emitted. - virtual unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, - bool Op0IsKill); + virtual unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0); /// This method is called by target-independent code to request that an /// instruction with the given type, opcode, and register operands be emitted. virtual unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, - bool Op0IsKill, unsigned Op1, bool Op1IsKill); + unsigned Op1); /// This method is called by target-independent code to request that an /// instruction with the given type, opcode, and register and immediate /// operands be emitted. virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, - bool Op0IsKill, uint64_t Imm); + uint64_t Imm); /// This method is a wrapper of fastEmit_ri. /// /// It first tries to emit an instruction with an immediate operand using /// fastEmit_ri. If that fails, it materializes the immediate into a register /// and try fastEmit_rr instead. - Register fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill, - uint64_t Imm, MVT ImmType); + Register fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, uint64_t Imm, + MVT ImmType); /// This method is called by target-independent code to request that an /// instruction with the given type, opcode, and immediate operand be emitted. @@ -387,33 +386,31 @@ protected: /// Emit a MachineInstr with one register operand and a result register /// in the given register class. Register fastEmitInst_r(unsigned MachineInstOpcode, - const TargetRegisterClass *RC, unsigned Op0, - bool Op0IsKill); + const TargetRegisterClass *RC, unsigned Op0); /// Emit a MachineInstr with two register operands and a result /// register in the given register class. Register fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, - bool Op0IsKill, unsigned Op1, bool Op1IsKill); + unsigned Op1); /// Emit a MachineInstr with three register operands and a result /// register in the given register class. Register fastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, - bool Op0IsKill, unsigned Op1, bool Op1IsKill, - unsigned Op2, bool Op2IsKill); + unsigned Op1, unsigned Op2); /// Emit a MachineInstr with a register operand, an immediate, and a /// result register in the given register class. Register fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, - bool Op0IsKill, uint64_t Imm); + uint64_t Imm); /// Emit a MachineInstr with one register operand and two immediate /// operands. Register fastEmitInst_rii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, - bool Op0IsKill, uint64_t Imm1, uint64_t Imm2); + uint64_t Imm1, uint64_t Imm2); /// Emit a MachineInstr with a floating point immediate, and a result /// register in the given register class. @@ -425,8 +422,7 @@ protected: /// result register in the given register class. Register fastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, - bool Op0IsKill, unsigned Op1, bool Op1IsKill, - uint64_t Imm); + unsigned Op1, uint64_t Imm); /// Emit a MachineInstr with a single immediate operand, and a result /// register in the given register class. @@ -435,12 +431,11 @@ protected: /// Emit a MachineInstr for an extract_subreg from a specified index of /// a superregister to a specified type. - Register fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill, - uint32_t Idx); + Register fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, uint32_t Idx); /// Emit MachineInstrs to compute the value of Op with all but the /// least significant bit set to zero. - Register fastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill); + Register fastEmitZExtFromI1(MVT VT, unsigned Op0); /// Emit an unconditional branch to the given block, unless it is the /// immediate (fall-through) successor, and update the CFG. @@ -490,9 +485,6 @@ protected: /// - \c Add has a constant operand. bool canFoldAddIntoGEP(const User *GEP, const Value *Add); - /// Test whether the given value has exactly one use. - bool hasTrivialKill(const Value *V); - /// Create a machine mem operand from the given instruction. MachineMemOperand *createMachineMemOperandFor(const Instruction *I) const; |