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-rw-r--r--llvm/include/llvm/CodeGen/MachineFunction.h127
1 files changed, 114 insertions, 13 deletions
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h
index e9979c788ce0..786fe908f68f 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -124,11 +124,14 @@ public:
// NoPHIs: The machine function does not contain any PHI instruction.
// TracksLiveness: True when tracking register liveness accurately.
// While this property is set, register liveness information in basic block
- // live-in lists and machine instruction operands (e.g. kill flags, implicit
- // defs) is accurate. This means it can be used to change the code in ways
- // that affect the values in registers, for example by the register
- // scavenger.
- // When this property is clear, liveness is no longer reliable.
+ // live-in lists and machine instruction operands (e.g. implicit defs) is
+ // accurate, kill flags are conservatively accurate (kill flag correctly
+ // indicates the last use of a register, an operand without kill flag may or
+ // may not be the last use of a register). This means it can be used to
+ // change the code in ways that affect the values in registers, for example
+ // by the register scavenger.
+ // When this property is cleared at a very late time, liveness is no longer
+ // reliable.
// NoVRegs: The machine function does not use any virtual registers.
// Legalized: In GlobalISel: the MachineLegalizer ran and all pre-isel generic
// instructions have been legalized; i.e., all instructions are now one of:
@@ -321,6 +324,10 @@ class MachineFunction {
/// construct a table of valid longjmp targets for Windows Control Flow Guard.
std::vector<MCSymbol *> LongjmpTargets;
+ /// List of basic blocks that are the target of catchrets. Used to construct
+ /// a table of valid targets for Windows EHCont Guard.
+ std::vector<MCSymbol *> CatchretTargets;
+
/// \name Exception Handling
/// \{
@@ -341,6 +348,7 @@ class MachineFunction {
bool CallsEHReturn = false;
bool CallsUnwindInit = false;
+ bool HasEHCatchret = false;
bool HasEHScopes = false;
bool HasEHFunclets = false;
@@ -443,15 +451,60 @@ public:
/// Pair of instruction number and operand number.
using DebugInstrOperandPair = std::pair<unsigned, unsigned>;
- /// Substitution map: from one <inst,operand> pair to another. Used to
- /// record changes in where a value is defined, so that debug variable
- /// locations can find it later.
- std::map<DebugInstrOperandPair, DebugInstrOperandPair>
- DebugValueSubstitutions;
+ /// Replacement definition for a debug instruction reference. Made up of a
+ /// source instruction / operand pair, destination pair, and a qualifying
+ /// subregister indicating what bits in the operand make up the substitution.
+ // For example, a debug user
+ /// of %1:
+ /// %0:gr32 = someinst, debug-instr-number 1
+ /// %1:gr16 = %0.some_16_bit_subreg, debug-instr-number 2
+ /// Would receive the substitution {{2, 0}, {1, 0}, $subreg}, where $subreg is
+ /// the subregister number for some_16_bit_subreg.
+ class DebugSubstitution {
+ public:
+ DebugInstrOperandPair Src; ///< Source instruction / operand pair.
+ DebugInstrOperandPair Dest; ///< Replacement instruction / operand pair.
+ unsigned Subreg; ///< Qualifier for which part of Dest is read.
+
+ DebugSubstitution(const DebugInstrOperandPair &Src,
+ const DebugInstrOperandPair &Dest, unsigned Subreg)
+ : Src(Src), Dest(Dest), Subreg(Subreg) {}
+
+ /// Order only by source instruction / operand pair: there should never
+ /// be duplicate entries for the same source in any collection.
+ bool operator<(const DebugSubstitution &Other) const {
+ return Src < Other.Src;
+ }
+ };
+
+ /// Debug value substitutions: a collection of DebugSubstitution objects,
+ /// recording changes in where a value is defined. For example, when one
+ /// instruction is substituted for another. Keeping a record allows recovery
+ /// of variable locations after compilation finishes.
+ SmallVector<DebugSubstitution, 8> DebugValueSubstitutions;
+
+ /// Location of a PHI instruction that is also a debug-info variable value,
+ /// for the duration of register allocation. Loaded by the PHI-elimination
+ /// pass, and emitted as DBG_PHI instructions during VirtRegRewriter, with
+ /// maintenance applied by intermediate passes that edit registers (such as
+ /// coalescing and the allocator passes).
+ class DebugPHIRegallocPos {
+ public:
+ MachineBasicBlock *MBB; ///< Block where this PHI was originally located.
+ Register Reg; ///< VReg where the control-flow-merge happens.
+ unsigned SubReg; ///< Optional subreg qualifier within Reg.
+ DebugPHIRegallocPos(MachineBasicBlock *MBB, Register Reg, unsigned SubReg)
+ : MBB(MBB), Reg(Reg), SubReg(SubReg) {}
+ };
+
+ /// Map of debug instruction numbers to the position of their PHI instructions
+ /// during register allocation. See DebugPHIRegallocPos.
+ DenseMap<unsigned, DebugPHIRegallocPos> DebugPHIPositions;
/// Create a substitution between one <instr,operand> value to a different,
/// new value.
- void makeDebugValueSubstitution(DebugInstrOperandPair, DebugInstrOperandPair);
+ void makeDebugValueSubstitution(DebugInstrOperandPair, DebugInstrOperandPair,
+ unsigned SubReg = 0);
/// Create substitutions for any tracked values in \p Old, to point at
/// \p New. Needed when we re-create an instruction during optimization,
@@ -464,6 +517,25 @@ public:
void substituteDebugValuesForInst(const MachineInstr &Old, MachineInstr &New,
unsigned MaxOperand = UINT_MAX);
+ /// Find the underlying defining instruction / operand for a COPY instruction
+ /// while in SSA form. Copies do not actually define values -- they move them
+ /// between registers. Labelling a COPY-like instruction with an instruction
+ /// number is to be avoided as it makes value numbers non-unique later in
+ /// compilation. This method follows the definition chain for any sequence of
+ /// COPY-like instructions to find whatever non-COPY-like instruction defines
+ /// the copied value; or for parameters, creates a DBG_PHI on entry.
+ /// May insert instructions into the entry block!
+ /// \p MI The copy-like instruction to salvage.
+ /// \returns An instruction/operand pair identifying the defining value.
+ DebugInstrOperandPair salvageCopySSA(MachineInstr &MI);
+
+ /// Finalise any partially emitted debug instructions. These are DBG_INSTR_REF
+ /// instructions where we only knew the vreg of the value they use, not the
+ /// instruction that defines that vreg. Once isel finishes, we should have
+ /// enough information for every DBG_INSTR_REF to point at an instruction
+ /// (or DBG_PHI).
+ void finalizeDebugInstrRefs();
+
MachineFunction(Function &F, const LLVMTargetMachine &Target,
const TargetSubtargetInfo &STI, unsigned FunctionNum,
MachineModuleInfo &MMI);
@@ -839,20 +911,34 @@ public:
AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
+ MachineMemOperand *getMachineMemOperand(
+ MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy,
+ Align base_alignment, const AAMDNodes &AAInfo = AAMDNodes(),
+ const MDNode *Ranges = nullptr, SyncScope::ID SSID = SyncScope::System,
+ AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
+ AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
+
/// getMachineMemOperand - Allocate a new MachineMemOperand by copying
/// an existing one, adjusting by an offset and using the given size.
/// MachineMemOperands are owned by the MachineFunction and need not be
/// explicitly deallocated.
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
- int64_t Offset, uint64_t Size);
+ int64_t Offset, LLT Ty);
+ MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
+ int64_t Offset, uint64_t Size) {
+ return getMachineMemOperand(MMO, Offset, LLT::scalar(8 * Size));
+ }
/// getMachineMemOperand - Allocate a new MachineMemOperand by copying
/// an existing one, replacing only the MachinePointerInfo and size.
/// MachineMemOperands are owned by the MachineFunction and need not be
/// explicitly deallocated.
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
- MachinePointerInfo &PtrInfo,
+ const MachinePointerInfo &PtrInfo,
uint64_t Size);
+ MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
+ const MachinePointerInfo &PtrInfo,
+ LLT Ty);
/// Allocate a new MachineMemOperand by copying an existing one,
/// replacing only AliasAnalysis information. MachineMemOperands are owned
@@ -930,6 +1016,18 @@ public:
/// Control Flow Guard.
void addLongjmpTarget(MCSymbol *Target) { LongjmpTargets.push_back(Target); }
+ /// Returns a reference to a list of symbols that we have catchrets.
+ /// Used to construct the catchret target table used by Windows EHCont Guard.
+ const std::vector<MCSymbol *> &getCatchretTargets() const {
+ return CatchretTargets;
+ }
+
+ /// Add the specified symbol to the list of valid catchret targets for Windows
+ /// EHCont Guard.
+ void addCatchretTarget(MCSymbol *Target) {
+ CatchretTargets.push_back(Target);
+ }
+
/// \name Exception Handling
/// \{
@@ -939,6 +1037,9 @@ public:
bool callsUnwindInit() const { return CallsUnwindInit; }
void setCallsUnwindInit(bool b) { CallsUnwindInit = b; }
+ bool hasEHCatchret() const { return HasEHCatchret; }
+ void setHasEHCatchret(bool V) { HasEHCatchret = V; }
+
bool hasEHScopes() const { return HasEHScopes; }
void setHasEHScopes(bool V) { HasEHScopes = V; }