diff options
Diffstat (limited to 'llvm/include/llvm/CodeGen/TargetRegisterInfo.h')
| -rw-r--r-- | llvm/include/llvm/CodeGen/TargetRegisterInfo.h | 75 |
1 files changed, 59 insertions, 16 deletions
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h index 8790e2f09eb6..92ce5b737090 100644 --- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h +++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h @@ -209,8 +209,10 @@ public: /// Extra information, not in MCRegisterDesc, about registers. /// These are used by codegen, not by MC. struct TargetRegisterInfoDesc { - unsigned CostPerUse; // Extra cost of instructions using register. - bool inAllocatableClass; // Register belongs to an allocatable regclass. + const uint8_t *CostPerUse; // Extra cost of instructions using register. + unsigned NumCosts; // Number of cost values associated with each register. + const bool + *InAllocatableClass; // Register belongs to an allocatable regclass. }; /// Each TargetRegisterClass has a per register weight, and weight @@ -281,12 +283,6 @@ public: /// Return the minimum required alignment in bytes for a spill slot for /// a register of this class. - unsigned getSpillAlignment(const TargetRegisterClass &RC) const { - return getRegClassInfo(RC).SpillAlignment / 8; - } - - /// Return the minimum required alignment in bytes for a spill slot for - /// a register of this class. Align getSpillAlign(const TargetRegisterClass &RC) const { return Align(getRegClassInfo(RC).SpillAlignment / 8); } @@ -299,6 +295,19 @@ public: return false; } + /// Return true if the given TargetRegisterClass is compatible with LLT T. + bool isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const { + for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I) { + MVT VT(*I); + if (VT == MVT::Untyped) + return true; + + if (LLT(VT) == T) + return true; + } + return false; + } + /// Loop over all of the value types that can be represented by values /// in the given register class. vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const { @@ -318,6 +327,13 @@ public: const TargetRegisterClass *getMinimalPhysRegClass(MCRegister Reg, MVT VT = MVT::Other) const; + /// Returns the Register Class of a physical register of the given type, + /// picking the most sub register class of the right type that contains this + /// physreg. If there is no register class compatible with the given type, + /// returns nullptr. + const TargetRegisterClass *getMinimalPhysRegClassLLT(MCRegister Reg, + LLT Ty = LLT()) const; + /// Return the maximal subclass of the given register class that is /// allocatable or NULL. const TargetRegisterClass * @@ -329,15 +345,19 @@ public: BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC = nullptr) const; - /// Return the additional cost of using this register instead - /// of other registers in its class. - unsigned getCostPerUse(MCRegister RegNo) const { - return InfoDesc[RegNo].CostPerUse; + /// Get a list of cost values for all registers that correspond to the index + /// returned by RegisterCostTableIndex. + ArrayRef<uint8_t> getRegisterCosts(const MachineFunction &MF) const { + unsigned Idx = getRegisterCostTableIndex(MF); + unsigned NumRegs = getNumRegs(); + assert(Idx < InfoDesc->NumCosts && "CostPerUse index out of bounds"); + + return makeArrayRef(&InfoDesc->CostPerUse[Idx * NumRegs], NumRegs); } /// Return true if the register is in the allocation of any register class. bool isInAllocatableClass(MCRegister RegNo) const { - return InfoDesc[RegNo].inAllocatableClass; + return InfoDesc->InAllocatableClass[RegNo]; } /// Return the human-readable symbolic target-specific @@ -357,6 +377,15 @@ public: return SubRegIndexLaneMasks[SubIdx]; } + /// Try to find one or more subregister indexes to cover \p LaneMask. + /// + /// If this is possible, returns true and appends the best matching set of + /// indexes to \p Indexes. If this is not possible, returns false. + bool getCoveringSubRegIndexes(const MachineRegisterInfo &MRI, + const TargetRegisterClass *RC, + LaneBitmask LaneMask, + SmallVectorImpl<unsigned> &Indexes) const; + /// The lane masks returned by getSubRegIndexLaneMask() above can only be /// used to determine if sub-registers overlap - they can't be used to /// determine if a set of sub-registers completely cover another @@ -648,6 +677,13 @@ protected: llvm_unreachable("Target has no sub-registers"); } + /// Return the register cost table index. This implementation is sufficient + /// for most architectures and can be overriden by targets in case there are + /// multiple cost values associated with each register. + virtual unsigned getRegisterCostTableIndex(const MachineFunction &MF) const { + return 0; + } + public: /// Find a common super-register class if it exists. /// @@ -835,6 +871,10 @@ public: /// (3) Bottom-up allocation is no longer guaranteed to optimally color. virtual bool reverseLocalAssignment() const { return false; } + /// Add the allocation priority to global and split ranges as well as the + /// local ranges when registers are added to the queue. + virtual bool addAllocPriorityToGlobalRanges() const { return false; } + /// Allow the target to override the cost of using a callee-saved register for /// the first time. Default value of 0 means we will use a callee-saved /// register if it is available. @@ -892,9 +932,12 @@ public: /// True if storage within the function requires the stack pointer to be /// aligned more than the normal calling convention calls for. - /// This cannot be overriden by the target, but canRealignStack can be - /// overridden. - bool needsStackRealignment(const MachineFunction &MF) const; + virtual bool shouldRealignStack(const MachineFunction &MF) const; + + /// True if stack realignment is required and still possible. + bool hasStackRealignment(const MachineFunction &MF) const { + return shouldRealignStack(MF) && canRealignStack(MF); + } /// Get the offset from the referenced frame index in the instruction, /// if there is one. |