diff options
Diffstat (limited to 'llvm/include/llvm/CodeGen')
40 files changed, 223 insertions, 109 deletions
diff --git a/llvm/include/llvm/CodeGen/AsmPrinter.h b/llvm/include/llvm/CodeGen/AsmPrinter.h index 281ecb8de251..d911bfd435ae 100644 --- a/llvm/include/llvm/CodeGen/AsmPrinter.h +++ b/llvm/include/llvm/CodeGen/AsmPrinter.h @@ -17,6 +17,7 @@ #include "llvm/ADT/MapVector.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/BinaryFormat/Dwarf.h" #include "llvm/CodeGen/AsmPrinterHandler.h" #include "llvm/CodeGen/DwarfStringPoolEntry.h" #include "llvm/CodeGen/MachineFunctionPass.h" @@ -231,6 +232,9 @@ public: /// Returns 4 for DWARF32 and 12 for DWARF64. unsigned int getUnitLengthFieldByteSize() const; + /// Returns information about the byte size of DW_FORM values. + dwarf::FormParams getDwarfFormParams() const; + bool isPositionIndependent() const; /// Return true if assembly output should contain comments. @@ -431,7 +435,8 @@ public: /// global value is specified, and if that global has an explicit alignment /// requested, it will override the alignment request if required for /// correctness. - void emitAlignment(Align Alignment, const GlobalObject *GV = nullptr) const; + void emitAlignment(Align Alignment, const GlobalObject *GV = nullptr, + unsigned MaxBytesToEmit = 0) const; /// Lower the specified LLVM Constant to an MCExpr. virtual const MCExpr *lowerConstant(const Constant *CV); diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h index 324b7dcfb3ac..0b2737628923 100644 --- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h +++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h @@ -875,14 +875,18 @@ public: switch (improveShuffleKindFromMask(Kind, Mask)) { case TTI::SK_Broadcast: - return getBroadcastShuffleOverhead(cast<FixedVectorType>(Tp)); + if (auto *FVT = dyn_cast<FixedVectorType>(Tp)) + return getBroadcastShuffleOverhead(FVT); + return InstructionCost::getInvalid(); case TTI::SK_Select: case TTI::SK_Splice: case TTI::SK_Reverse: case TTI::SK_Transpose: case TTI::SK_PermuteSingleSrc: case TTI::SK_PermuteTwoSrc: - return getPermuteShuffleOverhead(cast<FixedVectorType>(Tp)); + if (auto *FVT = dyn_cast<FixedVectorType>(Tp)) + return getPermuteShuffleOverhead(FVT); + return InstructionCost::getInvalid(); case TTI::SK_ExtractSubvector: return getExtractSubvectorOverhead(Tp, Index, cast<FixedVectorType>(SubTp)); diff --git a/llvm/include/llvm/CodeGen/CalcSpillWeights.h b/llvm/include/llvm/CodeGen/CalcSpillWeights.h index 0b6ed079b38e..bfd5bab3d1c0 100644 --- a/llvm/include/llvm/CodeGen/CalcSpillWeights.h +++ b/llvm/include/llvm/CodeGen/CalcSpillWeights.h @@ -80,6 +80,18 @@ class VirtRegMap; /// live intervals. void calculateSpillWeightsAndHints(); + /// Return the preferred allocation register for reg, given a COPY + /// instruction. + static Register copyHint(const MachineInstr *MI, unsigned Reg, + const TargetRegisterInfo &TRI, + const MachineRegisterInfo &MRI); + + /// Determine if all values in LI are rematerializable. + static bool isRematerializable(const LiveInterval &LI, + const LiveIntervals &LIS, + const VirtRegMap &VRM, + const TargetInstrInfo &TII); + protected: /// Helper function for weight calculations. /// (Re)compute LI's spill weight and allocation hint, or, for non null diff --git a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h index 1fd07ca2c8d4..f6563971f981 100644 --- a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h +++ b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h @@ -159,7 +159,7 @@ protected: class AddIRPass { public: AddIRPass(ModulePassManager &MPM, bool DebugPM, bool Check = true) - : MPM(MPM), FPM() { + : MPM(MPM) { if (Check) AddingFunctionPasses = false; } diff --git a/llvm/include/llvm/CodeGen/DIE.h b/llvm/include/llvm/CodeGen/DIE.h index 9e94c401bfae..32df448b91a1 100644 --- a/llvm/include/llvm/CodeGen/DIE.h +++ b/llvm/include/llvm/CodeGen/DIE.h @@ -191,7 +191,7 @@ public: void setValue(uint64_t Val) { Integer = Val; } void emitValue(const AsmPrinter *Asm, dwarf::Form Form) const; - unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const; + unsigned sizeOf(const dwarf::FormParams &FormParams, dwarf::Form Form) const; void print(raw_ostream &O) const; }; @@ -208,7 +208,7 @@ public: const MCExpr *getValue() const { return Expr; } void emitValue(const AsmPrinter *AP, dwarf::Form Form) const; - unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const; + unsigned sizeOf(const dwarf::FormParams &FormParams, dwarf::Form Form) const; void print(raw_ostream &O) const; }; @@ -225,7 +225,7 @@ public: const MCSymbol *getValue() const { return Label; } void emitValue(const AsmPrinter *AP, dwarf::Form Form) const; - unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const; + unsigned sizeOf(const dwarf::FormParams &FormParams, dwarf::Form Form) const; void print(raw_ostream &O) const; }; @@ -243,8 +243,8 @@ public: /// EmitValue - Emit base type reference. void emitValue(const AsmPrinter *AP, dwarf::Form Form) const; - /// SizeOf - Determine size of the base type reference in bytes. - unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const; + /// sizeOf - Determine size of the base type reference in bytes. + unsigned sizeOf(const dwarf::FormParams &, dwarf::Form) const; void print(raw_ostream &O) const; uint64_t getIndex() const { return Index; } @@ -261,7 +261,7 @@ public: DIEDelta(const MCSymbol *Hi, const MCSymbol *Lo) : LabelHi(Hi), LabelLo(Lo) {} void emitValue(const AsmPrinter *AP, dwarf::Form Form) const; - unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const; + unsigned sizeOf(const dwarf::FormParams &FormParams, dwarf::Form Form) const; void print(raw_ostream &O) const; }; @@ -280,7 +280,7 @@ public: StringRef getString() const { return S.getString(); } void emitValue(const AsmPrinter *AP, dwarf::Form Form) const; - unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const; + unsigned sizeOf(const dwarf::FormParams &FormParams, dwarf::Form Form) const; void print(raw_ostream &O) const; }; @@ -302,7 +302,7 @@ public: StringRef getString() const { return S; } void emitValue(const AsmPrinter *AP, dwarf::Form Form) const; - unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const; + unsigned sizeOf(const dwarf::FormParams &, dwarf::Form) const; void print(raw_ostream &O) const; }; @@ -321,7 +321,7 @@ public: DIE &getEntry() const { return *Entry; } void emitValue(const AsmPrinter *AP, dwarf::Form Form) const; - unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const; + unsigned sizeOf(const dwarf::FormParams &FormParams, dwarf::Form Form) const; void print(raw_ostream &O) const; }; @@ -340,7 +340,7 @@ public: size_t getValue() const { return Index; } void emitValue(const AsmPrinter *AP, dwarf::Form Form) const; - unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const; + unsigned sizeOf(const dwarf::FormParams &FormParams, dwarf::Form Form) const; void print(raw_ostream &O) const; }; @@ -356,7 +356,7 @@ public: : Addr(Idx), Offset(Hi, Lo) {} void emitValue(const AsmPrinter *AP, dwarf::Form Form) const; - unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const; + unsigned sizeOf(const dwarf::FormParams &FormParams, dwarf::Form Form) const; void print(raw_ostream &O) const; }; @@ -506,7 +506,7 @@ public: void emitValue(const AsmPrinter *AP) const; /// Return the size of a value in bytes. - unsigned SizeOf(const AsmPrinter *AP) const; + unsigned sizeOf(const dwarf::FormParams &FormParams) const; void print(raw_ostream &O) const; void dump() const; @@ -774,8 +774,16 @@ public: unsigned getAbbrevNumber() const { return AbbrevNumber; } dwarf::Tag getTag() const { return Tag; } /// Get the compile/type unit relative offset of this DIE. - unsigned getOffset() const { return Offset; } - unsigned getSize() const { return Size; } + unsigned getOffset() const { + // A real Offset can't be zero because the unit headers are at offset zero. + assert(Offset && "Offset being queried before it's been computed."); + return Offset; + } + unsigned getSize() const { + // A real Size can't be zero because it includes the non-empty abbrev code. + assert(Size && "Size being queried before it's been ocmputed."); + return Size; + } bool hasChildren() const { return ForceChildren || !Children.empty(); } void setForceChildren(bool B) { ForceChildren = B; } @@ -817,12 +825,12 @@ public: /// properly refer to other DIE objects since all DIEs have calculated their /// offsets. /// - /// \param AP AsmPrinter to use when calculating sizes. + /// \param FormParams Used when calculating sizes. /// \param AbbrevSet the abbreviation used to unique DIE abbreviations. /// \param CUOffset the compile/type unit relative offset in bytes. /// \returns the offset for the DIE that follows this DIE within the /// current compile/type unit. - unsigned computeOffsetsAndAbbrevs(const AsmPrinter *AP, + unsigned computeOffsetsAndAbbrevs(const dwarf::FormParams &FormParams, DIEAbbrevSet &AbbrevSet, unsigned CUOffset); /// Climb up the parent chain to get the compile unit or type unit DIE that @@ -925,9 +933,8 @@ class DIELoc : public DIEValueList { public: DIELoc() = default; - /// ComputeSize - Calculate the size of the location expression. - /// - unsigned ComputeSize(const AsmPrinter *AP) const; + /// Calculate the size of the location expression. + unsigned computeSize(const dwarf::FormParams &FormParams) const; // TODO: move setSize() and Size to DIEValueList. void setSize(unsigned size) { Size = size; } @@ -948,7 +955,7 @@ public: } void emitValue(const AsmPrinter *Asm, dwarf::Form Form) const; - unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const; + unsigned sizeOf(const dwarf::FormParams &, dwarf::Form Form) const; void print(raw_ostream &O) const; }; @@ -962,9 +969,8 @@ class DIEBlock : public DIEValueList { public: DIEBlock() = default; - /// ComputeSize - Calculate the size of the location expression. - /// - unsigned ComputeSize(const AsmPrinter *AP) const; + /// Calculate the size of the location expression. + unsigned computeSize(const dwarf::FormParams &FormParams) const; // TODO: move setSize() and Size to DIEValueList. void setSize(unsigned size) { Size = size; } @@ -982,7 +988,7 @@ public: } void emitValue(const AsmPrinter *Asm, dwarf::Form Form) const; - unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const; + unsigned sizeOf(const dwarf::FormParams &, dwarf::Form Form) const; void print(raw_ostream &O) const; }; diff --git a/llvm/include/llvm/CodeGen/DbgEntityHistoryCalculator.h b/llvm/include/llvm/CodeGen/DbgEntityHistoryCalculator.h index e7425dd3dc04..2ac9d938d281 100644 --- a/llvm/include/llvm/CodeGen/DbgEntityHistoryCalculator.h +++ b/llvm/include/llvm/CodeGen/DbgEntityHistoryCalculator.h @@ -17,7 +17,6 @@ namespace llvm { -class DILocalVariable; class DILocation; class DINode; class MachineFunction; diff --git a/llvm/include/llvm/CodeGen/FaultMaps.h b/llvm/include/llvm/CodeGen/FaultMaps.h index 12d2872c8c5b..8a8b1d2e6008 100644 --- a/llvm/include/llvm/CodeGen/FaultMaps.h +++ b/llvm/include/llvm/CodeGen/FaultMaps.h @@ -18,7 +18,6 @@ namespace llvm { class AsmPrinter; class MCExpr; -class raw_ostream; class FaultMaps { public: diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h index 9c878d4b087b..3a4b3ee18e1b 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h @@ -95,7 +95,7 @@ public: bool IsFixed = true) : ArgInfo(Regs, OrigValue.getType(), OrigIndex, Flags, IsFixed, &OrigValue) {} - ArgInfo() : BaseArgInfo() {} + ArgInfo() {} }; struct CallLoweringInfo { @@ -388,12 +388,12 @@ protected: /// \p Handler to move them to the assigned locations. /// /// \return True if everything has succeeded, false otherwise. - bool determineAndHandleAssignments(ValueHandler &Handler, - ValueAssigner &Assigner, - SmallVectorImpl<ArgInfo> &Args, - MachineIRBuilder &MIRBuilder, - CallingConv::ID CallConv, bool IsVarArg, - Register ThisReturnReg = Register()) const; + bool + determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, + SmallVectorImpl<ArgInfo> &Args, + MachineIRBuilder &MIRBuilder, + CallingConv::ID CallConv, bool IsVarArg, + ArrayRef<Register> ThisReturnRegs = None) const; /// Use \p Handler to insert code to handle the argument/return values /// represented by \p Args. It's expected determineAssignments previously @@ -402,7 +402,7 @@ protected: CCState &CCState, SmallVectorImpl<CCValAssign> &ArgLocs, MachineIRBuilder &MIRBuilder, - Register ThisReturnReg = Register()) const; + ArrayRef<Register> ThisReturnRegs = None) const; /// Check whether parameters to a call that are passed in callee saved /// registers are the same as from the calling function. This needs to be diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h index f3fa652b0175..45c27c25aea0 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h @@ -323,6 +323,11 @@ public: void applyCombineUnmergeConstant(MachineInstr &MI, SmallVectorImpl<APInt> &Csts); + /// Transform G_UNMERGE G_IMPLICIT_DEF -> G_IMPLICIT_DEF, G_IMPLICIT_DEF, ... + bool + matchCombineUnmergeUndef(MachineInstr &MI, + std::function<void(MachineIRBuilder &)> &MatchInfo); + /// Transform X, Y<dead> = G_UNMERGE Z -> X = G_TRUNC Z. bool matchCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI); void applyCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI); @@ -353,8 +358,8 @@ public: std::pair<Register, bool> &PtrRegAndCommute); // Transform G_PTR_ADD (G_PTRTOINT C1), C2 -> C1 + C2 - bool matchCombineConstPtrAddToI2P(MachineInstr &MI, int64_t &NewCst); - void applyCombineConstPtrAddToI2P(MachineInstr &MI, int64_t &NewCst); + bool matchCombineConstPtrAddToI2P(MachineInstr &MI, APInt &NewCst); + void applyCombineConstPtrAddToI2P(MachineInstr &MI, APInt &NewCst); /// Transform anyext(trunc(x)) to x. bool matchCombineAnyExtTrunc(MachineInstr &MI, Register &Reg); diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CombinerInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/CombinerInfo.h index 4a1a4ff2528a..e73f8489497e 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/CombinerInfo.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/CombinerInfo.h @@ -20,7 +20,6 @@ class GISelChangeObserver; class LegalizerInfo; class MachineInstr; class MachineIRBuilder; -class MachineRegisterInfo; // Contains information relevant to enabling/disabling various combines for a // pass. diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GISelWorkList.h b/llvm/include/llvm/CodeGen/GlobalISel/GISelWorkList.h index c5af64d2bcbe..7d198fada411 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/GISelWorkList.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/GISelWorkList.h @@ -15,7 +15,6 @@ namespace llvm { class MachineInstr; -class MachineFunction; // Worklist which mostly works similar to InstCombineWorkList, but on // MachineInstrs. The main difference with something like a SetVector is that diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h index 886b3af834d7..38d2fe28063a 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h @@ -487,7 +487,8 @@ public: // That is not done yet. if (ConvertOp == 0) return true; - return !DestTy.isVector() && OpTy.isVector(); + return !DestTy.isVector() && OpTy.isVector() && + DestTy == OpTy.getElementType(); case TargetOpcode::G_CONCAT_VECTORS: { if (ConvertOp == 0) return true; @@ -977,10 +978,13 @@ public: Builder.setInstr(MI); for (unsigned Idx = 0; Idx < NumDefs; ++Idx) { - Register MergeSrc = MergeI->getOperand(Idx + 1).getReg(); Register DefReg = MI.getOperand(Idx).getReg(); - Builder.buildInstr(ConvertOp, {DefReg}, {MergeSrc}); - UpdatedDefs.push_back(DefReg); + Register MergeSrc = MergeI->getOperand(Idx + 1).getReg(); + + if (!MRI.use_empty(DefReg)) { + Builder.buildInstr(ConvertOp, {DefReg}, {MergeSrc}); + UpdatedDefs.push_back(DefReg); + } } markInstAndDefDead(MI, *MergeI, DeadInsts); diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Legalizer.h b/llvm/include/llvm/CodeGen/GlobalISel/Legalizer.h index 4871d8d32ebd..c19f1d5330ba 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/Legalizer.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/Legalizer.h @@ -25,7 +25,6 @@ namespace llvm { -class MachineRegisterInfo; class LostDebugLocObserver; class Legalizer : public MachineFunctionPass { diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h index 044f2e22cfdd..3b2f937375eb 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h @@ -30,7 +30,6 @@ namespace llvm { // Forward declarations. class LegalizerInfo; -class Legalizer; class MachineRegisterInfo; class GISelChangeObserver; class LostDebugLocObserver; diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h index 0b37539030b1..9507c3411b5c 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h @@ -38,7 +38,6 @@ class LegalizerHelper; class MachineInstr; class MachineRegisterInfo; class MCInstrInfo; -class GISelChangeObserver; namespace LegalizeActions { enum LegalizeAction : std::uint8_t { @@ -557,7 +556,7 @@ class LegalizeRuleSet { } public: - LegalizeRuleSet() : AliasOf(0), IsAliasedByAnother(false), Rules() {} + LegalizeRuleSet() : AliasOf(0), IsAliasedByAnother(false) {} bool isAliasedByAnother() { return IsAliasedByAnother; } void setIsAliasedByAnother() { IsAliasedByAnother = true; } diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LoadStoreOpt.h b/llvm/include/llvm/CodeGen/GlobalISel/LoadStoreOpt.h index 29575f386d7a..0845c001abdb 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/LoadStoreOpt.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/LoadStoreOpt.h @@ -30,7 +30,6 @@ namespace llvm { // Forward declarations. class MachineRegisterInfo; -class TargetTransformInfo; namespace GISelAddressing { /// Helper struct to store a base, index and offset that forms an address struct BaseIndexOffset { diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h b/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h index 28bb8de11762..daf1ff052983 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h @@ -13,6 +13,7 @@ #ifndef LLVM_CODEGEN_GLOBALISEL_MIPATTERNMATCH_H #define LLVM_CODEGEN_GLOBALISEL_MIPATTERNMATCH_H +#include "llvm/ADT/APInt.h" #include "llvm/CodeGen/GlobalISel/Utils.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/IR/InstrTypes.h" @@ -59,11 +60,26 @@ inline OneNonDBGUse_match<SubPat> m_OneNonDBGUse(const SubPat &SP) { return SP; } -struct ConstantMatch { - int64_t &CR; - ConstantMatch(int64_t &C) : CR(C) {} +template <typename ConstT> +inline Optional<ConstT> matchConstant(Register, const MachineRegisterInfo &); + +template <> +inline Optional<APInt> matchConstant(Register Reg, + const MachineRegisterInfo &MRI) { + return getIConstantVRegVal(Reg, MRI); +} + +template <> +inline Optional<int64_t> matchConstant(Register Reg, + const MachineRegisterInfo &MRI) { + return getIConstantVRegSExtVal(Reg, MRI); +} + +template <typename ConstT> struct ConstantMatch { + ConstT &CR; + ConstantMatch(ConstT &C) : CR(C) {} bool match(const MachineRegisterInfo &MRI, Register Reg) { - if (auto MaybeCst = getIConstantVRegSExtVal(Reg, MRI)) { + if (auto MaybeCst = matchConstant<ConstT>(Reg, MRI)) { CR = *MaybeCst; return true; } @@ -71,7 +87,12 @@ struct ConstantMatch { } }; -inline ConstantMatch m_ICst(int64_t &Cst) { return ConstantMatch(Cst); } +inline ConstantMatch<APInt> m_ICst(APInt &Cst) { + return ConstantMatch<APInt>(Cst); +} +inline ConstantMatch<int64_t> m_ICst(int64_t &Cst) { + return ConstantMatch<int64_t>(Cst); +} struct GCstAndRegMatch { Optional<ValueAndVReg> &ValReg; diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h index fde0cb3cf1af..c4c2fc076dd8 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -836,17 +836,38 @@ public: /// \return a MachineInstrBuilder for the newly created instruction. MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op); + + /// Build and insert G_ASSERT_SEXT, G_ASSERT_ZEXT, or G_ASSERT_ALIGN + /// + /// \return a MachineInstrBuilder for the newly created instruction. + MachineInstrBuilder buildAssertOp(unsigned Opc, const DstOp &Res, const SrcOp &Op, + unsigned Val) { + return buildInstr(Opc, Res, Op).addImm(Val); + } + /// Build and insert \p Res = G_ASSERT_ZEXT Op, Size /// /// \return a MachineInstrBuilder for the newly created instruction. MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op, - unsigned Size); + unsigned Size) { + return buildAssertOp(TargetOpcode::G_ASSERT_ZEXT, Res, Op, Size); + } /// Build and insert \p Res = G_ASSERT_SEXT Op, Size /// /// \return a MachineInstrBuilder for the newly created instruction. MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op, - unsigned Size); + unsigned Size) { + return buildAssertOp(TargetOpcode::G_ASSERT_SEXT, Res, Op, Size); + } + + /// Build and insert \p Res = G_ASSERT_ALIGN Op, AlignVal + /// + /// \return a MachineInstrBuilder for the newly created instruction. + MachineInstrBuilder buildAssertAlign(const DstOp &Res, const SrcOp &Op, + Align AlignVal) { + return buildAssertOp(TargetOpcode::G_ASSERT_ALIGN, Res, Op, AlignVal.value()); + } /// Build and insert `Res = G_LOAD Addr, MMO`. /// diff --git a/llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h b/llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h index 5c693d8de521..45006eecfce6 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h @@ -253,7 +253,7 @@ public: public: MBBInsertPoint(MachineBasicBlock &MBB, bool Beginning = true) - : InsertPoint(), MBB(MBB), Beginning(Beginning) { + : MBB(MBB), Beginning(Beginning) { // If we try to insert before phis, we should use the insertion // points on the incoming edges. assert((!Beginning || MBB.getFirstNonPHI() == MBB.begin()) && @@ -299,7 +299,7 @@ public: public: EdgeInsertPoint(MachineBasicBlock &Src, MachineBasicBlock &Dst, Pass &P) - : InsertPoint(), Src(Src), DstOrSplit(&Dst), P(P) {} + : Src(Src), DstOrSplit(&Dst), P(P) {} bool isSplit() const override { return Src.succ_size() > 1 && DstOrSplit->pred_size() > 1; diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h index 8fed79585fe9..aed915d2cc4b 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h @@ -44,7 +44,6 @@ class TargetLowering; class TargetPassConfig; class TargetRegisterInfo; class TargetRegisterClass; -class ConstantInt; class ConstantFP; class APFloat; class MachineIRBuilder; @@ -271,9 +270,10 @@ Optional<APFloat> ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, /// If successful, returns the G_BUILD_VECTOR representing the folded vector /// constant. \p MIB should have an insertion point already set to create new /// G_CONSTANT instructions as needed. -Optional<MachineInstr *> -ConstantFoldVectorBinop(unsigned Opcode, const Register Op1, const Register Op2, - const MachineRegisterInfo &MRI, MachineIRBuilder &MIB); +Register ConstantFoldVectorBinop(unsigned Opcode, const Register Op1, + const Register Op2, + const MachineRegisterInfo &MRI, + MachineIRBuilder &MIB); Optional<APInt> ConstantFoldExtOp(unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI); @@ -311,10 +311,11 @@ Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO); /// /// If there is an existing live-in argument register, it will be returned. /// This will also ensure there is a valid copy -Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, +Register getFunctionLiveInPhysReg(MachineFunction &MF, + const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, - LLT RegTy = LLT()); + const DebugLoc &DL, LLT RegTy = LLT()); /// Return the least common multiple type of \p OrigTy and \p TargetTy, by changing the /// number of vector elements or scalar bitwidth. The intent is a diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h index fd106f55a43d..b07c7cd3db3a 100644 --- a/llvm/include/llvm/CodeGen/ISDOpcodes.h +++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h @@ -797,6 +797,10 @@ enum NodeType { /// The scalar width of the type given in operand 1 must be equal to, or /// smaller than, the scalar result type width. It may end up being smaller /// than the result width as a result of integer type legalization. + /// + /// After converting to the scalar integer type in operand 1, the value is + /// extended to the result VT. FP_TO_SINT_SAT sign extends and FP_TO_UINT_SAT + /// zero extends. FP_TO_SINT_SAT, FP_TO_UINT_SAT, diff --git a/llvm/include/llvm/CodeGen/IndirectThunks.h b/llvm/include/llvm/CodeGen/IndirectThunks.h index 90f9912f0ee0..a2cdd0a9e965 100644 --- a/llvm/include/llvm/CodeGen/IndirectThunks.h +++ b/llvm/include/llvm/CodeGen/IndirectThunks.h @@ -59,7 +59,7 @@ void ThunkInserter<Derived>::createThunkFunction(MachineModuleInfo &MMI, // Add Attributes so that we don't create a frame, unwind information, or // inline. - AttrBuilder B; + AttrBuilder B(Ctx); B.addAttribute(llvm::Attribute::NoUnwind); B.addAttribute(llvm::Attribute::Naked); F->addFnAttrs(B); diff --git a/llvm/include/llvm/CodeGen/LiveInterval.h b/llvm/include/llvm/CodeGen/LiveInterval.h index 923a45821dd4..51ffe2807434 100644 --- a/llvm/include/llvm/CodeGen/LiveInterval.h +++ b/llvm/include/llvm/CodeGen/LiveInterval.h @@ -724,7 +724,7 @@ namespace llvm { T *P; public: - SingleLinkedListIterator<T>(T *P) : P(P) {} + SingleLinkedListIterator(T *P) : P(P) {} SingleLinkedListIterator<T> &operator++() { P = P->Next; diff --git a/llvm/include/llvm/CodeGen/LiveRangeEdit.h b/llvm/include/llvm/CodeGen/LiveRangeEdit.h index fa4e80179eec..d80522f5bdac 100644 --- a/llvm/include/llvm/CodeGen/LiveRangeEdit.h +++ b/llvm/include/llvm/CodeGen/LiveRangeEdit.h @@ -34,9 +34,7 @@ namespace llvm { class AAResults; class LiveIntervals; -class MachineBlockFrequencyInfo; class MachineInstr; -class MachineLoopInfo; class MachineOperand; class TargetInstrInfo; class TargetRegisterInfo; diff --git a/llvm/include/llvm/CodeGen/MIRFormatter.h b/llvm/include/llvm/CodeGen/MIRFormatter.h index 12c90600f6df..3f145ff224ad 100644 --- a/llvm/include/llvm/CodeGen/MIRFormatter.h +++ b/llvm/include/llvm/CodeGen/MIRFormatter.h @@ -23,7 +23,6 @@ namespace llvm { class MachineFunction; class MachineInstr; struct PerFunctionMIParsingState; -struct SlotMapping; /// MIRFormater - Interface to format MIR operand based on target class MIRFormatter { diff --git a/llvm/include/llvm/CodeGen/MachineBasicBlock.h b/llvm/include/llvm/CodeGen/MachineBasicBlock.h index efe22ea8f332..638b6732a543 100644 --- a/llvm/include/llvm/CodeGen/MachineBasicBlock.h +++ b/llvm/include/llvm/CodeGen/MachineBasicBlock.h @@ -136,6 +136,10 @@ private: /// Alignment of the basic block. One if the basic block does not need to be /// aligned. Align Alignment; + /// Maximum amount of bytes that can be added to align the basic block. If the + /// alignment cannot be reached in this many bytes, no bytes are emitted. + /// Zero to represent no maximum. + unsigned MaxBytesForAlignment = 0; /// Indicate that this basic block is entered via an exception handler. bool IsEHPad = false; @@ -521,6 +525,19 @@ public: /// Set alignment of the basic block. void setAlignment(Align A) { Alignment = A; } + void setAlignment(Align A, unsigned MaxBytes) { + setAlignment(A); + setMaxBytesForAlignment(MaxBytes); + } + + /// Return the maximum amount of padding allowed for aligning the basic block. + unsigned getMaxBytesForAlignment() const { return MaxBytesForAlignment; } + + /// Set the maximum amount of padding allowed for aligning the basic block + void setMaxBytesForAlignment(unsigned MaxBytes) { + MaxBytesForAlignment = MaxBytes; + } + /// Returns true if the block is a landing pad. That is this basic block is /// entered via an exception handler. bool isEHPad() const { return IsEHPad; } diff --git a/llvm/include/llvm/CodeGen/MachineLoopUtils.h b/llvm/include/llvm/CodeGen/MachineLoopUtils.h index 2352fbca548d..b9bf93b71e25 100644 --- a/llvm/include/llvm/CodeGen/MachineLoopUtils.h +++ b/llvm/include/llvm/CodeGen/MachineLoopUtils.h @@ -10,7 +10,6 @@ #define LLVM_CODEGEN_MACHINELOOPUTILS_H namespace llvm { -class MachineLoop; class MachineBasicBlock; class MachineRegisterInfo; class TargetInstrInfo; diff --git a/llvm/include/llvm/CodeGen/MachineModuleInfo.h b/llvm/include/llvm/CodeGen/MachineModuleInfo.h index 860a86ee991b..c07606e89374 100644 --- a/llvm/include/llvm/CodeGen/MachineModuleInfo.h +++ b/llvm/include/llvm/CodeGen/MachineModuleInfo.h @@ -44,7 +44,6 @@ namespace llvm { class BasicBlock; -class CallInst; class Function; class LLVMTargetMachine; class MMIAddrLabelMap; diff --git a/llvm/include/llvm/CodeGen/MachinePassManager.h b/llvm/include/llvm/CodeGen/MachinePassManager.h index f967167c65e1..75b8a89c812e 100644 --- a/llvm/include/llvm/CodeGen/MachinePassManager.h +++ b/llvm/include/llvm/CodeGen/MachinePassManager.h @@ -40,10 +40,10 @@ class MachineFunctionAnalysisManager : public AnalysisManager<MachineFunction> { public: using Base = AnalysisManager<MachineFunction>; - MachineFunctionAnalysisManager() : Base(), FAM(nullptr), MAM(nullptr) {} + MachineFunctionAnalysisManager() : FAM(nullptr), MAM(nullptr) {} MachineFunctionAnalysisManager(FunctionAnalysisManager &FAM, ModuleAnalysisManager &MAM) - : Base(), FAM(&FAM), MAM(&MAM) {} + : FAM(&FAM), MAM(&MAM) {} MachineFunctionAnalysisManager(MachineFunctionAnalysisManager &&) = default; MachineFunctionAnalysisManager & operator=(MachineFunctionAnalysisManager &&) = default; @@ -135,7 +135,7 @@ public: MachineFunctionPassManager(bool DebugLogging = false, bool RequireCodeGenSCCOrder = false, bool VerifyMachineFunction = false) - : Base(), RequireCodeGenSCCOrder(RequireCodeGenSCCOrder), + : RequireCodeGenSCCOrder(RequireCodeGenSCCOrder), VerifyMachineFunction(VerifyMachineFunction) {} MachineFunctionPassManager(MachineFunctionPassManager &&) = default; MachineFunctionPassManager & diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h index e368fd7d056a..267c4b595eec 100644 --- a/llvm/include/llvm/CodeGen/MachineScheduler.h +++ b/llvm/include/llvm/CodeGen/MachineScheduler.h @@ -425,10 +425,6 @@ protected: IntervalPressure BotPressure; RegPressureTracker BotRPTracker; - /// True if disconnected subregister components are already renamed. - /// The renaming is only done on demand if lane masks are tracked. - bool DisconnectedComponentsRenamed = false; - public: ScheduleDAGMILive(MachineSchedContext *C, std::unique_ptr<MachineSchedStrategy> S) diff --git a/llvm/include/llvm/CodeGen/Passes.h b/llvm/include/llvm/CodeGen/Passes.h index d5ad12fadfa0..616ab1034133 100644 --- a/llvm/include/llvm/CodeGen/Passes.h +++ b/llvm/include/llvm/CodeGen/Passes.h @@ -30,7 +30,6 @@ class MemoryBuffer; class ModulePass; class Pass; class TargetMachine; -class TargetRegisterClass; class raw_ostream; } // End llvm namespace @@ -551,6 +550,10 @@ namespace llvm { /// The pass transforms amx intrinsics to scalar operation if the function has /// optnone attribute or it is O0. FunctionPass *createX86LowerAMXIntrinsicsPass(); + + /// When learning an eviction policy, extract score(reward) information, + /// otherwise this does nothing + FunctionPass *createRegAllocScoringPass(); } // End llvm namespace #endif diff --git a/llvm/include/llvm/CodeGen/SDNodeProperties.td b/llvm/include/llvm/CodeGen/SDNodeProperties.td index d25e0bda26a9..3cb304f47f4b 100644 --- a/llvm/include/llvm/CodeGen/SDNodeProperties.td +++ b/llvm/include/llvm/CodeGen/SDNodeProperties.td @@ -1,4 +1,4 @@ -//===- SDNodeProperties.td - Common code for DAG isels ---*- tablegen -*-===// +//===- SDNodeProperties.td - Common code for DAG isels -----*- tablegen -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h index d21844555f5b..e31719bcff0b 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAG.h +++ b/llvm/include/llvm/CodeGen/SelectionDAG.h @@ -1350,13 +1350,9 @@ public: SDValue getIndexedLoadVP(SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM); SDValue getStoreVP(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, - SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, - Align Alignment, MachineMemOperand::Flags MMOFlags, - const AAMDNodes &AAInfo = AAMDNodes(), - bool IsCompressing = false); - SDValue getStoreVP(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, - SDValue Mask, SDValue EVL, MachineMemOperand *MMO, - bool IsCompressing = false); + SDValue Offset, SDValue Mask, SDValue EVL, EVT MemVT, + MachineMemOperand *MMO, ISD::MemIndexedMode AM, + bool IsTruncating = false, bool IsCompressing = false); SDValue getTruncStoreVP(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, @@ -1833,18 +1829,18 @@ public: unsigned ComputeNumSignBits(SDValue Op, const APInt &DemandedElts, unsigned Depth = 0) const; - /// Get the minimum bit size for this Value \p Op as a signed integer. - /// i.e. x == sext(trunc(x to MinSignedBits) to bitwidth(x)). - /// Similar to the APInt::getMinSignedBits function. + /// Get the upper bound on bit size for this Value \p Op as a signed integer. + /// i.e. x == sext(trunc(x to MaxSignedBits) to bitwidth(x)). + /// Similar to the APInt::getSignificantBits function. /// Helper wrapper to ComputeNumSignBits. - unsigned ComputeMinSignedBits(SDValue Op, unsigned Depth = 0) const; + unsigned ComputeMaxSignificantBits(SDValue Op, unsigned Depth = 0) const; - /// Get the minimum bit size for this Value \p Op as a signed integer. - /// i.e. x == sext(trunc(x to MinSignedBits) to bitwidth(x)). - /// Similar to the APInt::getMinSignedBits function. + /// Get the upper bound on bit size for this Value \p Op as a signed integer. + /// i.e. x == sext(trunc(x to MaxSignedBits) to bitwidth(x)). + /// Similar to the APInt::getSignificantBits function. /// Helper wrapper to ComputeNumSignBits. - unsigned ComputeMinSignedBits(SDValue Op, const APInt &DemandedElts, - unsigned Depth = 0) const; + unsigned ComputeMaxSignificantBits(SDValue Op, const APInt &DemandedElts, + unsigned Depth = 0) const; /// Return true if this function can prove that \p Op is never poison /// and, if \p PoisonOnly is false, does not have undef bits. @@ -2001,6 +1997,9 @@ public: return SplitVector(N, DL, LoVT, HiVT); } + /// Split the explicit vector length parameter of a VP operation. + std::pair<SDValue, SDValue> SplitEVL(SDValue N, EVT VecVT, const SDLoc &DL); + /// Split the node's operand with EXTRACT_SUBVECTOR and /// return the low/high part. std::pair<SDValue, SDValue> SplitVectorOperand(const SDNode *N, unsigned OpNo) diff --git a/llvm/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h b/llvm/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h index 6a3d76be0ed6..0f3af915da64 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h @@ -39,7 +39,7 @@ private: public: BaseIndexOffset() = default; BaseIndexOffset(SDValue Base, SDValue Index, bool IsIndexSignExt) - : Base(Base), Index(Index), Offset(), IsIndexSignExt(IsIndexSignExt) {} + : Base(Base), Index(Index), IsIndexSignExt(IsIndexSignExt) {} BaseIndexOffset(SDValue Base, SDValue Index, int64_t Offset, bool IsIndexSignExt) : Base(Base), Index(Index), Offset(Offset), diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h index 2855e1f1e587..cd62c47abce9 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h @@ -675,6 +675,9 @@ public: } } + /// Test if this node is a vector predication operation. + bool isVPOpcode() const { return ISD::isVPOpcode(getOpcode()); } + /// Test if this node has a post-isel opcode, directly /// corresponding to a MachineInstr opcode. bool isMachineOpcode() const { return NodeType < 0; } diff --git a/llvm/include/llvm/CodeGen/TailDuplicator.h b/llvm/include/llvm/CodeGen/TailDuplicator.h index 6862bb2c3f44..daaa27f72d52 100644 --- a/llvm/include/llvm/CodeGen/TailDuplicator.h +++ b/llvm/include/llvm/CodeGen/TailDuplicator.h @@ -26,7 +26,6 @@ namespace llvm { class MachineBasicBlock; -class MachineBlockFrequencyInfo; class MachineBranchProbabilityInfo; class MachineFunction; class MachineInstr; diff --git a/llvm/include/llvm/CodeGen/TargetFrameLowering.h b/llvm/include/llvm/CodeGen/TargetFrameLowering.h index a855a0797723..f2ca1590fc39 100644 --- a/llvm/include/llvm/CodeGen/TargetFrameLowering.h +++ b/llvm/include/llvm/CodeGen/TargetFrameLowering.h @@ -216,8 +216,8 @@ public: /// With basic block sections, emit callee saved frame moves for basic blocks /// that are in a different section. virtual void - emitCalleeSavedFrameMoves(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI) const {} + emitCalleeSavedFrameMovesFullCFA(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI) const {} /// Replace a StackProbe stub (if any) with the actual probe code inline virtual void inlineStackProbe(MachineFunction &MF, diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h index 58b8e59b68d7..411811d08c18 100644 --- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h +++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h @@ -130,7 +130,7 @@ public: } /// Given \p MO is a PhysReg use return if it can be ignored for the purpose - /// of instruction rematerialization. + /// of instruction rematerialization or sinking. virtual bool isIgnorableUse(const MachineOperand &MO) const { return false; } diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h index b2d82e0cc6e8..bec191570594 100644 --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -63,7 +63,6 @@ namespace llvm { -class BranchProbability; class CCState; class CCValAssign; class Constant; @@ -1802,11 +1801,14 @@ public: /// Return the preferred loop alignment. virtual Align getPrefLoopAlignment(MachineLoop *ML = nullptr) const; + /// Return the maximum amount of bytes allowed to be emitted when padding for + /// alignment + virtual unsigned + getMaxPermittedBytesForAlignment(MachineBasicBlock *MBB) const; + /// Should loops be aligned even when the function is marked OptSize (but not /// MinSize). - virtual bool alignLoopsWithOptSize() const { - return false; - } + virtual bool alignLoopsWithOptSize() const { return false; } /// If the target has a standard location for the stack protector guard, /// returns the address of that location. Otherwise, returns nullptr. @@ -1836,8 +1838,8 @@ public: virtual Function *getSSPStackGuardCheck(const Module &M) const; /// \returns true if a constant G_UBFX is legal on the target. - virtual bool isConstantUnsignedBitfieldExtactLegal(unsigned Opc, LLT Ty1, - LLT Ty2) const { + virtual bool isConstantUnsignedBitfieldExtractLegal(unsigned Opc, LLT Ty1, + LLT Ty2) const { return false; } @@ -2341,6 +2343,9 @@ protected: /// means the target does not care about loop alignment. The target may also /// override getPrefLoopAlignment to provide per-loop values. void setPrefLoopAlignment(Align Alignment) { PrefLoopAlignment = Alignment; } + void setMaxBytesForAlignment(unsigned MaxBytes) { + MaxBytesForAlignment = MaxBytes; + } /// Set the minimum stack alignment of an argument. void setMinStackArgumentAlignment(Align Alignment) { @@ -2521,6 +2526,8 @@ public: case ISD::SHL: case ISD::SRL: case ISD::SRA: + case ISD::ROTL: + case ISD::ROTR: case ISD::SDIV: case ISD::UDIV: case ISD::SREM: @@ -3030,6 +3037,8 @@ private: /// The preferred loop alignment (in log2 bot in bytes). Align PrefLoopAlignment; + /// The maximum amount of bytes permitted to be emitted for alignment. + unsigned MaxBytesForAlignment; /// Size in bits of the maximum atomics size the backend supports. /// Accesses larger than this will be expanded by AtomicExpandPass. @@ -3283,6 +3292,17 @@ public: return false; } + // Lets target to control the following reassociation of operands: (op (op x, + // c1), y) -> (op (op x, y), c1) where N0 is (op x, c1) and N1 is y. By + // default consider profitable any case where N0 has single use. This + // behavior reflects the condition replaced by this target hook call in the + // DAGCombiner. Any particular target can implement its own heuristic to + // restrict common combiner. + virtual bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, + SDValue N1) const { + return N0.hasOneUse(); + } + virtual bool isSDNodeAlwaysUniform(const SDNode * N) const { return false; } diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h index 8483d078ca74..c3b842052ef5 100644 --- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h +++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h @@ -1094,6 +1094,13 @@ public: inline MCRegister getSubReg(MCRegister Reg, unsigned Idx) const { return static_cast<const MCRegisterInfo *>(this)->getSubReg(Reg, Idx); } + + /// Some targets have non-allocatable registers that aren't technically part + /// of the explicit callee saved register list, but should be handled as such + /// in certain cases. + virtual bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const { + return false; + } }; //===----------------------------------------------------------------------===// |