diff options
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64SchedPredicates.td')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SchedPredicates.td | 80 |
1 files changed, 76 insertions, 4 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SchedPredicates.td b/llvm/lib/Target/AArch64/AArch64SchedPredicates.td index 0ef0f3f8675a..fc13b23b4cf8 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedPredicates.td +++ b/llvm/lib/Target/AArch64/AArch64SchedPredicates.td @@ -41,7 +41,7 @@ let FunctionMapper = "AArch64_AM::getMemExtendType" in { // Check for scaling in the register offset addressing mode. let FunctionMapper = "AArch64_AM::getMemDoShift" in -def CheckMemScaled : CheckImmOperandSimple<3>; +def CheckMemScaled : CheckImmOperandSimple<4>; // Check the shifting type in arithmetic and logic instructions. let FunctionMapper = "AArch64_AM::getShiftType" in { @@ -60,6 +60,76 @@ foreach I = {0-3, 8} in { // Generic predicates. +// Identify whether an instruction is the 16-bit NEON form based on its result. +def CheckHForm : CheckAll<[CheckIsRegOperand<0>, + CheckAny<[CheckRegOperand<0, H0>, + CheckRegOperand<0, H1>, + CheckRegOperand<0, H2>, + CheckRegOperand<0, H3>, + CheckRegOperand<0, H4>, + CheckRegOperand<0, H5>, + CheckRegOperand<0, H6>, + CheckRegOperand<0, H7>, + CheckRegOperand<0, H8>, + CheckRegOperand<0, H9>, + CheckRegOperand<0, H10>, + CheckRegOperand<0, H11>, + CheckRegOperand<0, H12>, + CheckRegOperand<0, H13>, + CheckRegOperand<0, H14>, + CheckRegOperand<0, H15>, + CheckRegOperand<0, H16>, + CheckRegOperand<0, H17>, + CheckRegOperand<0, H18>, + CheckRegOperand<0, H19>, + CheckRegOperand<0, H20>, + CheckRegOperand<0, H21>, + CheckRegOperand<0, H22>, + CheckRegOperand<0, H23>, + CheckRegOperand<0, H24>, + CheckRegOperand<0, H25>, + CheckRegOperand<0, H26>, + CheckRegOperand<0, H27>, + CheckRegOperand<0, H28>, + CheckRegOperand<0, H29>, + CheckRegOperand<0, H30>, + CheckRegOperand<0, H31>]>]>; + +// Identify whether an instruction is the 32-bit NEON form based on its result. +def CheckSForm : CheckAll<[CheckIsRegOperand<0>, + CheckAny<[CheckRegOperand<0, S0>, + CheckRegOperand<0, S1>, + CheckRegOperand<0, S2>, + CheckRegOperand<0, S3>, + CheckRegOperand<0, S4>, + CheckRegOperand<0, S5>, + CheckRegOperand<0, S6>, + CheckRegOperand<0, S7>, + CheckRegOperand<0, S8>, + CheckRegOperand<0, S9>, + CheckRegOperand<0, S10>, + CheckRegOperand<0, S11>, + CheckRegOperand<0, S12>, + CheckRegOperand<0, S13>, + CheckRegOperand<0, S14>, + CheckRegOperand<0, S15>, + CheckRegOperand<0, S16>, + CheckRegOperand<0, S17>, + CheckRegOperand<0, S18>, + CheckRegOperand<0, S19>, + CheckRegOperand<0, S20>, + CheckRegOperand<0, S21>, + CheckRegOperand<0, S22>, + CheckRegOperand<0, S23>, + CheckRegOperand<0, S24>, + CheckRegOperand<0, S25>, + CheckRegOperand<0, S26>, + CheckRegOperand<0, S27>, + CheckRegOperand<0, S28>, + CheckRegOperand<0, S29>, + CheckRegOperand<0, S30>, + CheckRegOperand<0, S31>]>]>; + // Identify whether an instruction is the 64-bit NEON form based on its result. def CheckDForm : CheckAll<[CheckIsRegOperand<0>, CheckAny<[CheckRegOperand<0, D0>, @@ -249,9 +319,10 @@ def IsLoadRegOffsetOp : CheckOpcode<[PRFMroW, PRFMroX, LDRBroW, LDRBroX, LDRHroW, LDRHroX, LDRSroW, LDRSroX, - LDRDroW, LDRDroX]>; + LDRDroW, LDRDroX, + LDRQroW, LDRQroX]>; -// Identify whether an instruction is a load +// Identify whether an instruction is a store // using the register offset addressing mode. def IsStoreRegOffsetOp : CheckOpcode<[STRBBroW, STRBBroX, STRHHroW, STRHHroX, @@ -260,7 +331,8 @@ def IsStoreRegOffsetOp : CheckOpcode<[STRBBroW, STRBBroX, STRBroW, STRBroX, STRHroW, STRHroX, STRSroW, STRSroX, - STRDroW, STRDroX]>; + STRDroW, STRDroX, + STRQroW, STRQroX]>; // Identify whether an instruction is a load or // store using the register offset addressing mode. |