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Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIInstrInfo.h')
-rw-r--r--llvm/lib/Target/AMDGPU/SIInstrInfo.h104
1 files changed, 71 insertions, 33 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 53e2ffba0f65..ce59fe86c688 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -14,22 +14,12 @@
#ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
#define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
-#include "AMDGPUInstrInfo.h"
-#include "SIDefines.h"
+#include "AMDGPUMIRFormatter.h"
#include "SIRegisterInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
-#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SetVector.h"
-#include "llvm/CodeGen/MachineBasicBlock.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
-#include "llvm/MC/MCInstrDesc.h"
-#include "llvm/Support/Compiler.h"
-#include <cassert>
-#include <cstdint>
#define GET_INSTRINFO_HEADER
#include "AMDGPUGenInstrInfo.inc"
@@ -37,17 +27,20 @@
namespace llvm {
class APInt;
+class GCNSubtarget;
+class LiveVariables;
class MachineDominatorTree;
class MachineRegisterInfo;
class RegScavenger;
-class GCNSubtarget;
class TargetRegisterClass;
+class ScheduleHazardRecognizer;
class SIInstrInfo final : public AMDGPUGenInstrInfo {
private:
const SIRegisterInfo RI;
const GCNSubtarget &ST;
TargetSchedModel SchedModel;
+ mutable std::unique_ptr<AMDGPUMIRFormatter> Formatter;
// The inverse predicate should have the negative value.
enum BranchPredicate {
@@ -81,8 +74,9 @@ public:
private:
void swapOperands(MachineInstr &Inst) const;
- bool moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst,
- MachineDominatorTree *MDT = nullptr) const;
+ std::pair<bool, MachineBasicBlock *>
+ moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst,
+ MachineDominatorTree *MDT = nullptr) const;
void lowerSelect(SetVectorType &Worklist, MachineInstr &Inst,
MachineDominatorTree *MDT = nullptr) const;
@@ -201,10 +195,6 @@ public:
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
bool KillSrc) const override;
- unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB, MachineInstr &MI,
- RegScavenger *RS, unsigned TmpReg,
- unsigned Offset, unsigned Size) const;
-
void materializeImmediate(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const DebugLoc &DL,
@@ -248,9 +238,12 @@ public:
// DstRC, then AMDGPU::COPY is returned.
unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
- const MCInstrDesc &getIndirectRegWritePseudo(
- unsigned VecSize, unsigned EltSize, bool IsSGPR) const;
+ const MCInstrDesc &getIndirectRegWriteMovRelPseudo(unsigned VecSize,
+ unsigned EltSize,
+ bool IsSGPR) const;
+ const MCInstrDesc &getIndirectGPRIDXPseudo(unsigned VecSize,
+ bool IsIndirectSrc) const;
LLVM_READONLY
int commuteOpcode(unsigned Opc) const;
@@ -508,12 +501,28 @@ public:
// i.e. global_* or scratch_*.
static bool isSegmentSpecificFLAT(const MachineInstr &MI) {
auto Flags = MI.getDesc().TSFlags;
- return (Flags & SIInstrFlags::FLAT) && !(Flags & SIInstrFlags::LGKM_CNT);
+ return Flags & (SIInstrFlags::IsFlatGlobal | SIInstrFlags::IsFlatScratch);
+ }
+
+ bool isSegmentSpecificFLAT(uint16_t Opcode) const {
+ auto Flags = get(Opcode).TSFlags;
+ return Flags & (SIInstrFlags::IsFlatGlobal | SIInstrFlags::IsFlatScratch);
+ }
+
+ static bool isFLATGlobal(const MachineInstr &MI) {
+ return MI.getDesc().TSFlags & SIInstrFlags::IsFlatGlobal;
+ }
+
+ bool isFLATGlobal(uint16_t Opcode) const {
+ return get(Opcode).TSFlags & SIInstrFlags::IsFlatGlobal;
}
- // FIXME: Make this more precise
static bool isFLATScratch(const MachineInstr &MI) {
- return isSegmentSpecificFLAT(MI);
+ return MI.getDesc().TSFlags & SIInstrFlags::IsFlatScratch;
+ }
+
+ bool isFLATScratch(uint16_t Opcode) const {
+ return get(Opcode).TSFlags & SIInstrFlags::IsFlatScratch;
}
// Any FLAT encoded instruction, including global_* and scratch_*.
@@ -569,6 +578,14 @@ public:
return get(Opcode).TSFlags & SIInstrFlags::DPP;
}
+ static bool isTRANS(const MachineInstr &MI) {
+ return MI.getDesc().TSFlags & SIInstrFlags::TRANS;
+ }
+
+ bool isTRANS(uint16_t Opcode) const {
+ return get(Opcode).TSFlags & SIInstrFlags::TRANS;
+ }
+
static bool isVOP3P(const MachineInstr &MI) {
return MI.getDesc().TSFlags & SIInstrFlags::VOP3P;
}
@@ -677,7 +694,7 @@ public:
bool isVGPRCopy(const MachineInstr &MI) const {
assert(MI.isCopy());
- unsigned Dest = MI.getOperand(0).getReg();
+ Register Dest = MI.getOperand(0).getReg();
const MachineFunction &MF = *MI.getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo();
return !RI.isSGPRReg(MRI, Dest);
@@ -883,6 +900,7 @@ public:
MachineRegisterInfo &MRI) const;
void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const;
+ void legalizeOperandsFLAT(MachineRegisterInfo &MRI, MachineInstr &MI) const;
void legalizeGenericOperand(MachineBasicBlock &InsertMBB,
MachineBasicBlock::iterator I,
@@ -893,20 +911,22 @@ public:
/// Legalize all operands in this instruction. This function may create new
/// instructions and control-flow around \p MI. If present, \p MDT is
/// updated.
- void legalizeOperands(MachineInstr &MI,
- MachineDominatorTree *MDT = nullptr) const;
+ /// \returns A new basic block that contains \p MI if new blocks were created.
+ MachineBasicBlock *
+ legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT = nullptr) const;
/// Replace this instruction's opcode with the equivalent VALU
/// opcode. This function will also move the users of \p MI to the
/// VALU if necessary. If present, \p MDT is updated.
- void moveToVALU(MachineInstr &MI, MachineDominatorTree *MDT = nullptr) const;
-
- void insertWaitStates(MachineBasicBlock &MBB,MachineBasicBlock::iterator MI,
- int Count) const;
+ MachineBasicBlock *moveToVALU(MachineInstr &MI,
+ MachineDominatorTree *MDT = nullptr) const;
void insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const override;
+ void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
+ unsigned Quantity) const override;
+
void insertReturn(MachineBasicBlock &MBB) const;
/// Return the number of wait states that result from executing this
/// instruction.
@@ -1015,14 +1035,18 @@ public:
return isUInt<12>(Imm);
}
- unsigned getNumFlatOffsetBits(unsigned AddrSpace, bool Signed) const;
-
/// Returns if \p Offset is legal for the subtarget as the offset to a FLAT
/// encoded instruction. If \p Signed, this is for an instruction that
/// interprets the offset as signed.
bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace,
bool Signed) const;
+ /// Split \p COffsetVal into {immediate offset field, remainder offset}
+ /// values.
+ std::pair<int64_t, int64_t> splitFlatOffset(int64_t COffsetVal,
+ unsigned AddrSpace,
+ bool IsSigned) const;
+
/// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
/// Return -1 if the target-specific opcode for the pseudo instruction does
/// not exist. If Opcode is not a pseudo instruction, this is identity.
@@ -1053,6 +1077,14 @@ public:
unsigned getInstrLatency(const InstrItineraryData *ItinData,
const MachineInstr &MI,
unsigned *PredCost = nullptr) const override;
+
+ const MIRFormatter *getMIRFormatter() const override {
+ if (!Formatter.get())
+ Formatter = std::make_unique<AMDGPUMIRFormatter>();
+ return Formatter.get();
+ }
+
+ static unsigned getDSShaderTypeValue(const MachineFunction &MF);
};
/// \brief Returns true if a reg:subreg pair P has a TRC class
@@ -1148,6 +1180,12 @@ namespace AMDGPU {
LLVM_READONLY
int getVCMPXNoSDstOp(uint16_t Opcode);
+ LLVM_READONLY
+ int getFlatScratchInstSTfromSS(uint16_t Opcode);
+
+ LLVM_READONLY
+ int getFlatScratchInstSSfromSV(uint16_t Opcode);
+
const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19);
const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21);
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-27 00:46:50 +0000