diff options
Diffstat (limited to 'llvm/lib/Target/BPF')
37 files changed, 463 insertions, 305 deletions
diff --git a/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp b/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp index 9672ed009e9b..119684b8bbed 100644 --- a/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp +++ b/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp @@ -8,7 +8,6 @@ #include "MCTargetDesc/BPFMCTargetDesc.h" #include "TargetInfo/BPFTargetInfo.h" -#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringSwitch.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" @@ -17,7 +16,6 @@ #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" #include "llvm/MC/MCParser/MCTargetAsmParser.h" -#include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/TargetRegistry.h" @@ -34,7 +32,7 @@ class BPFAsmParser : public MCTargetAsmParser { bool PreMatchCheck(OperandVector &Operands); - bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, + bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) override; @@ -43,7 +41,7 @@ class BPFAsmParser : public MCTargetAsmParser { ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override; - bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, + bool parseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) override; // "=" is used as assignment operator for assembly statment, so can't be used @@ -86,7 +84,7 @@ struct BPFOperand : public MCParsedAsmOperand { } Kind; struct RegOp { - unsigned RegNum; + MCRegister RegNum; }; struct ImmOp { @@ -206,10 +204,10 @@ public: return Op; } - static std::unique_ptr<BPFOperand> createReg(unsigned RegNo, SMLoc S, + static std::unique_ptr<BPFOperand> createReg(MCRegister Reg, SMLoc S, SMLoc E) { auto Op = std::make_unique<BPFOperand>(Register); - Op->Reg.RegNum = RegNo; + Op->Reg.RegNum = Reg; Op->StartLoc = S; Op->EndLoc = E; return Op; @@ -304,7 +302,7 @@ bool BPFAsmParser::PreMatchCheck(OperandVector &Operands) { return false; } -bool BPFAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, +bool BPFAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) { @@ -447,13 +445,13 @@ ParseStatus BPFAsmParser::parseRegister(OperandVector &Operands) { return ParseStatus::NoMatch; case AsmToken::Identifier: StringRef Name = getLexer().getTok().getIdentifier(); - unsigned RegNo = MatchRegisterName(Name); + MCRegister Reg = MatchRegisterName(Name); - if (RegNo == 0) + if (!Reg) return ParseStatus::NoMatch; getLexer().Lex(); - Operands.push_back(BPFOperand::createReg(RegNo, S, E)); + Operands.push_back(BPFOperand::createReg(Reg, S, E)); } return ParseStatus::Success; } @@ -483,17 +481,16 @@ ParseStatus BPFAsmParser::parseImmediate(OperandVector &Operands) { return ParseStatus::Success; } -/// ParseInstruction - Parse an BPF instruction which is in BPF verifier -/// format. -bool BPFAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, +/// Parse an BPF instruction which is in BPF verifier format. +bool BPFAsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) { // The first operand could be either register or actually an operator. - unsigned RegNo = MatchRegisterName(Name); + MCRegister Reg = MatchRegisterName(Name); - if (RegNo != 0) { + if (Reg) { SMLoc E = SMLoc::getFromPointer(NameLoc.getPointer() - 1); - Operands.push_back(BPFOperand::createReg(RegNo, NameLoc, E)); - } else if (BPFOperand::isValidIdAtStart (Name)) + Operands.push_back(BPFOperand::createReg(Reg, NameLoc, E)); + } else if (BPFOperand::isValidIdAtStart(Name)) Operands.push_back(BPFOperand::createToken(Name, NameLoc)); else return Error(NameLoc, "invalid register/token name"); diff --git a/llvm/lib/Target/BPF/BPF.h b/llvm/lib/Target/BPF/BPF.h index 694d7bacf642..f07ae4c9baf1 100644 --- a/llvm/lib/Target/BPF/BPF.h +++ b/llvm/lib/Target/BPF/BPF.h @@ -37,7 +37,7 @@ InstructionSelector *createBPFInstructionSelector(const BPFTargetMachine &, void initializeBPFCheckAndAdjustIRPass(PassRegistry&); void initializeBPFDAGToDAGISelLegacyPass(PassRegistry &); void initializeBPFMIPeepholePass(PassRegistry &); -void initializeBPFMIPreEmitCheckingPass(PassRegistry&); +void initializeBPFMIPreEmitCheckingPass(PassRegistry &); void initializeBPFMIPreEmitPeepholePass(PassRegistry &); void initializeBPFMISimplifyPatchablePass(PassRegistry &); diff --git a/llvm/lib/Target/BPF/BPFASpaceCastSimplifyPass.cpp b/llvm/lib/Target/BPF/BPFASpaceCastSimplifyPass.cpp index f87b299bbba6..d70b87d76d6f 100644 --- a/llvm/lib/Target/BPF/BPFASpaceCastSimplifyPass.cpp +++ b/llvm/lib/Target/BPF/BPFASpaceCastSimplifyPass.cpp @@ -54,7 +54,7 @@ struct CastGEPCast { unsigned AS = OuterCast->getDestAddressSpace(); auto *NewGEP = cast<GetElementPtrInst>(GEP->clone()); NewGEP->setName(GEP->getName()); - NewGEP->insertAfter(OuterCast); + NewGEP->insertAfter(OuterCast->getIterator()); NewGEP->setOperand(0, InnerCast->getPointerOperand()); auto *GEPTy = cast<PointerType>(GEP->getType()); NewGEP->mutateType(changeAddressSpace(GEPTy, AS)); diff --git a/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp b/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp index 4be6220b358b..646d57770164 100644 --- a/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp +++ b/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp @@ -103,13 +103,13 @@ uint32_t BPFCoreSharedInfo::SeqNum; Instruction *BPFCoreSharedInfo::insertPassThrough(Module *M, BasicBlock *BB, Instruction *Input, Instruction *Before) { - Function *Fn = Intrinsic::getDeclaration( + Function *Fn = Intrinsic::getOrInsertDeclaration( M, Intrinsic::bpf_passthrough, {Input->getType(), Input->getType()}); Constant *SeqNumVal = ConstantInt::get(Type::getInt32Ty(BB->getContext()), BPFCoreSharedInfo::SeqNum++); auto *NewInst = CallInst::Create(Fn, {SeqNumVal, Input}); - NewInst->insertBefore(Before); + NewInst->insertBefore(Before->getIterator()); return NewInst; } } // namespace llvm @@ -221,10 +221,9 @@ bool BPFAbstractMemberAccess::run(Function &F) { void BPFAbstractMemberAccess::ResetMetadata(struct CallInfo &CInfo) { if (auto Ty = dyn_cast<DICompositeType>(CInfo.Metadata)) { - if (AnonRecords.find(Ty) != AnonRecords.end()) { - if (AnonRecords[Ty] != nullptr) - CInfo.Metadata = AnonRecords[Ty]; - } + auto It = AnonRecords.find(Ty); + if (It != AnonRecords.end() && It->second != nullptr) + CInfo.Metadata = It->second; } } @@ -234,18 +233,12 @@ void BPFAbstractMemberAccess::CheckCompositeType(DIDerivedType *ParentTy, ParentTy->getTag() != dwarf::DW_TAG_typedef) return; - if (AnonRecords.find(CTy) == AnonRecords.end()) { - AnonRecords[CTy] = ParentTy; - return; - } - + auto [It, Inserted] = AnonRecords.try_emplace(CTy, ParentTy); // Two or more typedef's may point to the same anon record. // If this is the case, set the typedef DIType to be nullptr // to indicate the duplication case. - DIDerivedType *CurrTy = AnonRecords[CTy]; - if (CurrTy == ParentTy) - return; - AnonRecords[CTy] = nullptr; + if (!Inserted && It->second != ParentTy) + It->second = nullptr; } void BPFAbstractMemberAccess::CheckDerivedType(DIDerivedType *ParentTy, @@ -310,7 +303,7 @@ static uint32_t calcArraySize(const DICompositeType *CTy, uint32_t StartDim) { if (auto *Element = dyn_cast_or_null<DINode>(Elements[I])) if (Element->getTag() == dwarf::DW_TAG_subrange_type) { const DISubrange *SR = cast<DISubrange>(Element); - auto *CI = SR->getCount().dyn_cast<ConstantInt *>(); + auto *CI = dyn_cast<ConstantInt *>(SR->getCount()); DimSize *= CI->getSExtValue(); } } @@ -1122,16 +1115,16 @@ bool BPFAbstractMemberAccess::transformGEPChain(CallInst *Call, // Generate a BitCast auto *BCInst = new BitCastInst(Base, PointerType::getUnqual(BB->getContext())); - BCInst->insertBefore(Call); + BCInst->insertBefore(Call->getIterator()); // Generate a GetElementPtr auto *GEP = GetElementPtrInst::Create(Type::getInt8Ty(BB->getContext()), BCInst, LDInst); - GEP->insertBefore(Call); + GEP->insertBefore(Call->getIterator()); // Generate a BitCast auto *BCInst2 = new BitCastInst(GEP, Call->getType()); - BCInst2->insertBefore(Call); + BCInst2->insertBefore(Call->getIterator()); // For the following code, // Block0: diff --git a/llvm/lib/Target/BPF/BPFAdjustOpt.cpp b/llvm/lib/Target/BPF/BPFAdjustOpt.cpp index 4ab0cbcc9247..afc47968bf65 100644 --- a/llvm/lib/Target/BPF/BPFAdjustOpt.cpp +++ b/llvm/lib/Target/BPF/BPFAdjustOpt.cpp @@ -12,7 +12,6 @@ #include "BPF.h" #include "BPFCORE.h" -#include "BPFTargetMachine.h" #include "llvm/IR/Instruction.h" #include "llvm/IR/Instructions.h" #include "llvm/IR/IntrinsicsBPF.h" @@ -126,10 +125,10 @@ bool BPFAdjustOptImpl::adjustICmpToBuiltin() { Constant *Opcode = ConstantInt::get(Type::getInt32Ty(BB.getContext()), Op); - Function *Fn = Intrinsic::getDeclaration( + Function *Fn = Intrinsic::getOrInsertDeclaration( M, Intrinsic::bpf_compare, {Op0->getType(), ConstOp1->getType()}); auto *NewInst = CallInst::Create(Fn, {Opcode, Op0, ConstOp1}); - NewInst->insertBefore(&I); + NewInst->insertBefore(I.getIterator()); Icmp->replaceAllUsesWith(NewInst); Changed = true; ToBeDeleted = Icmp; @@ -223,7 +222,7 @@ bool BPFAdjustOptImpl::serializeICMPCrossBB(BasicBlock &BB) { if (!BI || !BI->isConditional()) return false; auto *Cond = dyn_cast<ICmpInst>(BI->getCondition()); - if (!Cond || B2->getFirstNonPHI() != Cond) + if (!Cond || &*B2->getFirstNonPHIIt() != Cond) return false; Value *B2Op0 = Cond->getOperand(0); auto Cond2Op = Cond->getPredicate(); diff --git a/llvm/lib/Target/BPF/BPFAsmPrinter.cpp b/llvm/lib/Target/BPF/BPFAsmPrinter.cpp index a9ac4f651ea2..b3c27a3d1d6f 100644 --- a/llvm/lib/Target/BPF/BPFAsmPrinter.cpp +++ b/llvm/lib/Target/BPF/BPFAsmPrinter.cpp @@ -14,13 +14,11 @@ #include "BPF.h" #include "BPFInstrInfo.h" #include "BPFMCInstLower.h" -#include "BPFTargetMachine.h" #include "BTFDebug.h" #include "MCTargetDesc/BPFInstPrinter.h" #include "TargetInfo/BPFTargetInfo.h" #include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/MachineConstantPool.h" -#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/IR/Module.h" @@ -62,7 +60,7 @@ bool BPFAsmPrinter::doInitialization(Module &M) { // Only emit BTF when debuginfo available. if (MAI->doesSupportDebugInformation() && !M.debug_compile_units().empty()) { BTF = new BTFDebug(this); - DebugHandlers.push_back(std::unique_ptr<BTFDebug>(BTF)); + Handlers.push_back(std::unique_ptr<BTFDebug>(BTF)); } return false; diff --git a/llvm/lib/Target/BPF/BPFCallingConv.td b/llvm/lib/Target/BPF/BPFCallingConv.td index ef4ef1930aa8..a557211437e9 100644 --- a/llvm/lib/Target/BPF/BPFCallingConv.td +++ b/llvm/lib/Target/BPF/BPFCallingConv.td @@ -46,3 +46,4 @@ def CC_BPF32 : CallingConv<[ ]>; def CSR : CalleeSavedRegs<(add R6, R7, R8, R9, R10)>; +def CSR_PreserveAll : CalleeSavedRegs<(add R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10)>; diff --git a/llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp b/llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp index 2b78ed7134c9..b202b20291af 100644 --- a/llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp +++ b/llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp @@ -21,9 +21,7 @@ #include "BPF.h" #include "BPFCORE.h" -#include "BPFTargetMachine.h" #include "llvm/Analysis/LoopInfo.h" -#include "llvm/IR/DebugInfoMetadata.h" #include "llvm/IR/GlobalVariable.h" #include "llvm/IR/IRBuilder.h" #include "llvm/IR/Instruction.h" @@ -31,7 +29,6 @@ #include "llvm/IR/IntrinsicsBPF.h" #include "llvm/IR/Module.h" #include "llvm/IR/Type.h" -#include "llvm/IR/User.h" #include "llvm/IR/Value.h" #include "llvm/Pass.h" #include "llvm/Transforms/Utils/BasicBlockUtils.h" @@ -164,7 +161,7 @@ bool BPFCheckAndAdjustIR::removeCompareBuiltin(Module &M) { CmpInst::Predicate Opcode = (CmpInst::Predicate)OpVal; auto *ICmp = new ICmpInst(Opcode, Arg1, Arg2); - ICmp->insertBefore(Call); + ICmp->insertBefore(Call->getIterator()); Call->replaceAllUsesWith(ICmp); ToBeDeleted = Call; @@ -370,16 +367,16 @@ void BPFCheckAndAdjustIR::getAnalysisUsage(AnalysisUsage &AU) const { static void unrollGEPLoad(CallInst *Call) { auto [GEP, Load] = BPFPreserveStaticOffsetPass::reconstructLoad(Call); - GEP->insertBefore(Call); - Load->insertBefore(Call); + GEP->insertBefore(Call->getIterator()); + Load->insertBefore(Call->getIterator()); Call->replaceAllUsesWith(Load); Call->eraseFromParent(); } static void unrollGEPStore(CallInst *Call) { auto [GEP, Store] = BPFPreserveStaticOffsetPass::reconstructStore(Call); - GEP->insertBefore(Call); - Store->insertBefore(Call); + GEP->insertBefore(Call->getIterator()); + Store->insertBefore(Call->getIterator()); Call->eraseFromParent(); } @@ -439,8 +436,8 @@ static Value *aspaceWrapValue(DenseMap<Value *, Value *> &Cache, Function *F, Value *WrappedPtr = aspaceWrapValue(Cache, F, Ptr); auto *GEPTy = cast<PointerType>(GEP->getType()); auto *NewGEP = GEP->clone(); - NewGEP->insertAfter(GEP); - NewGEP->mutateType(GEPTy->getPointerTo(0)); + NewGEP->insertAfter(GEP->getIterator()); + NewGEP->mutateType(PointerType::getUnqual(GEPTy->getContext())); NewGEP->setOperand(GEP->getPointerOperandIndex(), WrappedPtr); NewGEP->setName(GEP->getName()); Cache[ToWrap] = NewGEP; @@ -452,8 +449,7 @@ static Value *aspaceWrapValue(DenseMap<Value *, Value *> &Cache, Function *F, IB.SetInsertPoint(*InsnPtr->getInsertionPointAfterDef()); else IB.SetInsertPoint(F->getEntryBlock().getFirstInsertionPt()); - auto *PtrTy = cast<PointerType>(ToWrap->getType()); - auto *ASZeroPtrTy = PtrTy->getPointerTo(0); + auto *ASZeroPtrTy = IB.getPtrTy(0); auto *ACast = IB.CreateAddrSpaceCast(ToWrap, ASZeroPtrTy, ToWrap->getName()); Cache[ToWrap] = ACast; return ACast; diff --git a/llvm/lib/Target/BPF/BPFFrameLowering.cpp b/llvm/lib/Target/BPF/BPFFrameLowering.cpp index 8812cfdd86da..00780b4d1406 100644 --- a/llvm/lib/Target/BPF/BPFFrameLowering.cpp +++ b/llvm/lib/Target/BPF/BPFFrameLowering.cpp @@ -11,16 +11,15 @@ //===----------------------------------------------------------------------===// #include "BPFFrameLowering.h" -#include "BPFInstrInfo.h" #include "BPFSubtarget.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" using namespace llvm; -bool BPFFrameLowering::hasFP(const MachineFunction &MF) const { return true; } +bool BPFFrameLowering::hasFPImpl(const MachineFunction &MF) const { + return true; +} void BPFFrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const {} diff --git a/llvm/lib/Target/BPF/BPFFrameLowering.h b/llvm/lib/Target/BPF/BPFFrameLowering.h index a546351ec6cb..6beffcbe69dd 100644 --- a/llvm/lib/Target/BPF/BPFFrameLowering.h +++ b/llvm/lib/Target/BPF/BPFFrameLowering.h @@ -26,7 +26,6 @@ public: void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override; - bool hasFP(const MachineFunction &MF) const override; void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override; @@ -35,6 +34,9 @@ public: MachineBasicBlock::iterator MI) const override { return MBB.erase(MI); } + +protected: + bool hasFPImpl(const MachineFunction &MF) const override; }; } #endif diff --git a/llvm/lib/Target/BPF/BPFIRPeephole.cpp b/llvm/lib/Target/BPF/BPFIRPeephole.cpp index a257f582f2a1..d82275c08d37 100644 --- a/llvm/lib/Target/BPF/BPFIRPeephole.cpp +++ b/llvm/lib/Target/BPF/BPFIRPeephole.cpp @@ -15,10 +15,8 @@ #include "llvm/IR/Instruction.h" #include "llvm/IR/Instructions.h" #include "llvm/IR/IntrinsicInst.h" -#include "llvm/IR/Module.h" #include "llvm/IR/PassManager.h" #include "llvm/IR/Type.h" -#include "llvm/IR/User.h" #include "llvm/IR/Value.h" #include "llvm/Pass.h" diff --git a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp index 67f98bd7c05b..352017e9b929 100644 --- a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp +++ b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp @@ -12,15 +12,12 @@ //===----------------------------------------------------------------------===// #include "BPF.h" -#include "BPFRegisterInfo.h" #include "BPFSubtarget.h" #include "BPFTargetMachine.h" #include "llvm/CodeGen/FunctionLoweringInfo.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/IR/Constants.h" #include "llvm/IR/IntrinsicInst.h" @@ -29,7 +26,6 @@ #include "llvm/Support/Endian.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/Target/TargetMachine.h" using namespace llvm; diff --git a/llvm/lib/Target/BPF/BPFISelLowering.cpp b/llvm/lib/Target/BPF/BPFISelLowering.cpp index 071fe004806e..1f5cadf37ab5 100644 --- a/llvm/lib/Target/BPF/BPFISelLowering.cpp +++ b/llvm/lib/Target/BPF/BPFISelLowering.cpp @@ -14,7 +14,6 @@ #include "BPFISelLowering.h" #include "BPF.h" #include "BPFSubtarget.h" -#include "BPFTargetMachine.h" #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" @@ -402,6 +401,21 @@ SDValue BPFTargetLowering::LowerFormalArguments( const size_t BPFTargetLowering::MaxArgs = 5; +static void resetRegMaskBit(const TargetRegisterInfo *TRI, uint32_t *RegMask, + MCRegister Reg) { + for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) + RegMask[SubReg / 32] &= ~(1u << (SubReg % 32)); +} + +static uint32_t *regMaskFromTemplate(const TargetRegisterInfo *TRI, + MachineFunction &MF, + const uint32_t *BaseRegMask) { + uint32_t *RegMask = MF.allocateRegMask(); + unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs()); + memcpy(RegMask, BaseRegMask, sizeof(RegMask[0]) * RegMaskSize); + return RegMask; +} + SDValue BPFTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const { SelectionDAG &DAG = CLI.DAG; @@ -513,6 +527,22 @@ SDValue BPFTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, for (auto &Reg : RegsToPass) Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType())); + bool HasFastCall = + (CLI.CB && isa<CallInst>(CLI.CB) && CLI.CB->hasFnAttr("bpf_fastcall")); + const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); + if (HasFastCall) { + uint32_t *RegMask = regMaskFromTemplate( + TRI, MF, TRI->getCallPreservedMask(MF, CallingConv::PreserveAll)); + for (auto const &RegPair : RegsToPass) + resetRegMaskBit(TRI, RegMask, RegPair.first); + if (!CLI.CB->getType()->isVoidTy()) + resetRegMaskBit(TRI, RegMask, BPF::R0); + Ops.push_back(DAG.getRegisterMask(RegMask)); + } else { + Ops.push_back( + DAG.getRegisterMask(TRI->getCallPreservedMask(MF, CLI.CallConv))); + } + if (InGlue.getNode()) Ops.push_back(InGlue); @@ -666,10 +696,9 @@ SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { NegateCC(LHS, RHS, CC); SDValue TargetCC = DAG.getConstant(CC, DL, LHS.getValueType()); - SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV}; - return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops); + return DAG.getNode(BPFISD::SELECT_CC, DL, Op.getValueType(), Ops); } const char *BPFTargetLowering::getTargetNodeName(unsigned Opcode) const { diff --git a/llvm/lib/Target/BPF/BPFISelLowering.h b/llvm/lib/Target/BPF/BPFISelLowering.h index 42707949e864..d59098f9f569 100644 --- a/llvm/lib/Target/BPF/BPFISelLowering.h +++ b/llvm/lib/Target/BPF/BPFISelLowering.h @@ -118,7 +118,9 @@ private: return Op.size() >= 8 ? MVT::i64 : MVT::i32; } - bool isIntDivCheap(EVT VT, AttributeList Attr) const override { return true; } + bool isIntDivCheap(EVT VT, AttributeList Attr) const override { + return false; + } bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override { diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.cpp b/llvm/lib/Target/BPF/BPFInstrInfo.cpp index 2209f1f1462b..c79fb99ba5cf 100644 --- a/llvm/lib/Target/BPF/BPFInstrInfo.cpp +++ b/llvm/lib/Target/BPF/BPFInstrInfo.cpp @@ -31,7 +31,8 @@ BPFInstrInfo::BPFInstrInfo() void BPFInstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, - MCRegister SrcReg, bool KillSrc) const { + MCRegister SrcReg, bool KillSrc, + bool RenamableDest, bool RenamableSrc) const { if (BPF::GPRRegClass.contains(DestReg, SrcReg)) BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg) .addReg(SrcReg, getKillRegState(KillSrc)); @@ -126,7 +127,8 @@ void BPFInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, Register SrcReg, bool IsKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, - Register VReg) const { + Register VReg, + MachineInstr::MIFlag Flags) const { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); @@ -145,12 +147,10 @@ void BPFInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, llvm_unreachable("Can't store this register to stack slot"); } -void BPFInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - Register DestReg, int FI, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const { +void BPFInstrInfo::loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, + int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, + Register VReg, MachineInstr::MIFlag Flags) const { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.h b/llvm/lib/Target/BPF/BPFInstrInfo.h index 354aca1bd2f9..904d94d47e47 100644 --- a/llvm/lib/Target/BPF/BPFInstrInfo.h +++ b/llvm/lib/Target/BPF/BPFInstrInfo.h @@ -31,22 +31,22 @@ public: void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, - bool KillSrc) const override; + bool KillSrc, bool RenamableDest = false, + bool RenamableSrc = false) const override; bool expandPostRAPseudo(MachineInstr &MI) const override; - void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register SrcReg, - bool isKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; + void storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; - void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register DestReg, - int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; + void loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + Register DestReg, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.td b/llvm/lib/Target/BPF/BPFInstrInfo.td index 55989f5eb6a3..86929a952d1b 100644 --- a/llvm/lib/Target/BPF/BPFInstrInfo.td +++ b/llvm/lib/Target/BPF/BPFInstrInfo.td @@ -44,7 +44,7 @@ def BPFcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_BPFCallSeqEnd, def BPFbrcc : SDNode<"BPFISD::BR_CC", SDT_BPFBrCC, [SDNPHasChain, SDNPOutGlue, SDNPInGlue]>; -def BPFselectcc : SDNode<"BPFISD::SELECT_CC", SDT_BPFSelectCC, [SDNPInGlue]>; +def BPFselectcc : SDNode<"BPFISD::SELECT_CC", SDT_BPFSelectCC>; def BPFWrapper : SDNode<"BPFISD::Wrapper", SDT_BPFWrapper>; def BPFmemcpy : SDNode<"BPFISD::MEMCPY", SDT_BPFMEMCPY, [SDNPHasChain, SDNPInGlue, SDNPOutGlue, @@ -677,9 +677,7 @@ let isBranch = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1 in { } // Jump and link -let isCall=1, hasDelaySlot=0, Uses = [R11], - // Potentially clobbered registers - Defs = [R0, R1, R2, R3, R4, R5] in { +let isCall=1, hasDelaySlot=0, Uses = [R11] in { def JAL : CALL<"call">; def JALX : CALLX<"callx">; } @@ -788,51 +786,13 @@ let Predicates = [BPFNoALU32] in { def : Pat<(i64 (extloadi32 ADDRri:$src)), (i64 (LDW ADDRri:$src))>; } -// Atomic XADD for BPFNoALU32 -class XADD<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode> - : TYPE_LD_ST<BPF_ATOMIC.Value, SizeOp.Value, - (outs GPR:$dst), - (ins MEMri:$addr, GPR:$val), - "lock *("#OpcodeStr#" *)($addr) += $val", - [(set GPR:$dst, (OpNode ADDRri:$addr, GPR:$val))]> { - bits<4> dst; - bits<20> addr; - - let Inst{51-48} = addr{19-16}; // base reg - let Inst{55-52} = dst; - let Inst{47-32} = addr{15-0}; // offset - let Inst{7-4} = BPF_ADD.Value; - let BPFClass = BPF_STX; -} - -let Constraints = "$dst = $val" in { - let Predicates = [BPFNoALU32] in { - def XADDW : XADD<BPF_W, "u32", atomic_load_add_i32>; - } -} - // Atomic add, and, or, xor -class ATOMIC_NOFETCH<BPFArithOp Opc, string Opstr> - : TYPE_LD_ST<BPF_ATOMIC.Value, BPF_DW.Value, - (outs GPR:$dst), - (ins MEMri:$addr, GPR:$val), - "lock *(u64 *)($addr) " #Opstr# "= $val", - []> { - bits<4> dst; - bits<20> addr; - - let Inst{51-48} = addr{19-16}; // base reg - let Inst{55-52} = dst; - let Inst{47-32} = addr{15-0}; // offset - let Inst{7-4} = Opc.Value; - let BPFClass = BPF_STX; -} - -class ATOMIC32_NOFETCH<BPFArithOp Opc, string Opstr> - : TYPE_LD_ST<BPF_ATOMIC.Value, BPF_W.Value, - (outs GPR32:$dst), - (ins MEMri:$addr, GPR32:$val), - "lock *(u32 *)($addr) " #Opstr# "= $val", +class ATOMIC_NOFETCH<BPFWidthModifer SizeOp, string OpType, RegisterClass RegTp, + BPFArithOp Opc, string Opstr> + : TYPE_LD_ST<BPF_ATOMIC.Value, SizeOp.Value, + (outs RegTp:$dst), + (ins MEMri:$addr, RegTp:$val), + "lock *(" #OpType# " *)($addr) " #Opstr# "= $val", []> { bits<4> dst; bits<20> addr; @@ -846,26 +806,32 @@ class ATOMIC32_NOFETCH<BPFArithOp Opc, string Opstr> let Constraints = "$dst = $val" in { let Predicates = [BPFHasALU32], DecoderNamespace = "BPFALU32" in { - def XADDW32 : ATOMIC32_NOFETCH<BPF_ADD, "+">; - def XANDW32 : ATOMIC32_NOFETCH<BPF_AND, "&">; - def XORW32 : ATOMIC32_NOFETCH<BPF_OR, "|">; - def XXORW32 : ATOMIC32_NOFETCH<BPF_XOR, "^">; + def XADDW32 : ATOMIC_NOFETCH<BPF_W, "u32", GPR32, BPF_ADD, "+">; + def XANDW32 : ATOMIC_NOFETCH<BPF_W, "u32", GPR32, BPF_AND, "&">; + def XORW32 : ATOMIC_NOFETCH<BPF_W, "u32", GPR32, BPF_OR, "|">; + def XXORW32 : ATOMIC_NOFETCH<BPF_W, "u32", GPR32, BPF_XOR, "^">; } + def XADDW : ATOMIC_NOFETCH<BPF_W, "u32", GPR, BPF_ADD, "+">; + def XADDD : ATOMIC_NOFETCH<BPF_DW, "u64", GPR, BPF_ADD, "+">; + def XANDD : ATOMIC_NOFETCH<BPF_DW, "u64", GPR, BPF_AND, "&">; + def XORD : ATOMIC_NOFETCH<BPF_DW, "u64", GPR, BPF_OR, "|">; + def XXORD : ATOMIC_NOFETCH<BPF_DW, "u64", GPR, BPF_XOR, "^">; +} - def XADDD : ATOMIC_NOFETCH<BPF_ADD, "+">; - def XANDD : ATOMIC_NOFETCH<BPF_AND, "&">; - def XORD : ATOMIC_NOFETCH<BPF_OR, "|">; - def XXORD : ATOMIC_NOFETCH<BPF_XOR, "^">; +let Predicates = [BPFNoALU32] in { + def : Pat<(atomic_load_add_i32 ADDRri:$addr, GPR:$val), + (XADDW ADDRri:$addr, GPR:$val)>; + def : Pat<(atomic_load_add_i64 ADDRri:$addr, GPR:$val), + (XADDD ADDRri:$addr, GPR:$val)>; } // Atomic Fetch-and-<add, and, or, xor> operations -class XFALU64<BPFWidthModifer SizeOp, BPFArithOp Opc, string OpcodeStr, - string OpcStr, PatFrag OpNode> +class XFALU64<BPFWidthModifer SizeOp, BPFArithOp Opc, string OpcodeStr, string OpcStr> : TYPE_LD_ST<BPF_ATOMIC.Value, SizeOp.Value, (outs GPR:$dst), (ins MEMri:$addr, GPR:$val), "$dst = atomic_fetch_"#OpcStr#"(("#OpcodeStr#" *)($addr), $val)", - [(set GPR:$dst, (OpNode ADDRri:$addr, GPR:$val))]> { + []> { bits<4> dst; bits<20> addr; @@ -877,13 +843,12 @@ class XFALU64<BPFWidthModifer SizeOp, BPFArithOp Opc, string OpcodeStr, let BPFClass = BPF_STX; } -class XFALU32<BPFWidthModifer SizeOp, BPFArithOp Opc, string OpcodeStr, - string OpcStr, PatFrag OpNode> +class XFALU32<BPFWidthModifer SizeOp, BPFArithOp Opc, string OpcodeStr, string OpcStr> : TYPE_LD_ST<BPF_ATOMIC.Value, SizeOp.Value, (outs GPR32:$dst), (ins MEMri:$addr, GPR32:$val), "$dst = atomic_fetch_"#OpcStr#"(("#OpcodeStr#" *)($addr), $val)", - [(set GPR32:$dst, (OpNode ADDRri:$addr, GPR32:$val))]> { + []> { bits<4> dst; bits<20> addr; @@ -897,24 +862,122 @@ class XFALU32<BPFWidthModifer SizeOp, BPFArithOp Opc, string OpcodeStr, let Constraints = "$dst = $val" in { let Predicates = [BPFHasALU32], DecoderNamespace = "BPFALU32" in { - def XFADDW32 : XFALU32<BPF_W, BPF_ADD, "u32", "add", atomic_load_add_i32>; - def XFANDW32 : XFALU32<BPF_W, BPF_AND, "u32", "and", atomic_load_and_i32>; - def XFORW32 : XFALU32<BPF_W, BPF_OR, "u32", "or", atomic_load_or_i32>; - def XFXORW32 : XFALU32<BPF_W, BPF_XOR, "u32", "xor", atomic_load_xor_i32>; + def XFADDW32 : XFALU32<BPF_W, BPF_ADD, "u32", "add">; + def XFANDW32 : XFALU32<BPF_W, BPF_AND, "u32", "and">; + def XFORW32 : XFALU32<BPF_W, BPF_OR, "u32", "or">; + def XFXORW32 : XFALU32<BPF_W, BPF_XOR, "u32", "xor">; } - def XFADDD : XFALU64<BPF_DW, BPF_ADD, "u64", "add", atomic_load_add_i64>; - def XFANDD : XFALU64<BPF_DW, BPF_AND, "u64", "and", atomic_load_and_i64>; - def XFORD : XFALU64<BPF_DW, BPF_OR, "u64", "or", atomic_load_or_i64>; - def XFXORD : XFALU64<BPF_DW, BPF_XOR, "u64", "xor", atomic_load_xor_i64>; + let Predicates = [BPFHasALU32] in { + def XFADDD : XFALU64<BPF_DW, BPF_ADD, "u64", "add">; + } + def XFANDD : XFALU64<BPF_DW, BPF_AND, "u64", "and">; + def XFORD : XFALU64<BPF_DW, BPF_OR, "u64", "or">; + def XFXORD : XFALU64<BPF_DW, BPF_XOR, "u64", "xor">; } -// atomic_load_sub can be represented as a neg followed -// by an atomic_load_add. -def : Pat<(atomic_load_sub_i32 ADDRri:$addr, GPR32:$val), - (XFADDW32 ADDRri:$addr, (NEG_32 GPR32:$val))>; -def : Pat<(atomic_load_sub_i64 ADDRri:$addr, GPR:$val), - (XFADDD ADDRri:$addr, (NEG_64 GPR:$val))>; +let Predicates = [BPFHasALU32] in { + foreach P = [// add + [atomic_load_add_i32_monotonic, XADDW32], + [atomic_load_add_i32_acquire, XFADDW32], + [atomic_load_add_i32_release, XFADDW32], + [atomic_load_add_i32_acq_rel, XFADDW32], + [atomic_load_add_i32_seq_cst, XFADDW32], + // and + [atomic_load_and_i32_monotonic, XANDW32], + [atomic_load_and_i32_acquire, XFANDW32], + [atomic_load_and_i32_release, XFANDW32], + [atomic_load_and_i32_acq_rel, XFANDW32], + [atomic_load_and_i32_seq_cst, XFANDW32], + // or + [atomic_load_or_i32_monotonic, XORW32], + [atomic_load_or_i32_acquire, XFORW32], + [atomic_load_or_i32_release, XFORW32], + [atomic_load_or_i32_acq_rel, XFORW32], + [atomic_load_or_i32_seq_cst, XFORW32], + // xor + [atomic_load_xor_i32_monotonic, XXORW32], + [atomic_load_xor_i32_acquire, XFXORW32], + [atomic_load_xor_i32_release, XFXORW32], + [atomic_load_xor_i32_acq_rel, XFXORW32], + [atomic_load_xor_i32_seq_cst, XFXORW32], + ] in { + def : Pat<(P[0] ADDRri:$addr, GPR32:$val), (P[1] ADDRri:$addr, GPR32:$val)>; + } + + // atomic_load_sub can be represented as a neg followed + // by an atomic_load_add. + foreach P = [[atomic_load_sub_i32_monotonic, XADDW32], + [atomic_load_sub_i32_acquire, XFADDW32], + [atomic_load_sub_i32_release, XFADDW32], + [atomic_load_sub_i32_acq_rel, XFADDW32], + [atomic_load_sub_i32_seq_cst, XFADDW32], + ] in { + def : Pat<(P[0] ADDRri:$addr, GPR32:$val), (P[1] ADDRri:$addr, (NEG_32 GPR32:$val))>; + } + + foreach P = [// add + [atomic_load_add_i64_monotonic, XADDD], + [atomic_load_add_i64_acquire, XFADDD], + [atomic_load_add_i64_release, XFADDD], + [atomic_load_add_i64_acq_rel, XFADDD], + [atomic_load_add_i64_seq_cst, XFADDD], + ] in { + def : Pat<(P[0] ADDRri:$addr, GPR:$val), (P[1] ADDRri:$addr, GPR:$val)>; + } +} + +foreach P = [[atomic_load_sub_i64_monotonic, XADDD], + [atomic_load_sub_i64_acquire, XFADDD], + [atomic_load_sub_i64_release, XFADDD], + [atomic_load_sub_i64_acq_rel, XFADDD], + [atomic_load_sub_i64_seq_cst, XFADDD], + ] in { + def : Pat<(P[0] ADDRri:$addr, GPR:$val), (P[1] ADDRri:$addr, (NEG_64 GPR:$val))>; +} + +// Borrow the idea from X86InstrFragments.td +class binop_no_use<SDPatternOperator operator> + : PatFrag<(ops node:$A, node:$B), + (operator node:$A, node:$B), + [{ return SDValue(N, 0).use_empty(); }]>; + +class binop_has_use<SDPatternOperator operator> + : PatFrag<(ops node:$A, node:$B), + (operator node:$A, node:$B), + [{ return !SDValue(N, 0).use_empty(); }]>; + +foreach op = [add, and, or, xor] in { +def atomic_load_ # op # _i64_monotonic_nu: + binop_no_use <!cast<SDPatternOperator>("atomic_load_"#op# _i64_monotonic)>; +def atomic_load_ # op # _i64_monotonic_hu: + binop_has_use<!cast<SDPatternOperator>("atomic_load_"#op# _i64_monotonic)>; +} + +foreach P = [// and + [atomic_load_and_i64_monotonic_nu, XANDD], + [atomic_load_and_i64_monotonic_hu, XFANDD], + [atomic_load_and_i64_acquire, XFANDD], + [atomic_load_and_i64_release, XFANDD], + [atomic_load_and_i64_acq_rel, XFANDD], + [atomic_load_and_i64_seq_cst, XFANDD], + // or + [atomic_load_or_i64_monotonic_nu, XORD], + [atomic_load_or_i64_monotonic_hu, XFORD], + [atomic_load_or_i64_acquire, XFORD], + [atomic_load_or_i64_release, XFORD], + [atomic_load_or_i64_acq_rel, XFORD], + [atomic_load_or_i64_seq_cst, XFORD], + // xor + [atomic_load_xor_i64_monotonic_nu, XXORD], + [atomic_load_xor_i64_monotonic_hu, XFXORD], + [atomic_load_xor_i64_acquire, XFXORD], + [atomic_load_xor_i64_release, XFXORD], + [atomic_load_xor_i64_acq_rel, XFXORD], + [atomic_load_xor_i64_seq_cst, XFXORD], + ] in { + def : Pat<(P[0] ADDRri:$addr, GPR:$val), (P[1] ADDRri:$addr, GPR:$val)>; +} // Atomic Exchange class XCHG<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode> diff --git a/llvm/lib/Target/BPF/BPFMIChecking.cpp b/llvm/lib/Target/BPF/BPFMIChecking.cpp index a968950f5bfc..0633836df73b 100644 --- a/llvm/lib/Target/BPF/BPFMIChecking.cpp +++ b/llvm/lib/Target/BPF/BPFMIChecking.cpp @@ -15,11 +15,8 @@ //===----------------------------------------------------------------------===// #include "BPF.h" -#include "BPFInstrInfo.h" #include "BPFTargetMachine.h" #include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/IR/DiagnosticInfo.h" #include "llvm/Support/Debug.h" @@ -43,15 +40,14 @@ private: // Initialize class variables. void initialize(MachineFunction &MFParm); - bool processAtomicInsts(); + void processAtomicInsts(); public: - // Main entry point for this pass. bool runOnMachineFunction(MachineFunction &MF) override { if (!skipFunction(MF.getFunction())) { initialize(MF); - return processAtomicInsts(); + processAtomicInsts(); } return false; } @@ -107,7 +103,7 @@ void BPFMIPreEmitChecking::initialize(MachineFunction &MFParm) { // Dead correctly, and it is safe to use such information or our purpose. static bool hasLiveDefs(const MachineInstr &MI, const TargetRegisterInfo *TRI) { const MCRegisterClass *GPR64RegClass = - &BPFMCRegisterClasses[BPF::GPRRegClassID]; + &BPFMCRegisterClasses[BPF::GPRRegClassID]; std::vector<unsigned> GPR32LiveDefs; std::vector<unsigned> GPR64DeadDefs; @@ -119,7 +115,7 @@ static bool hasLiveDefs(const MachineInstr &MI, const TargetRegisterInfo *TRI) { RegIsGPR64 = GPR64RegClass->contains(MO.getReg()); if (!MO.isDead()) { - // It is a GPR64 live Def, we are sure it is live. */ + // It is a GPR64 live Def, we are sure it is live. if (RegIsGPR64) return true; // It is a GPR32 live Def, we are unsure whether it is really dead due to @@ -153,12 +149,14 @@ static bool hasLiveDefs(const MachineInstr &MI, const TargetRegisterInfo *TRI) { return false; } -bool BPFMIPreEmitChecking::processAtomicInsts() { +void BPFMIPreEmitChecking::processAtomicInsts() { + if (MF->getSubtarget<BPFSubtarget>().getHasJmp32()) + return; + + // Only check for cpu version 1 and 2. for (MachineBasicBlock &MBB : *MF) { for (MachineInstr &MI : MBB) { - if (MI.getOpcode() != BPF::XADDW && - MI.getOpcode() != BPF::XADDD && - MI.getOpcode() != BPF::XADDW32) + if (MI.getOpcode() != BPF::XADDW && MI.getOpcode() != BPF::XADDD) continue; LLVM_DEBUG(MI.dump()); @@ -171,81 +169,14 @@ bool BPFMIPreEmitChecking::processAtomicInsts() { } } } - - // Check return values of atomic_fetch_and_{add,and,or,xor}. - // If the return is not used, the atomic_fetch_and_<op> instruction - // is replaced with atomic_<op> instruction. - MachineInstr *ToErase = nullptr; - bool Changed = false; - const BPFInstrInfo *TII = MF->getSubtarget<BPFSubtarget>().getInstrInfo(); - for (MachineBasicBlock &MBB : *MF) { - for (MachineInstr &MI : MBB) { - if (ToErase) { - ToErase->eraseFromParent(); - ToErase = nullptr; - } - - if (MI.getOpcode() != BPF::XFADDW32 && MI.getOpcode() != BPF::XFADDD && - MI.getOpcode() != BPF::XFANDW32 && MI.getOpcode() != BPF::XFANDD && - MI.getOpcode() != BPF::XFXORW32 && MI.getOpcode() != BPF::XFXORD && - MI.getOpcode() != BPF::XFORW32 && MI.getOpcode() != BPF::XFORD) - continue; - - if (hasLiveDefs(MI, TRI)) - continue; - - LLVM_DEBUG(dbgs() << "Transforming "; MI.dump()); - unsigned newOpcode; - switch (MI.getOpcode()) { - case BPF::XFADDW32: - newOpcode = BPF::XADDW32; - break; - case BPF::XFADDD: - newOpcode = BPF::XADDD; - break; - case BPF::XFANDW32: - newOpcode = BPF::XANDW32; - break; - case BPF::XFANDD: - newOpcode = BPF::XANDD; - break; - case BPF::XFXORW32: - newOpcode = BPF::XXORW32; - break; - case BPF::XFXORD: - newOpcode = BPF::XXORD; - break; - case BPF::XFORW32: - newOpcode = BPF::XORW32; - break; - case BPF::XFORD: - newOpcode = BPF::XORD; - break; - default: - llvm_unreachable("Incorrect Atomic Instruction Opcode"); - } - - BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(newOpcode)) - .add(MI.getOperand(0)) - .add(MI.getOperand(1)) - .add(MI.getOperand(2)) - .add(MI.getOperand(3)); - - ToErase = &MI; - Changed = true; - } - } - - return Changed; } -} // end default namespace +} // namespace INITIALIZE_PASS(BPFMIPreEmitChecking, "bpf-mi-pemit-checking", "BPF PreEmit Checking", false, false) char BPFMIPreEmitChecking::ID = 0; -FunctionPass* llvm::createBPFMIPreEmitCheckingPass() -{ +FunctionPass *llvm::createBPFMIPreEmitCheckingPass() { return new BPFMIPreEmitChecking(); } diff --git a/llvm/lib/Target/BPF/BPFMIPeephole.cpp b/llvm/lib/Target/BPF/BPFMIPeephole.cpp index f0edf706bd8f..106572cdeb84 100644 --- a/llvm/lib/Target/BPF/BPFMIPeephole.cpp +++ b/llvm/lib/Target/BPF/BPFMIPeephole.cpp @@ -24,6 +24,9 @@ #include "BPFInstrInfo.h" #include "BPFTargetMachine.h" #include "llvm/ADT/Statistic.h" +#include "llvm/ADT/StringExtras.h" +#include "llvm/CodeGen/LivePhysRegs.h" +#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" @@ -319,6 +322,8 @@ private: bool in16BitRange(int Num); bool eliminateRedundantMov(); bool adjustBranch(); + bool insertMissingCallerSavedSpills(); + bool removeMayGotoZero(); public: @@ -333,6 +338,8 @@ public: Changed = eliminateRedundantMov(); if (SupportGotol) Changed = adjustBranch() || Changed; + Changed |= insertMissingCallerSavedSpills(); + Changed |= removeMayGotoZero(); return Changed; } }; @@ -596,6 +603,141 @@ bool BPFMIPreEmitPeephole::adjustBranch() { return Changed; } +static const unsigned CallerSavedRegs[] = {BPF::R0, BPF::R1, BPF::R2, + BPF::R3, BPF::R4, BPF::R5}; + +struct BPFFastCall { + MachineInstr *MI; + unsigned LiveCallerSavedRegs; +}; + +static void collectBPFFastCalls(const TargetRegisterInfo *TRI, + LivePhysRegs &LiveRegs, MachineBasicBlock &BB, + SmallVectorImpl<BPFFastCall> &Calls) { + LiveRegs.init(*TRI); + LiveRegs.addLiveOuts(BB); + Calls.clear(); + for (MachineInstr &MI : llvm::reverse(BB)) { + if (MI.isCall()) { + unsigned LiveCallerSavedRegs = 0; + for (MCRegister R : CallerSavedRegs) { + bool DoSpillFill = false; + for (MCPhysReg SR : TRI->subregs(R)) + DoSpillFill |= !MI.definesRegister(SR, TRI) && LiveRegs.contains(SR); + if (!DoSpillFill) + continue; + LiveCallerSavedRegs |= 1 << R; + } + if (LiveCallerSavedRegs) + Calls.push_back({&MI, LiveCallerSavedRegs}); + } + LiveRegs.stepBackward(MI); + } +} + +static int64_t computeMinFixedObjOffset(MachineFrameInfo &MFI, + unsigned SlotSize) { + int64_t MinFixedObjOffset = 0; + // Same logic as in X86FrameLowering::adjustFrameForMsvcCxxEh() + for (int I = MFI.getObjectIndexBegin(); I < MFI.getObjectIndexEnd(); ++I) { + if (MFI.isDeadObjectIndex(I)) + continue; + MinFixedObjOffset = std::min(MinFixedObjOffset, MFI.getObjectOffset(I)); + } + MinFixedObjOffset -= + (SlotSize + MinFixedObjOffset % SlotSize) & (SlotSize - 1); + return MinFixedObjOffset; +} + +bool BPFMIPreEmitPeephole::insertMissingCallerSavedSpills() { + MachineFrameInfo &MFI = MF->getFrameInfo(); + SmallVector<BPFFastCall, 8> Calls; + LivePhysRegs LiveRegs; + const unsigned SlotSize = 8; + int64_t MinFixedObjOffset = computeMinFixedObjOffset(MFI, SlotSize); + bool Changed = false; + for (MachineBasicBlock &BB : *MF) { + collectBPFFastCalls(TRI, LiveRegs, BB, Calls); + Changed |= !Calls.empty(); + for (BPFFastCall &Call : Calls) { + int64_t CurOffset = MinFixedObjOffset; + for (MCRegister Reg : CallerSavedRegs) { + if (((1 << Reg) & Call.LiveCallerSavedRegs) == 0) + continue; + // Allocate stack object + CurOffset -= SlotSize; + MFI.CreateFixedSpillStackObject(SlotSize, CurOffset); + // Generate spill + BuildMI(BB, Call.MI->getIterator(), Call.MI->getDebugLoc(), + TII->get(BPF::STD)) + .addReg(Reg, RegState::Kill) + .addReg(BPF::R10) + .addImm(CurOffset); + // Generate fill + BuildMI(BB, ++Call.MI->getIterator(), Call.MI->getDebugLoc(), + TII->get(BPF::LDD)) + .addReg(Reg, RegState::Define) + .addReg(BPF::R10) + .addImm(CurOffset); + } + } + } + return Changed; +} + +bool BPFMIPreEmitPeephole::removeMayGotoZero() { + bool Changed = false; + MachineBasicBlock *Prev_MBB, *Curr_MBB = nullptr; + + for (MachineBasicBlock &MBB : make_early_inc_range(reverse(*MF))) { + Prev_MBB = Curr_MBB; + Curr_MBB = &MBB; + if (Prev_MBB == nullptr || Curr_MBB->empty()) + continue; + + MachineInstr &MI = Curr_MBB->back(); + if (MI.getOpcode() != TargetOpcode::INLINEASM_BR) + continue; + + const char *AsmStr = MI.getOperand(0).getSymbolName(); + SmallVector<StringRef, 4> AsmPieces; + SplitString(AsmStr, AsmPieces, ";\n"); + + // Do not support multiple insns in one inline asm. + if (AsmPieces.size() != 1) + continue; + + // The asm insn must be a may_goto insn. + SmallVector<StringRef, 4> AsmOpPieces; + SplitString(AsmPieces[0], AsmOpPieces, " "); + if (AsmOpPieces.size() != 2 || AsmOpPieces[0] != "may_goto") + continue; + // Enforce the format of 'may_goto <label>'. + if (AsmOpPieces[1] != "${0:l}" && AsmOpPieces[1] != "$0") + continue; + + // Get the may_goto branch target. + MachineOperand &MO = MI.getOperand(InlineAsm::MIOp_FirstOperand + 1); + if (!MO.isMBB() || MO.getMBB() != Prev_MBB) + continue; + + Changed = true; + if (Curr_MBB->begin() == MI) { + // Single 'may_goto' insn in the same basic block. + Curr_MBB->removeSuccessor(Prev_MBB); + for (MachineBasicBlock *Pred : Curr_MBB->predecessors()) + Pred->replaceSuccessor(Curr_MBB, Prev_MBB); + Curr_MBB->eraseFromParent(); + Curr_MBB = Prev_MBB; + } else { + // Remove 'may_goto' insn. + MI.eraseFromParent(); + } + } + + return Changed; +} + } // end default namespace INITIALIZE_PASS(BPFMIPreEmitPeephole, "bpf-mi-pemit-peephole", diff --git a/llvm/lib/Target/BPF/BPFPreserveDIType.cpp b/llvm/lib/Target/BPF/BPFPreserveDIType.cpp index afc154988050..d3b0c0246581 100644 --- a/llvm/lib/Target/BPF/BPFPreserveDIType.cpp +++ b/llvm/lib/Target/BPF/BPFPreserveDIType.cpp @@ -21,7 +21,6 @@ #include "llvm/IR/Module.h" #include "llvm/IR/PassManager.h" #include "llvm/IR/Type.h" -#include "llvm/IR/User.h" #include "llvm/IR/Value.h" #include "llvm/Pass.h" #include "llvm/Transforms/Utils/BasicBlockUtils.h" diff --git a/llvm/lib/Target/BPF/BPFPreserveStaticOffset.cpp b/llvm/lib/Target/BPF/BPFPreserveStaticOffset.cpp index 5d8339b4a44c..2b890ddccf62 100644 --- a/llvm/lib/Target/BPF/BPFPreserveStaticOffset.cpp +++ b/llvm/lib/Target/BPF/BPFPreserveStaticOffset.cpp @@ -105,7 +105,6 @@ #include "BPFCORE.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" -#include "llvm/IR/Argument.h" #include "llvm/IR/Attributes.h" #include "llvm/IR/BasicBlock.h" #include "llvm/IR/Constants.h" @@ -163,7 +162,7 @@ static CallInst *makeIntrinsicCall(Module *M, ArrayRef<Type *> Types, ArrayRef<Value *> Args) { - Function *Fn = Intrinsic::getDeclaration(M, Intrinsic, Types); + Function *Fn = Intrinsic::getOrInsertDeclaration(M, Intrinsic, Types); return CallInst::Create(Fn, Args); } @@ -422,12 +421,12 @@ static bool tryToReplaceWithGEPBuiltin(Instruction *LoadOrStoreTemplate, Module *M = InsnToReplace->getModule(); if (auto *Load = dyn_cast<LoadInst>(LoadOrStoreTemplate)) { Instruction *Replacement = makeGEPAndLoad(M, GEPChain, Load); - Replacement->insertBefore(InsnToReplace); + Replacement->insertBefore(InsnToReplace->getIterator()); InsnToReplace->replaceAllUsesWith(Replacement); } if (auto *Store = dyn_cast<StoreInst>(LoadOrStoreTemplate)) { Instruction *Replacement = makeGEPAndStore(M, GEPChain, Store); - Replacement->insertBefore(InsnToReplace); + Replacement->insertBefore(InsnToReplace->getIterator()); } return true; } diff --git a/llvm/lib/Target/BPF/BPFRegisterInfo.cpp b/llvm/lib/Target/BPF/BPFRegisterInfo.cpp index 84af6806abb3..307f278025ff 100644 --- a/llvm/lib/Target/BPF/BPFRegisterInfo.cpp +++ b/llvm/lib/Target/BPF/BPFRegisterInfo.cpp @@ -11,7 +11,6 @@ //===----------------------------------------------------------------------===// #include "BPFRegisterInfo.h" -#include "BPF.h" #include "BPFSubtarget.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" @@ -40,6 +39,17 @@ BPFRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { return CSR_SaveList; } +const uint32_t * +BPFRegisterInfo::getCallPreservedMask(const MachineFunction &MF, + CallingConv::ID CC) const { + switch (CC) { + default: + return CSR_RegMask; + case CallingConv::PreserveAll: + return CSR_PreserveAll_RegMask; + } +} + BitVector BPFRegisterInfo::getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); markSuperRegs(Reserved, BPF::W10); // [W|R]10 is read only frame pointer diff --git a/llvm/lib/Target/BPF/BPFRegisterInfo.h b/llvm/lib/Target/BPF/BPFRegisterInfo.h index f7dea75ebea6..db868769a157 100644 --- a/llvm/lib/Target/BPF/BPFRegisterInfo.h +++ b/llvm/lib/Target/BPF/BPFRegisterInfo.h @@ -26,6 +26,9 @@ struct BPFRegisterInfo : public BPFGenRegisterInfo { const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override; + const uint32_t *getCallPreservedMask(const MachineFunction &MF, + CallingConv::ID) const override; + BitVector getReservedRegs(const MachineFunction &MF) const override; bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, diff --git a/llvm/lib/Target/BPF/BPFSelectionDAGInfo.cpp b/llvm/lib/Target/BPF/BPFSelectionDAGInfo.cpp index 4c36c0edcef6..3e29e6c7ed38 100644 --- a/llvm/lib/Target/BPF/BPFSelectionDAGInfo.cpp +++ b/llvm/lib/Target/BPF/BPFSelectionDAGInfo.cpp @@ -12,7 +12,6 @@ #include "BPFTargetMachine.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/IR/DerivedTypes.h" using namespace llvm; #define DEBUG_TYPE "bpf-selectiondag-info" diff --git a/llvm/lib/Target/BPF/BPFSubtarget.cpp b/llvm/lib/Target/BPF/BPFSubtarget.cpp index 9a8e42f32371..305e9a2bf2cd 100644 --- a/llvm/lib/Target/BPF/BPFSubtarget.cpp +++ b/llvm/lib/Target/BPF/BPFSubtarget.cpp @@ -65,6 +65,8 @@ void BPFSubtarget::initializeEnvironment() { } void BPFSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { + if (CPU.empty()) + CPU = "v3"; if (CPU == "probe") CPU = sys::detail::getHostCPUNameForBPF(); if (CPU == "generic" || CPU == "v1") diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.cpp b/llvm/lib/Target/BPF/BPFTargetMachine.cpp index 7d91fa8bb824..3379af6fe874 100644 --- a/llvm/lib/Target/BPF/BPFTargetMachine.cpp +++ b/llvm/lib/Target/BPF/BPFTargetMachine.cpp @@ -26,7 +26,6 @@ #include "llvm/InitializePasses.h" #include "llvm/MC/TargetRegistry.h" #include "llvm/Passes/PassBuilder.h" -#include "llvm/Support/FormattedStream.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Scalar/SimplifyCFG.h" @@ -69,9 +68,9 @@ BPFTargetMachine::BPFTargetMachine(const Target &T, const Triple &TT, std::optional<Reloc::Model> RM, std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, bool JIT) - : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, - getEffectiveRelocModel(RM), - getEffectiveCodeModel(CM, CodeModel::Small), OL), + : CodeGenTargetMachineImpl(T, computeDataLayout(TT), TT, CPU, FS, Options, + getEffectiveRelocModel(RM), + getEffectiveCodeModel(CM, CodeModel::Small), OL), TLOF(std::make_unique<TargetLoweringObjectFileELF>()), Subtarget(TT, std::string(CPU), std::string(FS), *this) { initAsmInfo(); @@ -138,7 +137,7 @@ void BPFTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) { FPM.addPass(BPFPreserveStaticOffsetPass(false)); }); PB.registerPipelineEarlySimplificationEPCallback( - [=](ModulePassManager &MPM, OptimizationLevel) { + [=](ModulePassManager &MPM, OptimizationLevel, ThinOrFullLTOPhase) { MPM.addPass(BPFAdjustOptPass()); }); } diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.h b/llvm/lib/Target/BPF/BPFTargetMachine.h index 4e6adc722e76..15230bd06dad 100644 --- a/llvm/lib/Target/BPF/BPFTargetMachine.h +++ b/llvm/lib/Target/BPF/BPFTargetMachine.h @@ -14,11 +14,11 @@ #define LLVM_LIB_TARGET_BPF_BPFTARGETMACHINE_H #include "BPFSubtarget.h" -#include "llvm/Target/TargetMachine.h" +#include "llvm/CodeGen/CodeGenTargetMachineImpl.h" #include <optional> namespace llvm { -class BPFTargetMachine : public LLVMTargetMachine { +class BPFTargetMachine : public CodeGenTargetMachineImpl { std::unique_ptr<TargetLoweringObjectFile> TLOF; BPFSubtarget Subtarget; diff --git a/llvm/lib/Target/BPF/BPFTargetTransformInfo.h b/llvm/lib/Target/BPF/BPFTargetTransformInfo.h index 13dcae7e67bc..bf0bef3a2b2f 100644 --- a/llvm/lib/Target/BPF/BPFTargetTransformInfo.h +++ b/llvm/lib/Target/BPF/BPFTargetTransformInfo.h @@ -44,23 +44,24 @@ public: return TTI::TCC_Basic; } - InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, - CmpInst::Predicate VecPred, - TTI::TargetCostKind CostKind, - const llvm::Instruction *I = nullptr) { + InstructionCost getCmpSelInstrCost( + unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, + TTI::TargetCostKind CostKind, + TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, + TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, + const llvm::Instruction *I = nullptr) { if (Opcode == Instruction::Select) return SCEVCheapExpansionBudget.getValue(); return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, - I); + Op1Info, Op2Info, I); } InstructionCost getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, - ArrayRef<const Value *> Args = std::nullopt, - const Instruction *CxtI = nullptr) { + ArrayRef<const Value *> Args = {}, const Instruction *CxtI = nullptr) { int ISD = TLI->InstructionOpcodeToISD(Opcode); if (ISD == ISD::ADD && CostKind == TTI::TCK_RecipThroughput) return SCEVCheapExpansionBudget.getValue() + 1; diff --git a/llvm/lib/Target/BPF/BTFDebug.cpp b/llvm/lib/Target/BPF/BTFDebug.cpp index 4d847abea731..1a9ee3128e20 100644 --- a/llvm/lib/Target/BPF/BTFDebug.cpp +++ b/llvm/lib/Target/BPF/BTFDebug.cpp @@ -35,6 +35,15 @@ static const char *BTFKindStr[] = { #include "llvm/DebugInfo/BTF/BTF.def" }; +static const DIType *tryRemoveAtomicType(const DIType *Ty) { + if (!Ty) + return Ty; + auto DerivedTy = dyn_cast<DIDerivedType>(Ty); + if (DerivedTy && DerivedTy->getTag() == dwarf::DW_TAG_atomic_type) + return DerivedTy->getBaseType(); + return Ty; +} + /// Emit a BTF common type. void BTFTypeBase::emitType(MCStreamer &OS) { OS.AddComment(std::string(BTFKindStr[Kind]) + "(id = " + std::to_string(Id) + @@ -90,7 +99,7 @@ void BTFTypeDerived::completeType(BTFDebug &BDebug) { return; // The base type for PTR/CONST/VOLATILE could be void. - const DIType *ResolvedType = DTy->getBaseType(); + const DIType *ResolvedType = tryRemoveAtomicType(DTy->getBaseType()); if (!ResolvedType) { assert((Kind == BTF::BTF_KIND_PTR || Kind == BTF::BTF_KIND_CONST || Kind == BTF::BTF_KIND_VOLATILE) && @@ -305,7 +314,7 @@ void BTFTypeStruct::completeType(BTFDebug &BDebug) { } else { BTFMember.Offset = DDTy->getOffsetInBits(); } - const auto *BaseTy = DDTy->getBaseType(); + const auto *BaseTy = tryRemoveAtomicType(DDTy->getBaseType()); BTFMember.Type = BDebug.getTypeId(BaseTy); Members.push_back(BTFMember); } @@ -342,7 +351,7 @@ void BTFTypeFuncProto::completeType(BTFDebug &BDebug) { IsCompleted = true; DITypeRefArray Elements = STy->getTypeArray(); - auto RetType = Elements[0]; + auto RetType = tryRemoveAtomicType(Elements[0]); BTFType.Type = RetType ? BDebug.getTypeId(RetType) : 0; BTFType.NameOff = 0; @@ -350,7 +359,7 @@ void BTFTypeFuncProto::completeType(BTFDebug &BDebug) { // to represent the vararg, encode the NameOff/Type to be 0. for (unsigned I = 1, N = Elements.size(); I < N; ++I) { struct BTF::BTFParam Param; - auto Element = Elements[I]; + auto Element = tryRemoveAtomicType(Elements[I]); if (Element) { Param.NameOff = BDebug.addString(FuncArgNames[I]); Param.Type = BDebug.getTypeId(Element); @@ -483,7 +492,7 @@ void BTFTypeTypeTag::completeType(BTFDebug &BDebug) { IsCompleted = true; BTFType.NameOff = BDebug.addString(Tag); if (DTy) { - const DIType *ResolvedType = DTy->getBaseType(); + const DIType *ResolvedType = tryRemoveAtomicType(DTy->getBaseType()); if (!ResolvedType) BTFType.Type = 0; else @@ -706,7 +715,7 @@ void BTFDebug::visitArrayType(const DICompositeType *CTy, uint32_t &TypeId) { if (auto *Element = dyn_cast_or_null<DINode>(Elements[I])) if (Element->getTag() == dwarf::DW_TAG_subrange_type) { const DISubrange *SR = cast<DISubrange>(Element); - auto *CI = SR->getCount().dyn_cast<ConstantInt *>(); + auto *CI = dyn_cast<ConstantInt *>(SR->getCount()); int64_t Count = CI->getSExtValue(); // For struct s { int b; char c[]; }, the c[] will be represented @@ -800,6 +809,10 @@ void BTFDebug::visitDerivedType(const DIDerivedType *DTy, uint32_t &TypeId, bool CheckPointer, bool SeenPointer) { unsigned Tag = DTy->getTag(); + if (Tag == dwarf::DW_TAG_atomic_type) + return visitTypeEntry(DTy->getBaseType(), TypeId, CheckPointer, + SeenPointer); + /// Try to avoid chasing pointees, esp. structure pointees which may /// unnecessary bring in a lot of types. if (CheckPointer && !SeenPointer) { @@ -1444,8 +1457,10 @@ void BTFDebug::processGlobals(bool ProcessingMapDef) { DIGlobal = GVE->getVariable(); if (SecName.starts_with(".maps")) visitMapDefType(DIGlobal->getType(), GVTypeId); - else - visitTypeEntry(DIGlobal->getType(), GVTypeId, false, false); + else { + const DIType *Ty = tryRemoveAtomicType(DIGlobal->getType()); + visitTypeEntry(Ty, GVTypeId, false, false); + } break; } @@ -1484,17 +1499,15 @@ void BTFDebug::processGlobals(bool ProcessingMapDef) { continue; // Find or create a DataSec - if (DataSecEntries.find(std::string(SecName)) == DataSecEntries.end()) { - DataSecEntries[std::string(SecName)] = - std::make_unique<BTFKindDataSec>(Asm, std::string(SecName)); - } + auto [It, Inserted] = DataSecEntries.try_emplace(std::string(SecName)); + if (Inserted) + It->second = std::make_unique<BTFKindDataSec>(Asm, std::string(SecName)); // Calculate symbol size const DataLayout &DL = Global.getDataLayout(); uint32_t Size = DL.getTypeAllocSize(Global.getValueType()); - DataSecEntries[std::string(SecName)]->addDataSecEntry(VarId, - Asm->getSymbol(&Global), Size); + It->second->addDataSecEntry(VarId, Asm->getSymbol(&Global), Size); if (Global.hasInitializer()) processGlobalInitializer(Global.getInitializer()); @@ -1594,14 +1607,12 @@ void BTFDebug::processFuncPrototypes(const Function *F) { if (F->hasSection()) { StringRef SecName = F->getSection(); - if (DataSecEntries.find(std::string(SecName)) == DataSecEntries.end()) { - DataSecEntries[std::string(SecName)] = - std::make_unique<BTFKindDataSec>(Asm, std::string(SecName)); - } + auto [It, Inserted] = DataSecEntries.try_emplace(std::string(SecName)); + if (Inserted) + It->second = std::make_unique<BTFKindDataSec>(Asm, std::string(SecName)); // We really don't know func size, set it to 0. - DataSecEntries[std::string(SecName)]->addDataSecEntry(FuncId, - Asm->getSymbol(F), 0); + It->second->addDataSecEntry(FuncId, Asm->getSymbol(F), 0); } } diff --git a/llvm/lib/Target/BPF/GISel/BPFCallLowering.cpp b/llvm/lib/Target/BPF/GISel/BPFCallLowering.cpp index 3829a1a3151f..87d92da1b576 100644 --- a/llvm/lib/Target/BPF/GISel/BPFCallLowering.cpp +++ b/llvm/lib/Target/BPF/GISel/BPFCallLowering.cpp @@ -14,7 +14,6 @@ #include "BPFCallLowering.h" #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" -#include "llvm/Support/Debug.h" #define DEBUG_TYPE "bpf-call-lowering" diff --git a/llvm/lib/Target/BPF/GISel/BPFInstructionSelector.cpp b/llvm/lib/Target/BPF/GISel/BPFInstructionSelector.cpp index c7db93a260c4..16cc98e24511 100644 --- a/llvm/lib/Target/BPF/GISel/BPFInstructionSelector.cpp +++ b/llvm/lib/Target/BPF/GISel/BPFInstructionSelector.cpp @@ -16,9 +16,7 @@ #include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h" #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" -#include "llvm/CodeGen/MachineFunction.h" #include "llvm/IR/IntrinsicsBPF.h" -#include "llvm/Support/Debug.h" #define DEBUG_TYPE "bpf-gisel" diff --git a/llvm/lib/Target/BPF/GISel/BPFLegalizerInfo.cpp b/llvm/lib/Target/BPF/GISel/BPFLegalizerInfo.cpp index 04220c176376..7c95ecc075f3 100644 --- a/llvm/lib/Target/BPF/GISel/BPFLegalizerInfo.cpp +++ b/llvm/lib/Target/BPF/GISel/BPFLegalizerInfo.cpp @@ -10,7 +10,6 @@ //===----------------------------------------------------------------------===// #include "BPFLegalizerInfo.h" -#include "llvm/Support/Debug.h" #define DEBUG_TYPE "bpf-legalinfo" diff --git a/llvm/lib/Target/BPF/GISel/BPFRegisterBankInfo.cpp b/llvm/lib/Target/BPF/GISel/BPFRegisterBankInfo.cpp index f50e8f524a87..54601a776409 100644 --- a/llvm/lib/Target/BPF/GISel/BPFRegisterBankInfo.cpp +++ b/llvm/lib/Target/BPF/GISel/BPFRegisterBankInfo.cpp @@ -10,9 +10,6 @@ //===----------------------------------------------------------------------===// #include "BPFRegisterBankInfo.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/Support/Debug.h" #define DEBUG_TYPE "bpf-reg-bank-info" diff --git a/llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp b/llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp index a7a08714f05f..25bfb7ae143c 100644 --- a/llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp +++ b/llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp @@ -8,7 +8,6 @@ #include "MCTargetDesc/BPFMCFixups.h" #include "MCTargetDesc/BPFMCTargetDesc.h" -#include "llvm/ADT/StringRef.h" #include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCContext.h" diff --git a/llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.cpp b/llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.cpp index c266538bec73..792aa47e77a0 100644 --- a/llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.cpp +++ b/llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.cpp @@ -10,17 +10,14 @@ // //===----------------------------------------------------------------------===// - -#include "BPF.h" #include "MCTargetDesc/BPFInstPrinter.h" +#include "BPF.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" -#include "llvm/MC/MCRegister.h" #include "llvm/MC/MCSymbol.h" #include "llvm/Support/Casting.h" #include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/FormattedStream.h" using namespace llvm; #define DEBUG_TYPE "asm-printer" diff --git a/llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.h b/llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.h index ad2dee1a97b8..41835bb2d10d 100644 --- a/llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.h +++ b/llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.h @@ -32,7 +32,8 @@ public: void printBrTargetOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); // Autogenerated by tblgen. - std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override; + std::pair<const char *, uint64_t> + getMnemonic(const MCInst &MI) const override; void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O); static const char *getRegisterName(MCRegister Reg); }; diff --git a/llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp b/llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp index b807d6904004..10a46f100bbe 100644 --- a/llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp +++ b/llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp @@ -20,7 +20,6 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/Support/Endian.h" #include "llvm/Support/EndianStream.h" #include <cassert> #include <cstdint> |