diff options
Diffstat (limited to 'llvm/lib/Target/LoongArch/LoongArch.td')
| -rw-r--r-- | llvm/lib/Target/LoongArch/LoongArch.td | 40 |
1 files changed, 38 insertions, 2 deletions
diff --git a/llvm/lib/Target/LoongArch/LoongArch.td b/llvm/lib/Target/LoongArch/LoongArch.td index ddb27dc6404f..5fd52babfc6e 100644 --- a/llvm/lib/Target/LoongArch/LoongArch.td +++ b/llvm/lib/Target/LoongArch/LoongArch.td @@ -112,6 +112,35 @@ def FeatureFrecipe "Support frecipe.{s/d} and frsqrte.{s/d} instructions.">; def HasFrecipe : Predicate<"Subtarget->hasFrecipe()">; +// Atomic memory swap and add instructions for byte and half word +def FeatureLAM_BH + : SubtargetFeature<"lam-bh", "HasLAM_BH", "true", + "Support amswap[_db].{b/h} and amadd[_db].{b/h} instructions.">; +def HasLAM_BH : Predicate<"Subtarget->hasLAM_BH()">; + +// Atomic memory compare and swap instructions for byte, half word, word and double word +def FeatureLAMCAS + : SubtargetFeature<"lamcas", "HasLAMCAS", "true", + "Support amcas[_db].{b/h/w/d}.">; +def HasLAMCAS : Predicate<"Subtarget->hasLAMCAS()">; + +def FeatureLD_SEQ_SA + : SubtargetFeature<"ld-seq-sa", "HasLD_SEQ_SA", "true", + "Don't use load-load barrier (dbar 0x700).">; +def HasLD_SEQ_SA : Predicate<"Subtarget->hasLD_SEQ_SA()">; + +// Assume div.w[u] and mod.w[u] can handle inputs that are not sign-extended. +def FeatureDiv32 + : SubtargetFeature<"div32", "HasDiv32", "true", + "Assume div.w[u] and mod.w[u] can handle inputs that are not sign-extended">; +def HasDiv32 : Predicate<"Subtarget->hasDiv32()">; + +// Support SC.Q instruction +def FeatureSCQ + : SubtargetFeature<"scq", "HasSCQ", "true", + "Support sc.q instruction">; +def HasSCQ : Predicate<"Subtarget->hasSCQ()">; + def TunePreferWInst : SubtargetFeature<"prefer-w-inst", "PreferWInst", "true", "Prefer instructions with W suffix">; @@ -129,7 +158,9 @@ include "LoongArchInstrInfo.td" //===----------------------------------------------------------------------===// def : ProcessorModel<"generic-la32", NoSchedModel, [Feature32Bit]>; -def : ProcessorModel<"generic-la64", NoSchedModel, [Feature64Bit, FeatureUAL]>; +def : ProcessorModel<"generic-la64", NoSchedModel, [Feature64Bit, + FeatureUAL, + FeatureExtLSX]>; // Generic 64-bit processor with double-precision floating-point support. def : ProcessorModel<"loongarch64", NoSchedModel, [Feature64Bit, @@ -151,7 +182,12 @@ def : ProcessorModel<"la664", NoSchedModel, [Feature64Bit, FeatureExtLASX, FeatureExtLVZ, FeatureExtLBT, - FeatureFrecipe]>; + FeatureFrecipe, + FeatureLAM_BH, + FeatureLAMCAS, + FeatureLD_SEQ_SA, + FeatureDiv32, + FeatureSCQ]>; //===----------------------------------------------------------------------===// // Define the LoongArch target. |