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-rw-r--r--llvm/lib/Target/MSP430/MSP430InstrInfo.td166
1 files changed, 58 insertions, 108 deletions
diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.td b/llvm/lib/Target/MSP430/MSP430InstrInfo.td
index 714a5d4f5116..546ba6fd8e3b 100644
--- a/llvm/lib/Target/MSP430/MSP430InstrInfo.td
+++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.td
@@ -451,21 +451,17 @@ multiclass Arith<bits<4> opcode, string asmstring, SDPatternOperator node,
let isCommutable = commutes in {
def 8rr : I8rr<opcode, (outs GR8:$rd), (ins GR8:$src2, GR8:$rs),
!strconcat(asmstring, ".b\t$rs, $rd"),
- [(set GR8:$rd, (node GR8:$src2, GR8:$rs)),
- (implicit SR)]>;
+ [(set GR8:$rd, (node GR8:$src2, GR8:$rs))]>;
def 16rr : I16rr<opcode, (outs GR16:$rd), (ins GR16:$src2, GR16:$rs),
!strconcat(asmstring, "\t$rs, $rd"),
- [(set GR16:$rd, (node GR16:$src2, GR16:$rs)),
- (implicit SR)]>;
+ [(set GR16:$rd, (node GR16:$src2, GR16:$rs))]>;
}
def 8rm : I8rm<opcode, (outs GR8:$rd), (ins GR8:$src2, memsrc:$src),
!strconcat(asmstring, ".b\t$src, $rd"),
- [(set GR8:$rd, (node GR8:$src2, (load addr:$src))),
- (implicit SR)]>;
+ [(set GR8:$rd, (node GR8:$src2, (load addr:$src)))]>;
def 16rm : I16rm<opcode, (outs GR16:$rd), (ins GR16:$src2, memsrc:$src),
!strconcat(asmstring, "\t$src, $rd"),
- [(set GR16:$rd, (node GR16:$src2, (load addr:$src))),
- (implicit SR)]>;
+ [(set GR16:$rd, (node GR16:$src2, (load addr:$src)))]>;
def 8rn : I8rn<opcode, (outs GR8:$rd), (ins GR8:$src2, indreg:$rs),
!strconcat(asmstring, ".b\t$rs, $rd"), []>;
def 16rn : I16rn<opcode, (outs GR16:$rd), (ins GR16:$src2, indreg:$rs),
@@ -480,55 +476,43 @@ multiclass Arith<bits<4> opcode, string asmstring, SDPatternOperator node,
}
def 8rc : I8rc<opcode, (outs GR8:$rd), (ins GR8:$src2, cg8imm:$imm),
!strconcat(asmstring, ".b\t$imm, $rd"),
- [(set GR8:$rd, (node GR8:$src2, cg8imm:$imm)),
- (implicit SR)]>;
+ [(set GR8:$rd, (node GR8:$src2, cg8imm:$imm))]>;
def 16rc : I16rc<opcode, (outs GR16:$rd), (ins GR16:$src2, cg16imm:$imm),
!strconcat(asmstring, "\t$imm, $rd"),
- [(set GR16:$rd, (node GR16:$src2, cg16imm:$imm)),
- (implicit SR)]>;
+ [(set GR16:$rd, (node GR16:$src2, cg16imm:$imm))]>;
def 8ri : I8ri<opcode, (outs GR8:$rd), (ins GR8:$src2, i8imm:$imm),
!strconcat(asmstring, ".b\t$imm, $rd"),
- [(set GR8:$rd, (node GR8:$src2, imm:$imm)),
- (implicit SR)]>;
+ [(set GR8:$rd, (node GR8:$src2, imm:$imm))]>;
def 16ri : I16ri<opcode, (outs GR16:$rd), (ins GR16:$src2, i16imm:$imm),
!strconcat(asmstring, "\t$imm, $rd"),
- [(set GR16:$rd, (node GR16:$src2, imm:$imm)),
- (implicit SR)]>;
+ [(set GR16:$rd, (node GR16:$src2, imm:$imm))]>;
}
def 8mr : I8mr<opcode, (outs), (ins memdst:$dst, GR8:$rs),
!strconcat(asmstring, ".b\t$rs, $dst"),
- [(store (node (load addr:$dst), GR8:$rs), addr:$dst),
- (implicit SR)]>;
+ [(store (node (load addr:$dst), GR8:$rs), addr:$dst)]>;
def 16mr : I16mr<opcode, (outs), (ins memdst:$dst, GR16:$rs),
!strconcat(asmstring, "\t$rs, $dst"),
- [(store (node (load addr:$dst), GR16:$rs), addr:$dst),
- (implicit SR)]>;
+ [(store (node (load addr:$dst), GR16:$rs), addr:$dst)]>;
def 8mc : I8mc<opcode, (outs), (ins memdst:$dst, cg8imm:$imm),
!strconcat(asmstring, ".b\t$imm, $dst"),
- [(store (node (load addr:$dst), (i8 cg8imm:$imm)), addr:$dst),
- (implicit SR)]>;
+ [(store (node (load addr:$dst), (i8 cg8imm:$imm)), addr:$dst)]>;
def 16mc : I16mc<opcode, (outs), (ins memdst:$dst, cg16imm:$imm),
!strconcat(asmstring, "\t$imm, $dst"),
- [(store (node (load addr:$dst), (i16 cg16imm:$imm)), addr:$dst),
- (implicit SR)]>;
+ [(store (node (load addr:$dst), (i16 cg16imm:$imm)), addr:$dst)]>;
def 8mi : I8mi<opcode, (outs), (ins memdst:$dst, i8imm:$imm),
!strconcat(asmstring, ".b\t$imm, $dst"),
- [(store (node (load addr:$dst), (i8 imm:$imm)), addr:$dst),
- (implicit SR)]>;
+ [(store (node (load addr:$dst), (i8 imm:$imm)), addr:$dst)]>;
def 16mi : I16mi<opcode, (outs), (ins memdst:$dst, i16imm:$imm),
!strconcat(asmstring, "\t$imm, $dst"),
- [(store (node (load addr:$dst), (i16 imm:$imm)), addr:$dst),
- (implicit SR)]>;
+ [(store (node (load addr:$dst), (i16 imm:$imm)), addr:$dst)]>;
def 8mm : I8mm<opcode, (outs), (ins memdst:$dst, memsrc:$src),
!strconcat(asmstring, ".b\t$src, $dst"),
[(store (node (load addr:$dst),
- (i8 (load addr:$src))), addr:$dst),
- (implicit SR)]>;
+ (i8 (load addr:$src))), addr:$dst)]>;
def 16mm : I16mm<opcode, (outs), (ins memdst:$dst, memsrc:$src),
!strconcat(asmstring, "\t$src, $dst"),
[(store (node (load addr:$dst),
- (i16 (load addr:$src))), addr:$dst),
- (implicit SR)]>;
+ (i16 (load addr:$src))), addr:$dst)]>;
def 8mn : I8mn<opcode, (outs), (ins memdst:$dst, indreg:$rs),
!strconcat(asmstring, ".b\t$rs, $dst"), []>;
def 16mn : I16mn<opcode, (outs), (ins memdst:$dst, indreg:$rs),
@@ -631,32 +615,27 @@ let Defs = [SR] in {
def RRA8r : II8r<0b010,
(outs GR8:$rd), (ins GR8:$rs),
"rra.b\t$rd",
- [(set GR8:$rd, (MSP430rra GR8:$rs)),
- (implicit SR)]>;
+ [(set GR8:$rd, (MSP430rra GR8:$rs))]>;
def RRA16r : II16r<0b010,
(outs GR16:$rd), (ins GR16:$rs),
"rra\t$rd",
- [(set GR16:$rd, (MSP430rra GR16:$rs)),
- (implicit SR)]>;
+ [(set GR16:$rd, (MSP430rra GR16:$rs))]>;
let Uses = [SR] in {
def RRC8r : II8r<0b000,
(outs GR8:$rd), (ins GR8:$rs),
"rrc.b\t$rd",
- [(set GR8:$rd, (MSP430rrc GR8:$rs)),
- (implicit SR)]>;
+ [(set GR8:$rd, (MSP430rrc GR8:$rs))]>;
def RRC16r : II16r<0b000,
(outs GR16:$rd), (ins GR16:$rs),
"rrc\t$rd",
- [(set GR16:$rd, (MSP430rrc GR16:$rs)),
- (implicit SR)]>;
+ [(set GR16:$rd, (MSP430rrc GR16:$rs))]>;
} // Uses = [SR]
def SEXT16r : II16r<0b011,
(outs GR16:$rd), (ins GR16:$rs),
"sxt\t$rd",
- [(set GR16:$rd, (sext_inreg GR16:$rs, i8)),
- (implicit SR)]>;
+ [(set GR16:$rd, (sext_inreg GR16:$rs, i8))]>;
} // Defs = [SR]
@@ -678,13 +657,11 @@ let Defs = [SR] in {
def RRA8m : II8m<0b010,
(outs), (ins memsrc:$src),
"rra.b\t$src",
- [(store (MSP430rra (i8 (load addr:$src))), addr:$src),
- (implicit SR)]>;
+ [(store (MSP430rra (i8 (load addr:$src))), addr:$src)]>;
def RRA16m : II16m<0b010,
(outs), (ins memsrc:$src),
"rra\t$src",
- [(store (MSP430rra (i16 (load addr:$src))), addr:$src),
- (implicit SR)]>;
+ [(store (MSP430rra (i16 (load addr:$src))), addr:$src)]>;
def RRA8n : II8n<0b010, (outs), (ins indreg:$rs), "rra.b\t$rs", []>;
def RRA16n : II16n<0b010, (outs), (ins indreg:$rs), "rra\t$rs", []>;
@@ -695,13 +672,11 @@ let Uses = [SR] in {
def RRC8m : II8m<0b000,
(outs), (ins memsrc:$src),
"rrc.b\t$src",
- [(store (MSP430rrc (i8 (load addr:$src))), addr:$src),
- (implicit SR)]>;
+ [(store (MSP430rrc (i8 (load addr:$src))), addr:$src)]>;
def RRC16m : II16m<0b000,
(outs), (ins memsrc:$src),
"rrc\t$src",
- [(store (MSP430rrc (i16 (load addr:$src))), addr:$src),
- (implicit SR)]>;
+ [(store (MSP430rrc (i16 (load addr:$src))), addr:$src)]>;
def RRC8n : II8n<0b000, (outs), (ins indreg:$rs), "rrc.b\t$rs", []>;
def RRC16n : II16n<0b000, (outs), (ins indreg:$rs), "rrc\t$rs", []>;
@@ -714,8 +689,7 @@ def SEXT16m : II16m<0b011,
(outs), (ins memsrc:$src),
"sxt\t$src",
[(store (sext_inreg (extloadi16i8 addr:$src), i8),
- addr:$src),
- (implicit SR)]>;
+ addr:$src)]>;
def SEXT16n : II16n<0b011, (outs), (ins indreg:$rs), "sxt\t$rs", []>;
def SEXT16p : II16p<0b011, (outs), (ins postreg:$rs), "sxt\t$rs", []>;
@@ -733,62 +707,58 @@ let Defs = [SR] in {
def CMP8rr : I8rr<0b1001,
(outs), (ins GR8:$rd, GR8:$rs),
"cmp.b\t$rs, $rd",
- [(MSP430cmp GR8:$rd, GR8:$rs), (implicit SR)]>;
+ [(MSP430cmp GR8:$rd, GR8:$rs)]>;
def CMP16rr : I16rr<0b1001,
(outs), (ins GR16:$rd, GR16:$rs),
"cmp\t$rs, $rd",
- [(MSP430cmp GR16:$rd, GR16:$rs), (implicit SR)]>;
+ [(MSP430cmp GR16:$rd, GR16:$rs)]>;
def CMP8rc : I8rc<0b1001,
(outs), (ins GR8:$rd, cg8imm:$imm),
"cmp.b\t$imm, $rd",
- [(MSP430cmp GR8:$rd, cg8imm:$imm), (implicit SR)]>;
+ [(MSP430cmp GR8:$rd, cg8imm:$imm)]>;
def CMP16rc : I16rc<0b1001,
(outs), (ins GR16:$rd, cg16imm:$imm),
"cmp\t$imm, $rd",
- [(MSP430cmp GR16:$rd, cg16imm:$imm), (implicit SR)]>;
+ [(MSP430cmp GR16:$rd, cg16imm:$imm)]>;
def CMP8ri : I8ri<0b1001,
(outs), (ins GR8:$rd, i8imm:$imm),
"cmp.b\t$imm, $rd",
- [(MSP430cmp GR8:$rd, imm:$imm), (implicit SR)]>;
+ [(MSP430cmp GR8:$rd, imm:$imm)]>;
def CMP16ri : I16ri<0b1001,
(outs), (ins GR16:$rd, i16imm:$imm),
"cmp\t$imm, $rd",
- [(MSP430cmp GR16:$rd, imm:$imm), (implicit SR)]>;
+ [(MSP430cmp GR16:$rd, imm:$imm)]>;
def CMP8mc : I8mc<0b1001,
(outs), (ins memsrc:$dst, cg8imm:$imm),
"cmp.b\t$imm, $dst",
- [(MSP430cmp (load addr:$dst), (i8 cg8imm:$imm)),
- (implicit SR)]>;
+ [(MSP430cmp (load addr:$dst), (i8 cg8imm:$imm))]>;
def CMP16mc : I16mc<0b1001,
(outs), (ins memsrc:$dst, cg16imm:$imm),
"cmp\t$imm, $dst",
- [(MSP430cmp (load addr:$dst), (i16 cg16imm:$imm)),
- (implicit SR)]>;
+ [(MSP430cmp (load addr:$dst), (i16 cg16imm:$imm))]>;
def CMP8mi : I8mi<0b1001,
(outs), (ins memsrc:$dst, i8imm:$imm),
"cmp.b\t$imm, $dst",
[(MSP430cmp (load addr:$dst),
- (i8 imm:$imm)), (implicit SR)]>;
+ (i8 imm:$imm))]>;
def CMP16mi : I16mi<0b1001,
(outs), (ins memsrc:$dst, i16imm:$imm),
"cmp\t$imm, $dst",
[(MSP430cmp (load addr:$dst),
- (i16 imm:$imm)), (implicit SR)]>;
+ (i16 imm:$imm))]>;
def CMP8rm : I8rm<0b1001,
(outs), (ins GR8:$rd, memsrc:$src),
"cmp.b\t$src, $rd",
- [(MSP430cmp GR8:$rd, (load addr:$src)),
- (implicit SR)]>;
+ [(MSP430cmp GR8:$rd, (load addr:$src))]>;
def CMP16rm : I16rm<0b1001,
(outs), (ins GR16:$rd, memsrc:$src),
"cmp\t$src, $rd",
- [(MSP430cmp GR16:$rd, (load addr:$src)),
- (implicit SR)]>;
+ [(MSP430cmp GR16:$rd, (load addr:$src))]>;
def CMP8rn : I8rn<0b1001,
(outs), (ins GR8:$rd, indreg:$rs), "cmp.b\t$rs, $rd", []>;
@@ -803,22 +773,18 @@ def CMP16rp : I16rp<0b1001,
def CMP8mr : I8mr<0b1001,
(outs), (ins memsrc:$dst, GR8:$rs),
"cmp.b\t$rs, $dst",
- [(MSP430cmp (load addr:$dst), GR8:$rs),
- (implicit SR)]>;
+ [(MSP430cmp (load addr:$dst), GR8:$rs)]>;
def CMP16mr : I16mr<0b1001,
(outs), (ins memsrc:$dst, GR16:$rs),
"cmp\t$rs, $dst",
- [(MSP430cmp (load addr:$dst), GR16:$rs),
- (implicit SR)]>;
+ [(MSP430cmp (load addr:$dst), GR16:$rs)]>;
def CMP8mm : I8mm<0b1001,
(outs), (ins memdst:$dst, memsrc:$src),
"cmp.b\t$src, $dst",
- [(MSP430cmp (load addr:$dst), (i8 (load addr:$src))),
- (implicit SR)]>;
+ [(MSP430cmp (load addr:$dst), (i8 (load addr:$src)))]>;
def CMP16mm : I16mm<0b1001, (outs), (ins memdst:$dst, memsrc:$src),
"cmp\t$src, $dst",
- [(MSP430cmp (load addr:$dst), (i16 (load addr:$src))),
- (implicit SR)]>;
+ [(MSP430cmp (load addr:$dst), (i16 (load addr:$src)))]>;
def CMP8mn : I8mn<0b1001, (outs), (ins memsrc:$dst, indreg:$rs),
"cmp.b\t$rs, $dst", []>;
@@ -836,46 +802,38 @@ let isCommutable = 1 in {
def BIT8rr : I8rr<0b1011,
(outs), (ins GR8:$rd, GR8:$rs),
"bit.b\t$rs, $rd",
- [(MSP430cmp (and_su GR8:$rd, GR8:$rs), 0),
- (implicit SR)]>;
+ [(MSP430cmp (and_su GR8:$rd, GR8:$rs), 0)]>;
def BIT16rr : I16rr<0b1011,
(outs), (ins GR16:$rd, GR16:$rs),
"bit\t$rs, $rd",
- [(MSP430cmp (and_su GR16:$rd, GR16:$rs), 0),
- (implicit SR)]>;
+ [(MSP430cmp (and_su GR16:$rd, GR16:$rs), 0)]>;
}
def BIT8rc : I8rc<0b1011,
(outs), (ins GR8:$rd, cg8imm:$imm),
"bit.b\t$imm, $rd",
- [(MSP430cmp (and_su GR8:$rd, cg8imm:$imm), 0),
- (implicit SR)]>;
+ [(MSP430cmp (and_su GR8:$rd, cg8imm:$imm), 0)]>;
def BIT16rc : I16rc<0b1011,
(outs), (ins GR16:$rd, cg16imm:$imm),
"bit\t$imm, $rd",
- [(MSP430cmp (and_su GR16:$rd, cg16imm:$imm), 0),
- (implicit SR)]>;
+ [(MSP430cmp (and_su GR16:$rd, cg16imm:$imm), 0)]>;
def BIT8ri : I8ri<0b1011,
(outs), (ins GR8:$rd, i8imm:$imm),
"bit.b\t$imm, $rd",
- [(MSP430cmp (and_su GR8:$rd, imm:$imm), 0),
- (implicit SR)]>;
+ [(MSP430cmp (and_su GR8:$rd, imm:$imm), 0)]>;
def BIT16ri : I16ri<0b1011,
(outs), (ins GR16:$rd, i16imm:$imm),
"bit\t$imm, $rd",
- [(MSP430cmp (and_su GR16:$rd, imm:$imm), 0),
- (implicit SR)]>;
+ [(MSP430cmp (and_su GR16:$rd, imm:$imm), 0)]>;
def BIT8rm : I8rm<0b1011,
(outs), (ins GR8:$rd, memdst:$src),
"bit.b\t$src, $rd",
- [(MSP430cmp (and_su GR8:$rd, (load addr:$src)), 0),
- (implicit SR)]>;
+ [(MSP430cmp (and_su GR8:$rd, (load addr:$src)), 0)]>;
def BIT16rm : I16rm<0b1011,
(outs), (ins GR16:$rd, memdst:$src),
"bit\t$src, $rd",
- [(MSP430cmp (and_su GR16:$rd, (load addr:$src)), 0),
- (implicit SR)]>;
+ [(MSP430cmp (and_su GR16:$rd, (load addr:$src)), 0)]>;
def BIT8rn : I8rn<0b1011, (outs), (ins GR8:$rd, indreg:$rs),
"bit.b\t$rs, $rd", []>;
@@ -890,50 +848,42 @@ def BIT16rp : I16rp<0b1011, (outs), (ins GR16:$rd, postreg:$rs),
def BIT8mr : I8mr<0b1011,
(outs), (ins memsrc:$dst, GR8:$rs),
"bit.b\t$rs, $dst",
- [(MSP430cmp (and_su (load addr:$dst), GR8:$rs), 0),
- (implicit SR)]>;
+ [(MSP430cmp (and_su (load addr:$dst), GR8:$rs), 0)]>;
def BIT16mr : I16mr<0b1011,
(outs), (ins memsrc:$dst, GR16:$rs),
"bit\t$rs, $dst",
- [(MSP430cmp (and_su (load addr:$dst), GR16:$rs), 0),
- (implicit SR)]>;
+ [(MSP430cmp (and_su (load addr:$dst), GR16:$rs), 0)]>;
def BIT8mc : I8mc<0b1011,
(outs), (ins memsrc:$dst, cg8imm:$imm),
"bit.b\t$imm, $dst",
- [(MSP430cmp (and_su (load addr:$dst), (i8 cg8imm:$imm)), 0),
- (implicit SR)]>;
+ [(MSP430cmp (and_su (load addr:$dst), (i8 cg8imm:$imm)), 0)]>;
def BIT16mc : I16mc<0b1011,
(outs), (ins memdst:$dst, cg16imm:$imm),
"bit\t$imm, $dst",
- [(MSP430cmp (and_su (load addr:$dst), (i16 cg16imm:$imm)), 0),
- (implicit SR)]>;
+ [(MSP430cmp (and_su (load addr:$dst), (i16 cg16imm:$imm)), 0)]>;
def BIT8mi : I8mi<0b1011,
(outs), (ins memsrc:$dst, i8imm:$imm),
"bit.b\t$imm, $dst",
- [(MSP430cmp (and_su (load addr:$dst), (i8 imm:$imm)), 0),
- (implicit SR)]>;
+ [(MSP430cmp (and_su (load addr:$dst), (i8 imm:$imm)), 0)]>;
def BIT16mi : I16mi<0b1011,
(outs), (ins memsrc:$dst, i16imm:$imm),
"bit\t$imm, $dst",
- [(MSP430cmp (and_su (load addr:$dst), (i16 imm:$imm)), 0),
- (implicit SR)]>;
+ [(MSP430cmp (and_su (load addr:$dst), (i16 imm:$imm)), 0)]>;
def BIT8mm : I8mm<0b1011,
(outs), (ins memsrc:$dst, memsrc:$src),
"bit.b\t$src, $dst",
[(MSP430cmp (and_su (i8 (load addr:$dst)),
(load addr:$src)),
- 0),
- (implicit SR)]>;
+ 0)]>;
def BIT16mm : I16mm<0b1011,
(outs), (ins memsrc:$dst, memsrc:$src),
"bit\t$src, $dst",
[(MSP430cmp (and_su (i16 (load addr:$dst)),
(load addr:$src)),
- 0),
- (implicit SR)]>;
+ 0)]>;
def BIT8mn : I8mn<0b1011, (outs), (ins memsrc:$dst, indreg:$rs),
"bit.b\t$rs, $dst", []>;
def BIT16mn : I16mn<0b1011, (outs), (ins memsrc:$dst, indreg:$rs),
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-12 08:43:33 +0000