diff options
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td | 86 |
1 files changed, 32 insertions, 54 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td index 7afd6def4e4d..880ea0ae0a97 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td @@ -25,6 +25,7 @@ def rvv_vnot : PatFrag<(ops node:$in), (xor node:$in, (riscv_vmset_vl (XLenVT srcvalue)))>; multiclass VPatUSLoadStoreSDNode<ValueType type, + RegisterClass regclass, int log2sew, LMULInfo vlmul, OutPatFrag avl, @@ -33,32 +34,14 @@ multiclass VPatUSLoadStoreSDNode<ValueType type, defvar load_instr = !cast<Instruction>("PseudoVLE"#sew#"_V_"#vlmul.MX); defvar store_instr = !cast<Instruction>("PseudoVSE"#sew#"_V_"#vlmul.MX); // Load - def : Pat<(type (load GPR:$rs1)), + def : Pat<(type (load (XLenVT GPR:$rs1))), (load_instr (type (IMPLICIT_DEF)), GPR:$rs1, avl, log2sew, TA_MA)>; // Store - def : Pat<(store type:$rs2, GPR:$rs1), + def : Pat<(store (type regclass:$rs2), (XLenVT GPR:$rs1)), (store_instr reg_class:$rs2, GPR:$rs1, avl, log2sew)>; } -multiclass VPatUSLoadStoreWholeVRSDNode<ValueType type, - int log2sew, - LMULInfo vlmul, - VReg reg_class, - int sew = !shl(1, log2sew)> { - defvar load_instr = - !cast<Instruction>("VL"#!substr(vlmul.MX, 1)#"RE"#sew#"_V"); - defvar store_instr = - !cast<Instruction>("VS"#!substr(vlmul.MX, 1)#"R_V"); - - // Load - def : Pat<(type (load GPR:$rs1)), - (load_instr GPR:$rs1)>; - // Store - def : Pat<(store type:$rs2, GPR:$rs1), - (store_instr reg_class:$rs2, GPR:$rs1)>; -} - multiclass VPatUSLoadStoreMaskSDNode<MTypeInfo m> { defvar load_instr = !cast<Instruction>("PseudoVLM_V_"#m.BX); defvar store_instr = !cast<Instruction>("PseudoVSM_V_"#m.BX); @@ -67,7 +50,7 @@ multiclass VPatUSLoadStoreMaskSDNode<MTypeInfo m> { (load_instr (m.Mask (IMPLICIT_DEF)), GPR:$rs1, m.AVL, m.Log2SEW, TA_MA)>; // Store - def : Pat<(store m.Mask:$rs2, GPR:$rs1), + def : Pat<(store (m.Mask VR:$rs2), GPR:$rs1), (store_instr VR:$rs2, GPR:$rs1, m.AVL, m.Log2SEW)>; } @@ -694,13 +677,17 @@ multiclass VPatWidenBinaryFPSDNode_VV_VF_WV_WF_RM<SDNode op, : VPatWidenBinaryFPSDNode_VV_VF_RM<op, instruction_name>, VPatWidenBinaryFPSDNode_WV_WF_RM<op, instruction_name>; -multiclass VPatWidenFPMulAccSDNode_VV_VF_RM<string instruction_name> { - foreach vtiToWti = AllWidenableFloatVectors in { +multiclass VPatWidenFPMulAccSDNode_VV_VF_RM<string instruction_name, + list <VTypeInfoToWide> vtiToWtis> { + foreach vtiToWti = vtiToWtis in { defvar vti = vtiToWti.Vti; defvar wti = vtiToWti.Wti; defvar suffix = vti.LMul.MX # "_E" # vti.SEW; let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, - GetVTypePredicates<wti>.Predicates) in { + GetVTypePredicates<wti>.Predicates, + !if(!eq(vti.Scalar, bf16), + [HasStdExtZvfbfwma], + [])) in { def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), (XLenVT srcvalue))), @@ -895,23 +882,11 @@ multiclass VPatAVGADD_VV_VX_RM<SDNode vop, int vxrm, string suffix = ""> { //===----------------------------------------------------------------------===// // 7.4. Vector Unit-Stride Instructions -foreach vti = !listconcat(FractionalGroupIntegerVectors, - FractionalGroupFloatVectors, - FractionalGroupBFloatVectors) in +foreach vti = AllVectors in let Predicates = !if(!eq(vti.Scalar, f16), [HasVInstructionsF16Minimal], GetVTypePredicates<vti>.Predicates) in - defm : VPatUSLoadStoreSDNode<vti.Vector, vti.Log2SEW, vti.LMul, + defm : VPatUSLoadStoreSDNode<vti.Vector, vti.RegClass, vti.Log2SEW, vti.LMul, vti.AVL, vti.RegClass>; -foreach vti = [VI8M1, VI16M1, VI32M1, VI64M1, VBF16M1, VF16M1, VF32M1, VF64M1] in - let Predicates = !if(!eq(vti.Scalar, f16), [HasVInstructionsF16Minimal], - GetVTypePredicates<vti>.Predicates) in - defm : VPatUSLoadStoreWholeVRSDNode<vti.Vector, vti.Log2SEW, vti.LMul, - vti.RegClass>; -foreach vti = !listconcat(GroupIntegerVectors, GroupFloatVectors, GroupBFloatVectors) in - let Predicates = !if(!eq(vti.Scalar, f16), [HasVInstructionsF16Minimal], - GetVTypePredicates<vti>.Predicates) in - defm : VPatUSLoadStoreWholeVRSDNode<vti.Vector, vti.Log2SEW, vti.LMul, - vti.RegClass>; foreach mti = AllMasks in let Predicates = [HasVInstructions] in defm : VPatUSLoadStoreMaskSDNode<mti>; @@ -1166,35 +1141,35 @@ defm : VPatAVGADD_VV_VX_RM<avgceilu, 0b00, suffix = "U">; foreach mti = AllMasks in { let Predicates = [HasVInstructions] in { def : Pat<(mti.Mask (and VR:$rs1, VR:$rs2)), - (!cast<Instruction>("PseudoVMAND_MM_"#mti.LMul.MX) + (!cast<Instruction>("PseudoVMAND_MM_"#mti.BX) VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>; def : Pat<(mti.Mask (or VR:$rs1, VR:$rs2)), - (!cast<Instruction>("PseudoVMOR_MM_"#mti.LMul.MX) + (!cast<Instruction>("PseudoVMOR_MM_"#mti.BX) VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>; def : Pat<(mti.Mask (xor VR:$rs1, VR:$rs2)), - (!cast<Instruction>("PseudoVMXOR_MM_"#mti.LMul.MX) + (!cast<Instruction>("PseudoVMXOR_MM_"#mti.BX) VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>; def : Pat<(mti.Mask (rvv_vnot (and VR:$rs1, VR:$rs2))), - (!cast<Instruction>("PseudoVMNAND_MM_"#mti.LMul.MX) + (!cast<Instruction>("PseudoVMNAND_MM_"#mti.BX) VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>; def : Pat<(mti.Mask (rvv_vnot (or VR:$rs1, VR:$rs2))), - (!cast<Instruction>("PseudoVMNOR_MM_"#mti.LMul.MX) + (!cast<Instruction>("PseudoVMNOR_MM_"#mti.BX) VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>; def : Pat<(mti.Mask (rvv_vnot (xor VR:$rs1, VR:$rs2))), - (!cast<Instruction>("PseudoVMXNOR_MM_"#mti.LMul.MX) + (!cast<Instruction>("PseudoVMXNOR_MM_"#mti.BX) VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>; def : Pat<(mti.Mask (and VR:$rs1, (rvv_vnot VR:$rs2))), - (!cast<Instruction>("PseudoVMANDN_MM_"#mti.LMul.MX) + (!cast<Instruction>("PseudoVMANDN_MM_"#mti.BX) VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>; def : Pat<(mti.Mask (or VR:$rs1, (rvv_vnot VR:$rs2))), - (!cast<Instruction>("PseudoVMORN_MM_"#mti.LMul.MX) + (!cast<Instruction>("PseudoVMORN_MM_"#mti.BX) VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>; // Handle rvv_vnot the same as the vmnot.m pseudoinstruction. def : Pat<(mti.Mask (rvv_vnot VR:$rs)), - (!cast<Instruction>("PseudoVMNAND_MM_"#mti.LMul.MX) + (!cast<Instruction>("PseudoVMNAND_MM_"#mti.BX) VR:$rs, VR:$rs, mti.AVL, mti.Log2SEW)>; } } @@ -1314,7 +1289,10 @@ foreach fvti = AllFloatVectors in { } // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions -defm : VPatWidenFPMulAccSDNode_VV_VF_RM<"PseudoVFWMACC">; +defm : VPatWidenFPMulAccSDNode_VV_VF_RM<"PseudoVFWMACC", + AllWidenableFloatVectors>; +defm : VPatWidenFPMulAccSDNode_VV_VF_RM<"PseudoVFWMACCBF16", + AllWidenableBFloatToFloatVectors>; defm : VPatWidenFPNegMulAccSDNode_VV_VF_RM<"PseudoVFWNMACC">; defm : VPatWidenFPMulSacSDNode_VV_VF_RM<"PseudoVFWMSAC">; defm : VPatWidenFPNegMulSacSDNode_VV_VF_RM<"PseudoVFWNMSAC">; @@ -1397,7 +1375,7 @@ foreach fvti = !listconcat(AllFloatVectors, AllBFloatVectors) in { fvti.AVL, fvti.Log2SEW)>; def : Pat<(fvti.Vector (vselect (fvti.Mask V0), - (SplatFPOp (SelectFPImm (XLenVT GPR:$imm))), + (SplatFPOp (SelectScalarFPAsInt (XLenVT GPR:$imm))), fvti.RegClass:$rs2)), (!cast<Instruction>("PseudoVMERGE_VXM_"#fvti.LMul.MX) (fvti.Vector (IMPLICIT_DEF)), @@ -1460,7 +1438,7 @@ foreach fvtiToFWti = AllWidenableFloatVectors in { foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in { defvar fvti = fvtiToFWti.Vti; defvar fwti = fvtiToFWti.Wti; - let Predicates = [HasVInstructionsBF16] in + let Predicates = [HasVInstructionsBF16Minimal] in def : Pat<(fvti.Vector (fpround (fwti.Vector fwti.RegClass:$rs1))), (!cast<Instruction>("PseudoVFNCVTBF16_F_F_W_"#fvti.LMul.MX#"_E"#fvti.SEW) (fvti.Vector (IMPLICIT_DEF)), @@ -1474,14 +1452,14 @@ foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in { //===----------------------------------------------------------------------===// // Vector Element Extracts //===----------------------------------------------------------------------===// -foreach vti = AllFloatVectors in { - defvar vmv_f_s_inst = !cast<Instruction>(!strconcat("PseudoVFMV_", +foreach vti = NoGroupFloatVectors in { + defvar vfmv_f_s_inst = !cast<Instruction>(!strconcat("PseudoVFMV_", vti.ScalarSuffix, - "_S_", vti.LMul.MX)); + "_S")); // Only pattern-match extract-element operations where the index is 0. Any // other index will have been custom-lowered to slide the vector correctly // into place. let Predicates = GetVTypePredicates<vti>.Predicates in def : Pat<(vti.Scalar (extractelt (vti.Vector vti.RegClass:$rs2), 0)), - (vmv_f_s_inst vti.RegClass:$rs2, vti.Log2SEW)>; + (vfmv_f_s_inst vti.RegClass:$rs2, vti.Log2SEW)>; } |