1 files changed, 76 insertions, 9 deletions

diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index df11d237a16c..b19fdcb0082b 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -27,19 +27,42 @@ using namespace llvm;
 #define GET_SUBTARGETINFO_CTOR
 #include "RISCVGenSubtargetInfo.inc"
 
+static cl::opt<unsigned> RVVVectorBitsMax(
+    "riscv-v-vector-bits-max",
+    cl::desc("Assume V extension vector registers are at most this big, "
+             "with zero meaning no maximum size is assumed."),
+    cl::init(0), cl::Hidden);
+
+static cl::opt<unsigned> RVVVectorBitsMin(
+    "riscv-v-vector-bits-min",
+    cl::desc("Assume V extension vector registers are at least this big, "
+             "with zero meaning no minimum size is assumed."),
+    cl::init(0), cl::Hidden);
+
+static cl::opt<unsigned> RVVVectorLMULMax(
+    "riscv-v-fixed-length-vector-lmul-max",
+    cl::desc("The maximum LMUL value to use for fixed length vectors. "
+             "Fractional LMUL values are not supported."),
+    cl::init(8), cl::Hidden);
+
 void RISCVSubtarget::anchor() {}
 
-RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(
-    const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName) {
+RISCVSubtarget &
+RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU,
+                                                StringRef TuneCPU, StringRef FS,
+                                                StringRef ABIName) {
   // Determine default and user-specified characteristics
   bool Is64Bit = TT.isArch64Bit();
-  std::string CPUName = std::string(CPU);
-  std::string TuneCPUName = std::string(TuneCPU);
-  if (CPUName.empty())
-    CPUName = Is64Bit ? "generic-rv64" : "generic-rv32";
-  if (TuneCPUName.empty())
-    TuneCPUName = CPUName;
-  ParseSubtargetFeatures(CPUName, TuneCPUName, FS);
+  if (CPU.empty())
+    CPU = Is64Bit ? "generic-rv64" : "generic-rv32";
+  if (CPU == "generic")
+    report_fatal_error(Twine("CPU 'generic' is not supported. Use ") +
+                       (Is64Bit ? "generic-rv64" : "generic-rv32"));
+
+  if (TuneCPU.empty())
+    TuneCPU = CPU;
+
+  ParseSubtargetFeatures(CPU, TuneCPU, FS);
   if (Is64Bit) {
     XLenVT = MVT::i64;
     XLen = 64;
@@ -81,3 +104,47 @@ const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const {
 const RegisterBankInfo *RISCVSubtarget::getRegBankInfo() const {
   return RegBankInfo.get();
 }
+
+unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const {
+  assert(hasStdExtV() && "Tried to get vector length without V support!");
+  if (RVVVectorBitsMax == 0)
+    return 0;
+  assert(RVVVectorBitsMax >= 128 && RVVVectorBitsMax <= 65536 &&
+         isPowerOf2_32(RVVVectorBitsMax) &&
+         "V extension requires vector length to be in the range of 128 to "
+         "65536 and a power of 2!");
+  assert(RVVVectorBitsMax >= RVVVectorBitsMin &&
+         "Minimum V extension vector length should not be larger than its "
+         "maximum!");
+  unsigned Max = std::max(RVVVectorBitsMin, RVVVectorBitsMax);
+  return PowerOf2Floor((Max < 128 || Max > 65536) ? 0 : Max);
+}
+
+unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const {
+  assert(hasStdExtV() &&
+         "Tried to get vector length without V extension support!");
+  assert((RVVVectorBitsMin == 0 ||
+          (RVVVectorBitsMin >= 128 && RVVVectorBitsMax <= 65536 &&
+           isPowerOf2_32(RVVVectorBitsMin))) &&
+         "V extension requires vector length to be in the range of 128 to "
+         "65536 and a power of 2!");
+  assert((RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == 0) &&
+         "Minimum V extension vector length should not be larger than its "
+         "maximum!");
+  unsigned Min = RVVVectorBitsMin;
+  if (RVVVectorBitsMax != 0)
+    Min = std::min(RVVVectorBitsMin, RVVVectorBitsMax);
+  return PowerOf2Floor((Min < 128 || Min > 65536) ? 0 : Min);
+}
+
+unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {
+  assert(hasStdExtV() &&
+         "Tried to get maximum LMUL without V extension support!");
+  assert(RVVVectorLMULMax <= 8 && isPowerOf2_32(RVVVectorLMULMax) &&
+         "V extension requires a LMUL to be at most 8 and a power of 2!");
+  return PowerOf2Floor(std::max<unsigned>(RVVVectorLMULMax, 1));
+}
+
+bool RISCVSubtarget::useRVVForFixedLengthVectors() const {
+  return hasStdExtV() && getMinRVVVectorSizeInBits() != 0;
+}