diff options
Diffstat (limited to 'llvm/lib/Target/SystemZ/SystemZInstrInfo.td')
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZInstrInfo.td | 115 |
1 files changed, 93 insertions, 22 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td index 7ab0b3663630..adfd0a19859c 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td @@ -109,20 +109,11 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1 in { } // NOPs. These are again variants of the conditional branches, with the -// condition mask set to "never". NOP_bare can't be an InstAlias since it -// would need R0D hard coded which is not part of ADDR64BitRegClass. -def NOP : NeverCondBranchRX<"nop", 0x47>; -let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, X2 = 0, B2 = 0, D2 = 0 in - def NOP_bare : InstRXb<0x47,(outs), (ins), "nop", []>; -def NOPR : NeverCondBranchRR<"nopr", 0x07>; -def NOPR_bare : InstAlias<"nopr", (NOPR R0D), 0>; - -// An alias of BRC 0, label -def JNOP : InstAlias<"jnop\t$RI2", (BRCAsm 0, brtarget16:$RI2), 0>; - -// An alias of BRCL 0, label -// jgnop on att ; jlnop on hlasm -def JGNOP : InstAlias<"{jgnop|jlnop}\t$RI2", (BRCLAsm 0, brtarget32:$RI2), 0>; +// condition mask set to "never". +defm NOP : NeverCondBranchRX<"nop", 0x47>; +defm NOPR : NeverCondBranchRR<"nopr", 0x07>; +def JNOP : NeverCondBranchRI<"jnop", 0xA74>; +def JGNOP : NeverCondBranchRIL<"j{g|l}nop", 0xC04>; // Fused compare-and-branch instructions. // @@ -298,13 +289,13 @@ let Predicates = [IsTargetXPLINK64] in { } let hasNoSchedulingInfo = 1, Defs = [CC] in { - def ADA_ENTRY : Alias<12, (outs GR64:$Reg), (ins adasym:$addr, + def ADA_ENTRY : Alias<12, (outs ADDR64:$Reg), (ins adasym:$addr, ADDR64:$ADA, imm64:$Offset), [(set i64:$Reg, (z_ada_entry i64:$addr, i64:$ADA, i64:$Offset))]>; } let mayLoad = 1, AddedComplexity = 20, hasNoSchedulingInfo = 1, Defs = [CC] in { - def ADA_ENTRY_VALUE : Alias<12, (outs GR64:$Reg), (ins adasym:$addr, + def ADA_ENTRY_VALUE : Alias<12, (outs ADDR64:$Reg), (ins adasym:$addr, ADDR64:$ADA, imm64:$Offset), [(set i64:$Reg, (z_load (z_ada_entry iPTR:$addr, iPTR:$ADA, i64:$Offset)))]>; @@ -893,6 +884,39 @@ let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in def GOT : Alias<6, (outs GR64:$R1), (ins), [(set GR64:$R1, (global_offset_table))]>; +// Load (logical) indexed address. +let Predicates = [FeatureMiscellaneousExtensions4] in { + defm LXAB : LoadIndexedAddressRXY<"lxab", 0xE360, sext32>; + defm LXAH : LoadIndexedAddressRXY<"lxah", 0xE362, sext32, shl1>; + defm LXAF : LoadIndexedAddressRXY<"lxaf", 0xE364, sext32, shl2>; + defm LXAG : LoadIndexedAddressRXY<"lxag", 0xE366, sext32, shl3>; + defm LXAQ : LoadIndexedAddressRXY<"lxaq", 0xE368, sext32, shl4>; + defm LLXAB : LoadIndexedAddressRXY<"llxab", 0xE361, zext32>; + defm LLXAH : LoadIndexedAddressRXY<"llxah", 0xE363, zext32, shl1>; + defm LLXAF : LoadIndexedAddressRXY<"llxaf", 0xE365, zext32, shl2>; + defm LLXAG : LoadIndexedAddressRXY<"llxag", 0xE367, zext32, shl3>; + defm LLXAQ : LoadIndexedAddressRXY<"llxaq", 0xE369, zext32, shl4>; + + // Peepholes to use load (logical) indexed address to implement + // add + shift of an already extended value. + def : Pat<(add ADDR64:$base, (shl1 (assertsext32 ADDR64:$index))), + (LXAH ADDR64:$base, 0, (EXTRACT_SUBREG ADDR64:$index, subreg_l32))>; + def : Pat<(add ADDR64:$base, (shl2 (assertsext32 ADDR64:$index))), + (LXAF ADDR64:$base, 0, (EXTRACT_SUBREG ADDR64:$index, subreg_l32))>; + def : Pat<(add ADDR64:$base, (shl3 (assertsext32 ADDR64:$index))), + (LXAG ADDR64:$base, 0, (EXTRACT_SUBREG ADDR64:$index, subreg_l32))>; + def : Pat<(add ADDR64:$base, (shl4 (assertsext32 ADDR64:$index))), + (LXAQ ADDR64:$base, 0, (EXTRACT_SUBREG ADDR64:$index, subreg_l32))>; + def : Pat<(add ADDR64:$base, (shl1 (assertzext32 ADDR64:$index))), + (LLXAH ADDR64:$base, 0, (EXTRACT_SUBREG ADDR64:$index, subreg_l32))>; + def : Pat<(add ADDR64:$base, (shl2 (assertzext32 ADDR64:$index))), + (LLXAF ADDR64:$base, 0, (EXTRACT_SUBREG ADDR64:$index, subreg_l32))>; + def : Pat<(add ADDR64:$base, (shl3 (assertzext32 ADDR64:$index))), + (LLXAG ADDR64:$base, 0, (EXTRACT_SUBREG ADDR64:$index, subreg_l32))>; + def : Pat<(add ADDR64:$base, (shl4 (assertzext32 ADDR64:$index))), + (LLXAQ ADDR64:$base, 0, (EXTRACT_SUBREG ADDR64:$index, subreg_l32))>; +} + //===----------------------------------------------------------------------===// // Absolute and Negation //===----------------------------------------------------------------------===// @@ -960,10 +984,10 @@ def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>; def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>; -def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>; -def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>; -def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>; -def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>; +def IILL64 : BinaryAliasRI<insertll64, GR64, imm64ll16>; +def IILH64 : BinaryAliasRI<insertlh64, GR64, imm64lh16>; +def IIHL64 : BinaryAliasRI<inserthl64, GR64, imm64hl16>; +def IIHH64 : BinaryAliasRI<inserthh64, GR64, imm64hh16>; // ...likewise for 32-bit immediates. For GR32s this is a general // full-width move. (We use IILF rather than something like LLILF @@ -1830,6 +1854,19 @@ let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { def LPDG : BinarySSF<"lpdg", 0xC85, GR128>; } +// Compare and load. +let Predicates = [FeatureConcurrentFunctions], Defs = [CC] in { + def CAL : BinarySSF<"cal", 0xC86, GR32>; + def CALGF : BinarySSF<"calgf", 0xC8F, GR64>; + def CALG : BinarySSF<"calg", 0xC87, GR64>; +} + +// Perform function with concurrent results. +let Predicates = [FeatureConcurrentFunctions], Uses = [R0D], Defs = [CC], + mayLoad = 1, mayStore = 1, hasSideEffects = 1 in { + def PFCR : BinaryRSY<"pfcr", 0xEB16, null_frag, GR64>; +} + //===----------------------------------------------------------------------===// // Translate and convert //===----------------------------------------------------------------------===// @@ -1871,6 +1908,23 @@ let mayLoad = 1, mayStore = 1, Defs = [CC] in { } } +//-------------------------------------------------------------------------- +// Setjmp/Longjmp. +//-------------------------------------------------------------------------- +let isBarrier = 1, hasNoSchedulingInfo = 1 in { + let hasSideEffects = 1, usesCustomInserter = 1 in { + def EH_SjLj_SetJmp : Pseudo<(outs GR32:$dst), (ins ADDR64:$R2), + [(set GR32:$dst, (z_eh_sjlj_setjmp ADDR64:$R2))]>; + let isTerminator = 1 in { + def EH_SjLj_LongJmp : Pseudo<(outs), (ins ADDR64:$R2), + [(z_eh_sjlj_longjmp ADDR64:$R2)]>; + } + } + let isTerminator = 1, isCodeGenOnly = 1, Size = 0 in { + def EH_SjLj_Setup : Pseudo<(outs), (ins brtarget32:$dst), []>; + } +} + //===----------------------------------------------------------------------===// // Message-security assist //===----------------------------------------------------------------------===// @@ -1902,6 +1956,11 @@ let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { let Predicates = [FeatureMessageSecurityAssist9] in def KDSA : SideEffectBinaryMemRRE<"kdsa", 0xB93A, GR64, GR128>; + + let Predicates = [FeatureMessageSecurityAssist12] in { + def KIMDOpt : SideEffectTernaryMemMemRRFc<"kimd", 0xB93E, GR64, GR128, imm32zx4>; + def KLMDOpt : SideEffectTernaryMemMemRRFc<"klmd", 0xB93F, GR64, GR128, imm32zx4>; + } } //===----------------------------------------------------------------------===// @@ -2073,6 +2132,12 @@ let Predicates = [FeatureProcessorAssist] in { // Miscellaneous Instructions. //===----------------------------------------------------------------------===// +// Count leading/trailing zeros. +let Predicates = [FeatureMiscellaneousExtensions4] in { + def CLZG : UnaryRRE<"clzg", 0xB968, ctlz, GR64, GR64>; + def CTZG : UnaryRRE<"ctzg", 0xB969, cttz, GR64, GR64>; +} + // Find leftmost one, AKA count leading zeros. The instruction actually // returns a pair of GR64s, the first giving the number of leading zeros // and the second giving a copy of the source with the leftmost one bit @@ -2091,6 +2156,12 @@ let Predicates = [FeatureMiscellaneousExtensions3] in { let Predicates = [FeaturePopulationCount], Defs = [CC] in def POPCNT : UnaryRRE<"popcnt", 0xB9E1, z_popcnt, GR64, GR64>; +// Bit deposit and bit extract. +let Predicates = [FeatureMiscellaneousExtensions4] in { + def BDEPG : BinaryRRFa<"bdepg", 0xB96D, int_s390_bdepg, GR64, GR64, GR64>; + def BEXTG : BinaryRRFa<"bextg", 0xB96C, int_s390_bextg, GR64, GR64, GR64>; +} + // Search a block of memory for a character. let mayLoad = 1, Defs = [CC] in defm SRST : StringRRE<"srst", 0xB25E, z_search_string>; @@ -2351,12 +2422,12 @@ def JXHG : MnemonicAlias<"jxhg", "brxhg">; def JXLEG : MnemonicAlias<"jxleg", "brxlg">; def BRU : MnemonicAlias<"bru", "j">; -def BRUL : MnemonicAlias<"brul", "jg", "att">; +def BRUL : MnemonicAlias<"brul", "jg", "gnu">; def BRUL_HLASM : MnemonicAlias<"brul", "jlu", "hlasm">; foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { defm BRUAsm#V : MnemonicCondBranchAlias <CV<V>, "br#", "j#">; - defm BRULAsm#V : MnemonicCondBranchAlias <CV<V>, "br#l", "jg#", "att">; + defm BRULAsm#V : MnemonicCondBranchAlias <CV<V>, "br#l", "jg#", "gnu">; defm BRUL_HLASMAsm#V : MnemonicCondBranchAlias <CV<V>, "br#l", "jl#", "hlasm">; } |