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Diffstat (limited to 'llvm/lib/Target/X86/X86SchedSkylakeClient.td')
-rw-r--r--llvm/lib/Target/X86/X86SchedSkylakeClient.td78
1 files changed, 26 insertions, 52 deletions
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
index 3ee931fe5ed9..8cd52e2a8ebc 100644
--- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
@@ -236,10 +236,10 @@ defm : X86WriteRes<WriteFStoreNT, [SKLPort237,SKLPort4], 1, [1,1], 2>;
defm : X86WriteRes<WriteFStoreNTX, [SKLPort237,SKLPort4], 1, [1,1], 2>;
defm : X86WriteRes<WriteFStoreNTY, [SKLPort237,SKLPort4], 1, [1,1], 2>;
-defm : X86WriteRes<WriteFMaskedStore32, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>;
-defm : X86WriteRes<WriteFMaskedStore32Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>;
-defm : X86WriteRes<WriteFMaskedStore64, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>;
-defm : X86WriteRes<WriteFMaskedStore64Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>;
+defm : X86WriteRes<WriteFMaskedStore32, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 3>;
+defm : X86WriteRes<WriteFMaskedStore32Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 3>;
+defm : X86WriteRes<WriteFMaskedStore64, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 3>;
+defm : X86WriteRes<WriteFMaskedStore64Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 3>;
defm : X86WriteRes<WriteFMove, [SKLPort015], 1, [1], 1>;
defm : X86WriteRes<WriteFMoveX, [SKLPort015], 1, [1], 1>;
@@ -345,8 +345,8 @@ defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
defm : X86WriteRes<WriteVecLoad, [SKLPort23], 5, [1], 1>;
defm : X86WriteRes<WriteVecLoadX, [SKLPort23], 6, [1], 1>;
defm : X86WriteRes<WriteVecLoadY, [SKLPort23], 7, [1], 1>;
-defm : X86WriteRes<WriteVecLoadNT, [SKLPort23], 6, [1], 1>;
-defm : X86WriteRes<WriteVecLoadNTY, [SKLPort23], 7, [1], 1>;
+defm : X86WriteRes<WriteVecLoadNT, [SKLPort23,SKLPort015], 7, [1,1], 2>;
+defm : X86WriteRes<WriteVecLoadNTY, [SKLPort23,SKLPort015], 8, [1,1], 2>;
defm : X86WriteRes<WriteVecMaskedLoad, [SKLPort23,SKLPort015], 7, [1,1], 2>;
defm : X86WriteRes<WriteVecMaskedLoadY, [SKLPort23,SKLPort015], 8, [1,1], 2>;
defm : X86WriteRes<WriteVecStore, [SKLPort237,SKLPort4], 1, [1,1], 2>;
@@ -354,10 +354,10 @@ defm : X86WriteRes<WriteVecStoreX, [SKLPort237,SKLPort4], 1, [1,1], 2>;
defm : X86WriteRes<WriteVecStoreY, [SKLPort237,SKLPort4], 1, [1,1], 2>;
defm : X86WriteRes<WriteVecStoreNT, [SKLPort237,SKLPort4], 1, [1,1], 2>;
defm : X86WriteRes<WriteVecStoreNTY, [SKLPort237,SKLPort4], 1, [1,1], 2>;
-defm : X86WriteRes<WriteVecMaskedStore32, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>;
-defm : X86WriteRes<WriteVecMaskedStore32Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>;
-defm : X86WriteRes<WriteVecMaskedStore64, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>;
-defm : X86WriteRes<WriteVecMaskedStore64Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>;
+defm : X86WriteRes<WriteVecMaskedStore32, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 3>;
+defm : X86WriteRes<WriteVecMaskedStore32Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 3>;
+defm : X86WriteRes<WriteVecMaskedStore64, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 3>;
+defm : X86WriteRes<WriteVecMaskedStore64Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 3>;
defm : X86WriteRes<WriteVecMove, [SKLPort05], 1, [1], 1>;
defm : X86WriteRes<WriteVecMoveX, [SKLPort015], 1, [1], 1>;
defm : X86WriteRes<WriteVecMoveY, [SKLPort015], 1, [1], 1>;
@@ -387,7 +387,7 @@ defm : SKLWriteResPair<WriteShuffle, [SKLPort5], 1, [1], 1, 5>; // Vector shuff
defm : SKLWriteResPair<WriteShuffleX, [SKLPort5], 1, [1], 1, 6>;
defm : SKLWriteResPair<WriteShuffleY, [SKLPort5], 1, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WriteShuffleZ>;
-defm : SKLWriteResPair<WriteVarShuffle, [SKLPort5], 1, [1], 1, 5>; // Vector shuffles.
+defm : SKLWriteResPair<WriteVarShuffle, [SKLPort0,SKLPort5], 1, [1,1], 2, 5>; // Vector shuffles.
defm : SKLWriteResPair<WriteVarShuffleX, [SKLPort5], 1, [1], 1, 6>;
defm : SKLWriteResPair<WriteVarShuffleY, [SKLPort5], 1, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
@@ -404,7 +404,7 @@ defm : SKLWriteResPair<WritePSADBW, [SKLPort5], 3, [1], 1, 5>; // Vector PSADBW
defm : SKLWriteResPair<WritePSADBWX, [SKLPort5], 3, [1], 1, 6>;
defm : SKLWriteResPair<WritePSADBWY, [SKLPort5], 3, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WritePSADBWZ>;
-defm : SKLWriteResPair<WritePHMINPOS, [SKLPort01], 4, [1], 1, 6>; // Vector PHMINPOS.
+defm : SKLWriteResPair<WritePHMINPOS, [SKLPort0], 4, [1], 1, 6>; // Vector PHMINPOS.
// Vector integer shifts.
defm : SKLWriteResPair<WriteVecShift, [SKLPort0], 1, [1], 1, 5>;
@@ -460,8 +460,10 @@ defm : SKLWriteResPair<WriteCvtI2PSY, [SKLPort01], 4, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
defm : X86WriteRes<WriteCvtI2SD, [SKLPort5,SKLPort01], 5, [1,1], 2>;
defm : X86WriteRes<WriteCvtI2SDLd, [SKLPort23,SKLPort01], 10, [1,1], 2>;
-defm : SKLWriteResPair<WriteCvtI2PD, [SKLPort0,SKLPort5], 5, [1,1], 2, 6>;
-defm : SKLWriteResPair<WriteCvtI2PDY, [SKLPort0,SKLPort5], 7, [1,1], 2, 6>;
+defm : X86WriteRes<WriteCvtI2PD, [SKLPort5,SKLPort01], 5, [1,1], 2>;
+defm : X86WriteRes<WriteCvtI2PDLd, [SKLPort23,SKLPort01], 10, [1,1], 2>;
+defm : X86WriteRes<WriteCvtI2PDY, [SKLPort5,SKLPort01], 7, [1,1], 2>;
+defm : X86WriteRes<WriteCvtI2PDYLd, [SKLPort23,SKLPort01], 11, [1,1], 2>;
defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
defm : X86WriteRes<WriteCvtSS2SD, [SKLPort5,SKLPort01], 5, [1,1], 2>;
@@ -606,7 +608,7 @@ defm : SKLWriteResPair<WriteVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // 256-bi
def : WriteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
// Fence instructions.
-def : WriteRes<WriteFence, [SKLPort23, SKLPort4]>;
+def : WriteRes<WriteFence, [SKLPort23, SKLPort4]> { let NumMicroOps = 2; let ReleaseAtCycles = [1,1]; }
// Load/store MXCSR.
def : WriteRes<WriteLDMXCSR, [SKLPort0,SKLPort23,SKLPort0156]> { let Latency = 7; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
@@ -736,13 +738,6 @@ def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
}
def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>;
-def SKLWriteResGroup21 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
- let Latency = 2;
- let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
-}
-def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>;
-
def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
let Latency = 2;
let NumMicroOps = 2;
@@ -816,10 +811,10 @@ def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> {
def: InstRW<[SKLWriteResGroup36], (instregex "(V?)PHADDSW(Y?)rr",
"(V?)PHSUBSW(Y?)rr")>;
-def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
- let Latency = 3;
- let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5]> {
+ let Latency = 2;
+ let NumMicroOps = 2;
+ let ReleaseAtCycles = [2];
}
def: InstRW<[SKLWriteResGroup39], (instrs MMX_PACKSSDWrr,
MMX_PACKSSWBrr,
@@ -832,13 +827,6 @@ def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
}
def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>;
-def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
- let Latency = 3;
- let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
-}
-def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>;
-
def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
let Latency = 2;
let NumMicroOps = 3;
@@ -925,7 +913,7 @@ def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> {
}
def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
-def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort01]> {
+def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort0]> {
let Latency = 5;
let NumMicroOps = 2;
let ReleaseAtCycles = [1,1];
@@ -965,7 +953,7 @@ def: InstRW<[SKLWriteResGroup67], (instregex "(V?)MOVSHDUPrm",
"(V?)MOVSLDUPrm",
"(V?)MOVDDUPrm")>;
-def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0]> {
+def SKLWriteResGroup68 : SchedWriteRes<[SKLPort01]> {
let Latency = 6;
let NumMicroOps = 2;
let ReleaseAtCycles = [2];
@@ -1093,8 +1081,8 @@ def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> {
let NumMicroOps = 2;
let ReleaseAtCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup91], (instrs VINSERTF128rm,
- VINSERTI128rm,
+def: InstRW<[SKLWriteResGroup91], (instrs VINSERTF128rmi,
+ VINSERTI128rmi,
VPBLENDDrmi)>;
def: InstRW<[SKLWriteResGroup91, ReadAfterVecXLd],
(instregex "(V?)PADD(B|D|Q|W)rm",
@@ -1239,13 +1227,6 @@ def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06
}
def: SchedAlias<WriteADCRMW, SKLWriteResGroup119>;
-def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> {
- let Latency = 9;
- let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
-}
-def: InstRW<[SKLWriteResGroup120], (instrs MMX_CVTPI2PSrm)>;
-
def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let Latency = 9;
let NumMicroOps = 2;
@@ -1258,7 +1239,7 @@ def: InstRW<[SKLWriteResGroup121], (instrs PCMPGTQrm,
VPMOVSXWDYrm,
VPMOVZXWDYrm)>;
-def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort01]> {
+def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort0]> {
let Latency = 9;
let NumMicroOps = 2;
let ReleaseAtCycles = [1,1];
@@ -1290,13 +1271,6 @@ def: InstRW<[SKLWriteResGroup133], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
"ILD_F(16|32|64)m")>;
def: InstRW<[SKLWriteResGroup133], (instrs VPCMPGTQYrm)>;
-def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
- let Latency = 10;
- let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
-}
-def: InstRW<[SKLWriteResGroup138], (instrs MMX_CVTPI2PDrm)>;
-
def SKLWriteResGroup140 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
let Latency = 10;
let NumMicroOps = 4;
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-11 01:25:57 +0000