diff options
Diffstat (limited to 'llvm/lib/Target/X86/X86ScheduleBdVer2.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleBdVer2.td | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleBdVer2.td b/llvm/lib/Target/X86/X86ScheduleBdVer2.td index 0a201bc74a48..99d4011dae77 100644 --- a/llvm/lib/Target/X86/X86ScheduleBdVer2.td +++ b/llvm/lib/Target/X86/X86ScheduleBdVer2.td @@ -269,6 +269,7 @@ def : WriteRes<WriteLoad, [PdLoad]> { let Latency = 5; let ResourceCycles = [ def : WriteRes<WriteStore, [PdStore]>; def : WriteRes<WriteStoreNT, [PdStore]>; def : WriteRes<WriteMove, [PdEX01]> { let ResourceCycles = [2]; } +defm : X86WriteResUnsupported<WriteVecMaskedGatherWriteback>; // Load/store MXCSR. // FIXME: These are copy and pasted from WriteLoad/Store. @@ -1196,6 +1197,7 @@ defm : PdWriteResYMMPair<WriteVecTestY, [PdFPU01, PdFPFMA, PdEX0], 1, [2, 4 defm : X86WriteResPairUnsupported<WriteVecTestZ>; defm : PdWriteResXMMPair<WriteShuffle256, [PdFPU01, PdFPMAL]>; +defm : PdWriteResXMMPair<WriteVPMOV256, [PdFPU01, PdFPMAL]>; defm : PdWriteResXMMPair<WriteVarShuffle256, [PdFPU01, PdFPMAL]>; defm : PdWriteResXMMPair<WriteVarVecShift, [PdFPU01, PdFPMAL], 3, [1, 2]>; |