diff options
Diffstat (limited to 'source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp')
| -rw-r--r-- | source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp | 36 |
1 files changed, 16 insertions, 20 deletions
diff --git a/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp b/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp index e920d70cd596..61c3c64d4fc3 100644 --- a/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp +++ b/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp @@ -38,7 +38,7 @@ #include "lldb/Target/Target.h" #include "lldb/Target/StackFrame.h" -#include <regex.h> +#include "lldb/Core/RegularExpression.h" using namespace lldb; using namespace lldb_private; @@ -369,20 +369,14 @@ public: } } - if (!s_regex_compiled) - { - ::regcomp(&s_regex, "[ \t]*([^ ^\t]+)[ \t]*([^ ^\t].*)?", REG_EXTENDED); - s_regex_compiled = true; - } + static RegularExpression s_regex("[ \t]*([^ ^\t]+)[ \t]*([^ ^\t].*)?", REG_EXTENDED); - ::regmatch_t matches[3]; + RegularExpression::Match matches(3); - if (!::regexec(&s_regex, out_string, sizeof(matches) / sizeof(::regmatch_t), matches, 0)) + if (s_regex.Execute(out_string, &matches)) { - if (matches[1].rm_so != -1) - m_opcode_name.assign(out_string + matches[1].rm_so, matches[1].rm_eo - matches[1].rm_so); - if (matches[2].rm_so != -1) - m_mnemonics.assign(out_string + matches[2].rm_so, matches[2].rm_eo - matches[2].rm_so); + matches.GetMatchAtIndex(out_string, 1, m_opcode_name); + matches.GetMatchAtIndex(out_string, 2, m_mnemonics); } } } @@ -415,13 +409,9 @@ protected: LazyBool m_does_branch; bool m_is_valid; bool m_using_file_addr; - - static bool s_regex_compiled; - static ::regex_t s_regex; }; -bool InstructionLLVMC::s_regex_compiled = false; -::regex_t InstructionLLVMC::s_regex; + DisassemblerLLVMC::LLVMCDisassembler::LLVMCDisassembler (const char *triple, unsigned flavor, DisassemblerLLVMC &owner): m_is_valid(true) @@ -651,9 +641,15 @@ DisassemblerLLVMC::DisassemblerLLVMC (const ArchSpec &arch, const char *flavor_s } // Cortex-M3 devices (e.g. armv7m) can only execute thumb (T2) instructions, - // so hardcode the primary disassembler to thumb mode. + // so hardcode the primary disassembler to thumb mode. Same for Cortex-M4 (armv7em). + // + // Handle the Cortex-M0 (armv6m) the same; the ISA is a subset of the T and T32 + // instructions defined in ARMv7-A. + if (arch.GetTriple().getArch() == llvm::Triple::arm - && (arch.GetCore() == ArchSpec::Core::eCore_arm_armv7m || arch.GetCore() == ArchSpec::Core::eCore_arm_armv7em)) + && (arch.GetCore() == ArchSpec::Core::eCore_arm_armv7m + || arch.GetCore() == ArchSpec::Core::eCore_arm_armv7em + || arch.GetCore() == ArchSpec::Core::eCore_arm_armv6m)) { triple = thumb_arch.GetTriple().getTriple().c_str(); } @@ -796,7 +792,7 @@ int DisassemblerLLVMC::OpInfo (uint64_t PC, default: break; case 1: - bzero (tag_bug, sizeof(::LLVMOpInfo1)); + memset (tag_bug, 0, sizeof(::LLVMOpInfo1)); break; } return 0; |