diff options
Diffstat (limited to 'source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp')
| -rw-r--r-- | source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp b/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp index a71fca7c5c3a..99856a3684cb 100644 --- a/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp +++ b/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp @@ -17,7 +17,7 @@ #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrInfo.h" -#include "llvm/MC/MCDisassembler.h" +#include "llvm/MC/MCDisassembler/MCDisassembler.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCContext.h" @@ -1142,7 +1142,7 @@ EmulateInstructionMIPS::Emulate_SWSP (llvm::MCInst& insn) // We look for sp based non-volatile register stores. if (base == dwarf_sp_mips && nonvolatile_reg_p (src)) { - RegisterInfo reg_info_src; + RegisterInfo reg_info_src = {}; Context context; RegisterValue data_src; context.type = eContextPushRegisterOnStack; @@ -1482,56 +1482,56 @@ EmulateInstructionMIPS::Emulate_BXX_3ops_C (llvm::MCInst& insn) if (!strcasecmp (op_name, "BEQC")) { if (rs_val == rt_val) - target = pc + 4 + offset; + target = pc + offset; else target = pc + 4; } else if (!strcasecmp (op_name, "BNEC")) { if (rs_val != rt_val) - target = pc + 4 + offset; + target = pc + offset; else target = pc + 4; } else if (!strcasecmp (op_name, "BLTC")) { if (rs_val < rt_val) - target = pc + 4 + offset; + target = pc + offset; else target = pc + 4; } else if (!strcasecmp (op_name, "BGEC")) { if (rs_val >= rt_val) - target = pc + 4 + offset; + target = pc + offset; else target = pc + 4; } else if (!strcasecmp (op_name, "BLTUC")) { if (rs_val < rt_val) - target = pc + 4 + offset; + target = pc + offset; else target = pc + 4; } else if (!strcasecmp (op_name, "BGEUC")) { if ((uint32_t)rs_val >= (uint32_t)rt_val) - target = pc + 4 + offset; + target = pc + offset; else target = pc + 4; } else if (!strcasecmp (op_name, "BOVC")) { if (IsAdd64bitOverflow (rs_val, rt_val)) - target = pc + 4 + offset; + target = pc + offset; else target = pc + 4; } else if (!strcasecmp (op_name, "BNVC")) { if (!IsAdd64bitOverflow (rs_val, rt_val)) - target = pc + 4 + offset; + target = pc + offset; else target = pc + 4; } @@ -1773,42 +1773,42 @@ EmulateInstructionMIPS::Emulate_BXX_2ops_C (llvm::MCInst& insn) if (!strcasecmp (op_name, "BLTZC")) { if (rs_val < 0) - target = pc + 4 + offset; + target = pc + offset; else target = pc + 4; } else if (!strcasecmp (op_name, "BLEZC")) { if (rs_val <= 0) - target = pc + 4 + offset; + target = pc + offset; else target = pc + 4; } else if (!strcasecmp (op_name, "BGEZC")) { if (rs_val >= 0) - target = pc + 4 + offset; + target = pc + offset; else target = pc + 4; } else if (!strcasecmp (op_name, "BGTZC")) { if (rs_val > 0) - target = pc + 4 + offset; + target = pc + offset; else target = pc + 4; } else if (!strcasecmp (op_name, "BEQZC")) { if (rs_val == 0) - target = pc + 4 + offset; + target = pc + offset; else target = pc + 4; } else if (!strcasecmp (op_name, "BNEZC")) { if (rs_val != 0) - target = pc + 4 + offset; + target = pc + offset; else target = pc + 4; } @@ -2129,7 +2129,7 @@ EmulateInstructionMIPS::Emulate_BALC (llvm::MCInst& insn) if (!success) return false; - target = pc + 4 + offset; + target = pc + offset; Context context; @@ -2159,7 +2159,7 @@ EmulateInstructionMIPS::Emulate_BC (llvm::MCInst& insn) if (!success) return false; - target = pc + 4 + offset; + target = pc + offset; Context context; @@ -2603,7 +2603,7 @@ EmulateInstructionMIPS::Emulate_MSA_Branch_DF (llvm::MCInst& insn, int element_b bool success = false, branch_hit = true; int32_t target = 0; RegisterValue reg_value; - uint8_t * ptr = NULL; + const uint8_t *ptr = NULL; uint32_t wt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); int32_t offset = insn.getOperand(1).getImm(); @@ -2613,7 +2613,7 @@ EmulateInstructionMIPS::Emulate_MSA_Branch_DF (llvm::MCInst& insn, int element_b return false; if (ReadRegister (eRegisterKindDWARF, dwarf_w0_mips + wt, reg_value)) - ptr = (uint8_t *)reg_value.GetBytes(); + ptr = (const uint8_t *)reg_value.GetBytes(); else return false; @@ -2626,15 +2626,15 @@ EmulateInstructionMIPS::Emulate_MSA_Branch_DF (llvm::MCInst& insn, int element_b branch_hit = false; break; case 2: - if((*(uint16_t *)ptr == 0 && bnz) || (*(uint16_t *)ptr != 0 && !bnz)) + if ((*(const uint16_t *)ptr == 0 && bnz) || (*(const uint16_t *)ptr != 0 && !bnz)) branch_hit = false; break; case 4: - if((*(uint32_t *)ptr == 0 && bnz) || (*(uint32_t *)ptr != 0 && !bnz)) + if ((*(const uint32_t *)ptr == 0 && bnz) || (*(const uint32_t *)ptr != 0 && !bnz)) branch_hit = false; break; case 8: - if((*(uint64_t *)ptr == 0 && bnz) || (*(uint64_t *)ptr != 0 && !bnz)) + if ((*(const uint64_t *)ptr == 0 && bnz) || (*(const uint64_t *)ptr != 0 && !bnz)) branch_hit = false; break; } |