diff options
Diffstat (limited to 'source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp')
| -rw-r--r-- | source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp | 1823 |
1 files changed, 1478 insertions, 345 deletions
diff --git a/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp b/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp index 66866c73a5cb..d6485f686e2c 100644 --- a/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp +++ b/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp @@ -29,6 +29,7 @@ #include "lldb/Core/DataExtractor.h" #include "lldb/Core/Stream.h" #include "lldb/Symbol/UnwindPlan.h" +#include "lldb/Target/Target.h" #include "llvm/ADT/STLExtras.h" @@ -132,10 +133,6 @@ EmulateInstructionMIPS::EmulateInstructionMIPS (const lldb_private::ArchSpec &ar features += "+dsp,"; if (arch_flags & ArchSpec::eMIPSAse_dspr2) features += "+dspr2,"; - if (arch_flags & ArchSpec::eMIPSAse_mips16) - features += "+mips16,"; - if (arch_flags & ArchSpec::eMIPSAse_micromips) - features += "+micromips,"; m_reg_info.reset (target->createMCRegInfo (triple.getTriple())); assert (m_reg_info.get()); @@ -152,6 +149,21 @@ EmulateInstructionMIPS::EmulateInstructionMIPS (const lldb_private::ArchSpec &ar m_disasm.reset (target->createMCDisassembler (*m_subtype_info, *m_context)); assert (m_disasm.get()); + + /* Create alternate disassembler for microMIPS */ + if (arch_flags & ArchSpec::eMIPSAse_mips16) + features += "+mips16,"; + else if (arch_flags & ArchSpec::eMIPSAse_micromips) + features += "+micromips,"; + + m_alt_subtype_info.reset (target->createMCSubtargetInfo (triple.getTriple(), cpu, features)); + assert (m_alt_subtype_info.get()); + + m_alt_disasm.reset (target->createMCDisassembler (*m_alt_subtype_info, *m_context)); + assert (m_alt_disasm.get()); + + m_next_inst_size = 0; + m_use_alt_disaasm = false; } void @@ -221,41 +233,76 @@ EmulateInstructionMIPS::GetRegisterName (unsigned reg_num, bool alternate_name) { switch (reg_num) { - case gcc_dwarf_sp_mips: return "r29"; - case gcc_dwarf_r30_mips: return "r30"; - case gcc_dwarf_ra_mips: return "r31"; - case gcc_dwarf_f0_mips: return "f0"; - case gcc_dwarf_f1_mips: return "f1"; - case gcc_dwarf_f2_mips: return "f2"; - case gcc_dwarf_f3_mips: return "f3"; - case gcc_dwarf_f4_mips: return "f4"; - case gcc_dwarf_f5_mips: return "f5"; - case gcc_dwarf_f6_mips: return "f6"; - case gcc_dwarf_f7_mips: return "f7"; - case gcc_dwarf_f8_mips: return "f8"; - case gcc_dwarf_f9_mips: return "f9"; - case gcc_dwarf_f10_mips: return "f10"; - case gcc_dwarf_f11_mips: return "f11"; - case gcc_dwarf_f12_mips: return "f12"; - case gcc_dwarf_f13_mips: return "f13"; - case gcc_dwarf_f14_mips: return "f14"; - case gcc_dwarf_f15_mips: return "f15"; - case gcc_dwarf_f16_mips: return "f16"; - case gcc_dwarf_f17_mips: return "f17"; - case gcc_dwarf_f18_mips: return "f18"; - case gcc_dwarf_f19_mips: return "f19"; - case gcc_dwarf_f20_mips: return "f20"; - case gcc_dwarf_f21_mips: return "f21"; - case gcc_dwarf_f22_mips: return "f22"; - case gcc_dwarf_f23_mips: return "f23"; - case gcc_dwarf_f24_mips: return "f24"; - case gcc_dwarf_f25_mips: return "f25"; - case gcc_dwarf_f26_mips: return "f26"; - case gcc_dwarf_f27_mips: return "f27"; - case gcc_dwarf_f28_mips: return "f28"; - case gcc_dwarf_f29_mips: return "f29"; - case gcc_dwarf_f30_mips: return "f30"; - case gcc_dwarf_f31_mips: return "f31"; + case dwarf_sp_mips: return "r29"; + case dwarf_r30_mips: return "r30"; + case dwarf_ra_mips: return "r31"; + case dwarf_f0_mips: return "f0"; + case dwarf_f1_mips: return "f1"; + case dwarf_f2_mips: return "f2"; + case dwarf_f3_mips: return "f3"; + case dwarf_f4_mips: return "f4"; + case dwarf_f5_mips: return "f5"; + case dwarf_f6_mips: return "f6"; + case dwarf_f7_mips: return "f7"; + case dwarf_f8_mips: return "f8"; + case dwarf_f9_mips: return "f9"; + case dwarf_f10_mips: return "f10"; + case dwarf_f11_mips: return "f11"; + case dwarf_f12_mips: return "f12"; + case dwarf_f13_mips: return "f13"; + case dwarf_f14_mips: return "f14"; + case dwarf_f15_mips: return "f15"; + case dwarf_f16_mips: return "f16"; + case dwarf_f17_mips: return "f17"; + case dwarf_f18_mips: return "f18"; + case dwarf_f19_mips: return "f19"; + case dwarf_f20_mips: return "f20"; + case dwarf_f21_mips: return "f21"; + case dwarf_f22_mips: return "f22"; + case dwarf_f23_mips: return "f23"; + case dwarf_f24_mips: return "f24"; + case dwarf_f25_mips: return "f25"; + case dwarf_f26_mips: return "f26"; + case dwarf_f27_mips: return "f27"; + case dwarf_f28_mips: return "f28"; + case dwarf_f29_mips: return "f29"; + case dwarf_f30_mips: return "f30"; + case dwarf_f31_mips: return "f31"; + case dwarf_w0_mips: return "w0"; + case dwarf_w1_mips: return "w1"; + case dwarf_w2_mips: return "w2"; + case dwarf_w3_mips: return "w3"; + case dwarf_w4_mips: return "w4"; + case dwarf_w5_mips: return "w5"; + case dwarf_w6_mips: return "w6"; + case dwarf_w7_mips: return "w7"; + case dwarf_w8_mips: return "w8"; + case dwarf_w9_mips: return "w9"; + case dwarf_w10_mips: return "w10"; + case dwarf_w11_mips: return "w11"; + case dwarf_w12_mips: return "w12"; + case dwarf_w13_mips: return "w13"; + case dwarf_w14_mips: return "w14"; + case dwarf_w15_mips: return "w15"; + case dwarf_w16_mips: return "w16"; + case dwarf_w17_mips: return "w17"; + case dwarf_w18_mips: return "w18"; + case dwarf_w19_mips: return "w19"; + case dwarf_w20_mips: return "w20"; + case dwarf_w21_mips: return "w21"; + case dwarf_w22_mips: return "w22"; + case dwarf_w23_mips: return "w23"; + case dwarf_w24_mips: return "w24"; + case dwarf_w25_mips: return "w25"; + case dwarf_w26_mips: return "w26"; + case dwarf_w27_mips: return "w27"; + case dwarf_w28_mips: return "w28"; + case dwarf_w29_mips: return "w29"; + case dwarf_w30_mips: return "w30"; + case dwarf_w31_mips: return "w31"; + case dwarf_mir_mips: return "mir"; + case dwarf_mcsr_mips: return "mcsr"; + case dwarf_config5_mips: return "config5"; default: break; } @@ -264,78 +311,113 @@ EmulateInstructionMIPS::GetRegisterName (unsigned reg_num, bool alternate_name) switch (reg_num) { - case gcc_dwarf_zero_mips: return "r0"; - case gcc_dwarf_r1_mips: return "r1"; - case gcc_dwarf_r2_mips: return "r2"; - case gcc_dwarf_r3_mips: return "r3"; - case gcc_dwarf_r4_mips: return "r4"; - case gcc_dwarf_r5_mips: return "r5"; - case gcc_dwarf_r6_mips: return "r6"; - case gcc_dwarf_r7_mips: return "r7"; - case gcc_dwarf_r8_mips: return "r8"; - case gcc_dwarf_r9_mips: return "r9"; - case gcc_dwarf_r10_mips: return "r10"; - case gcc_dwarf_r11_mips: return "r11"; - case gcc_dwarf_r12_mips: return "r12"; - case gcc_dwarf_r13_mips: return "r13"; - case gcc_dwarf_r14_mips: return "r14"; - case gcc_dwarf_r15_mips: return "r15"; - case gcc_dwarf_r16_mips: return "r16"; - case gcc_dwarf_r17_mips: return "r17"; - case gcc_dwarf_r18_mips: return "r18"; - case gcc_dwarf_r19_mips: return "r19"; - case gcc_dwarf_r20_mips: return "r20"; - case gcc_dwarf_r21_mips: return "r21"; - case gcc_dwarf_r22_mips: return "r22"; - case gcc_dwarf_r23_mips: return "r23"; - case gcc_dwarf_r24_mips: return "r24"; - case gcc_dwarf_r25_mips: return "r25"; - case gcc_dwarf_r26_mips: return "r26"; - case gcc_dwarf_r27_mips: return "r27"; - case gcc_dwarf_gp_mips: return "gp"; - case gcc_dwarf_sp_mips: return "sp"; - case gcc_dwarf_r30_mips: return "fp"; - case gcc_dwarf_ra_mips: return "ra"; - case gcc_dwarf_sr_mips: return "sr"; - case gcc_dwarf_lo_mips: return "lo"; - case gcc_dwarf_hi_mips: return "hi"; - case gcc_dwarf_bad_mips: return "bad"; - case gcc_dwarf_cause_mips: return "cause"; - case gcc_dwarf_pc_mips: return "pc"; - case gcc_dwarf_f0_mips: return "f0"; - case gcc_dwarf_f1_mips: return "f1"; - case gcc_dwarf_f2_mips: return "f2"; - case gcc_dwarf_f3_mips: return "f3"; - case gcc_dwarf_f4_mips: return "f4"; - case gcc_dwarf_f5_mips: return "f5"; - case gcc_dwarf_f6_mips: return "f6"; - case gcc_dwarf_f7_mips: return "f7"; - case gcc_dwarf_f8_mips: return "f8"; - case gcc_dwarf_f9_mips: return "f9"; - case gcc_dwarf_f10_mips: return "f10"; - case gcc_dwarf_f11_mips: return "f11"; - case gcc_dwarf_f12_mips: return "f12"; - case gcc_dwarf_f13_mips: return "f13"; - case gcc_dwarf_f14_mips: return "f14"; - case gcc_dwarf_f15_mips: return "f15"; - case gcc_dwarf_f16_mips: return "f16"; - case gcc_dwarf_f17_mips: return "f17"; - case gcc_dwarf_f18_mips: return "f18"; - case gcc_dwarf_f19_mips: return "f19"; - case gcc_dwarf_f20_mips: return "f20"; - case gcc_dwarf_f21_mips: return "f21"; - case gcc_dwarf_f22_mips: return "f22"; - case gcc_dwarf_f23_mips: return "f23"; - case gcc_dwarf_f24_mips: return "f24"; - case gcc_dwarf_f25_mips: return "f25"; - case gcc_dwarf_f26_mips: return "f26"; - case gcc_dwarf_f27_mips: return "f27"; - case gcc_dwarf_f28_mips: return "f28"; - case gcc_dwarf_f29_mips: return "f29"; - case gcc_dwarf_f30_mips: return "f30"; - case gcc_dwarf_f31_mips: return "f31"; - case gcc_dwarf_fcsr_mips: return "fcsr"; - case gcc_dwarf_fir_mips: return "fir"; + case dwarf_zero_mips: return "r0"; + case dwarf_r1_mips: return "r1"; + case dwarf_r2_mips: return "r2"; + case dwarf_r3_mips: return "r3"; + case dwarf_r4_mips: return "r4"; + case dwarf_r5_mips: return "r5"; + case dwarf_r6_mips: return "r6"; + case dwarf_r7_mips: return "r7"; + case dwarf_r8_mips: return "r8"; + case dwarf_r9_mips: return "r9"; + case dwarf_r10_mips: return "r10"; + case dwarf_r11_mips: return "r11"; + case dwarf_r12_mips: return "r12"; + case dwarf_r13_mips: return "r13"; + case dwarf_r14_mips: return "r14"; + case dwarf_r15_mips: return "r15"; + case dwarf_r16_mips: return "r16"; + case dwarf_r17_mips: return "r17"; + case dwarf_r18_mips: return "r18"; + case dwarf_r19_mips: return "r19"; + case dwarf_r20_mips: return "r20"; + case dwarf_r21_mips: return "r21"; + case dwarf_r22_mips: return "r22"; + case dwarf_r23_mips: return "r23"; + case dwarf_r24_mips: return "r24"; + case dwarf_r25_mips: return "r25"; + case dwarf_r26_mips: return "r26"; + case dwarf_r27_mips: return "r27"; + case dwarf_gp_mips: return "gp"; + case dwarf_sp_mips: return "sp"; + case dwarf_r30_mips: return "fp"; + case dwarf_ra_mips: return "ra"; + case dwarf_sr_mips: return "sr"; + case dwarf_lo_mips: return "lo"; + case dwarf_hi_mips: return "hi"; + case dwarf_bad_mips: return "bad"; + case dwarf_cause_mips: return "cause"; + case dwarf_pc_mips: return "pc"; + case dwarf_f0_mips: return "f0"; + case dwarf_f1_mips: return "f1"; + case dwarf_f2_mips: return "f2"; + case dwarf_f3_mips: return "f3"; + case dwarf_f4_mips: return "f4"; + case dwarf_f5_mips: return "f5"; + case dwarf_f6_mips: return "f6"; + case dwarf_f7_mips: return "f7"; + case dwarf_f8_mips: return "f8"; + case dwarf_f9_mips: return "f9"; + case dwarf_f10_mips: return "f10"; + case dwarf_f11_mips: return "f11"; + case dwarf_f12_mips: return "f12"; + case dwarf_f13_mips: return "f13"; + case dwarf_f14_mips: return "f14"; + case dwarf_f15_mips: return "f15"; + case dwarf_f16_mips: return "f16"; + case dwarf_f17_mips: return "f17"; + case dwarf_f18_mips: return "f18"; + case dwarf_f19_mips: return "f19"; + case dwarf_f20_mips: return "f20"; + case dwarf_f21_mips: return "f21"; + case dwarf_f22_mips: return "f22"; + case dwarf_f23_mips: return "f23"; + case dwarf_f24_mips: return "f24"; + case dwarf_f25_mips: return "f25"; + case dwarf_f26_mips: return "f26"; + case dwarf_f27_mips: return "f27"; + case dwarf_f28_mips: return "f28"; + case dwarf_f29_mips: return "f29"; + case dwarf_f30_mips: return "f30"; + case dwarf_f31_mips: return "f31"; + case dwarf_fcsr_mips: return "fcsr"; + case dwarf_fir_mips: return "fir"; + case dwarf_w0_mips: return "w0"; + case dwarf_w1_mips: return "w1"; + case dwarf_w2_mips: return "w2"; + case dwarf_w3_mips: return "w3"; + case dwarf_w4_mips: return "w4"; + case dwarf_w5_mips: return "w5"; + case dwarf_w6_mips: return "w6"; + case dwarf_w7_mips: return "w7"; + case dwarf_w8_mips: return "w8"; + case dwarf_w9_mips: return "w9"; + case dwarf_w10_mips: return "w10"; + case dwarf_w11_mips: return "w11"; + case dwarf_w12_mips: return "w12"; + case dwarf_w13_mips: return "w13"; + case dwarf_w14_mips: return "w14"; + case dwarf_w15_mips: return "w15"; + case dwarf_w16_mips: return "w16"; + case dwarf_w17_mips: return "w17"; + case dwarf_w18_mips: return "w18"; + case dwarf_w19_mips: return "w19"; + case dwarf_w20_mips: return "w20"; + case dwarf_w21_mips: return "w21"; + case dwarf_w22_mips: return "w22"; + case dwarf_w23_mips: return "w23"; + case dwarf_w24_mips: return "w24"; + case dwarf_w25_mips: return "w25"; + case dwarf_w26_mips: return "w26"; + case dwarf_w27_mips: return "w27"; + case dwarf_w28_mips: return "w28"; + case dwarf_w29_mips: return "w29"; + case dwarf_w30_mips: return "w30"; + case dwarf_w31_mips: return "w31"; + case dwarf_mcsr_mips: return "mcsr"; + case dwarf_mir_mips: return "mir"; + case dwarf_config5_mips: return "config5"; } return nullptr; } @@ -347,11 +429,11 @@ EmulateInstructionMIPS::GetRegisterInfo (RegisterKind reg_kind, uint32_t reg_num { switch (reg_num) { - case LLDB_REGNUM_GENERIC_PC: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_pc_mips; break; - case LLDB_REGNUM_GENERIC_SP: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_sp_mips; break; - case LLDB_REGNUM_GENERIC_FP: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_r30_mips; break; - case LLDB_REGNUM_GENERIC_RA: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_ra_mips; break; - case LLDB_REGNUM_GENERIC_FLAGS: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_sr_mips; break; + case LLDB_REGNUM_GENERIC_PC: reg_kind = eRegisterKindDWARF; reg_num = dwarf_pc_mips; break; + case LLDB_REGNUM_GENERIC_SP: reg_kind = eRegisterKindDWARF; reg_num = dwarf_sp_mips; break; + case LLDB_REGNUM_GENERIC_FP: reg_kind = eRegisterKindDWARF; reg_num = dwarf_r30_mips; break; + case LLDB_REGNUM_GENERIC_RA: reg_kind = eRegisterKindDWARF; reg_num = dwarf_ra_mips; break; + case LLDB_REGNUM_GENERIC_FLAGS: reg_kind = eRegisterKindDWARF; reg_num = dwarf_sr_mips; break; default: return false; } @@ -362,18 +444,24 @@ EmulateInstructionMIPS::GetRegisterInfo (RegisterKind reg_kind, uint32_t reg_num ::memset (®_info, 0, sizeof(RegisterInfo)); ::memset (reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds)); - if (reg_num == gcc_dwarf_sr_mips || reg_num == gcc_dwarf_fcsr_mips || reg_num == gcc_dwarf_fir_mips) + if (reg_num == dwarf_sr_mips || reg_num == dwarf_fcsr_mips || reg_num == dwarf_fir_mips || reg_num == dwarf_mcsr_mips || reg_num == dwarf_mir_mips || reg_num == dwarf_config5_mips) { reg_info.byte_size = 4; reg_info.format = eFormatHex; reg_info.encoding = eEncodingUint; } - else if ((int)reg_num >= gcc_dwarf_zero_mips && (int)reg_num <= gcc_dwarf_f31_mips) + else if ((int)reg_num >= dwarf_zero_mips && (int)reg_num <= dwarf_f31_mips) { reg_info.byte_size = 4; reg_info.format = eFormatHex; reg_info.encoding = eEncodingUint; } + else if ((int)reg_num >= dwarf_w0_mips && (int)reg_num <= dwarf_w31_mips) + { + reg_info.byte_size = 16; + reg_info.format = eFormatVectorOfUInt8; + reg_info.encoding = eEncodingVector; + } else { return false; @@ -385,11 +473,11 @@ EmulateInstructionMIPS::GetRegisterInfo (RegisterKind reg_kind, uint32_t reg_num switch (reg_num) { - case gcc_dwarf_r30_mips: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FP; break; - case gcc_dwarf_ra_mips: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_RA; break; - case gcc_dwarf_sp_mips: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_SP; break; - case gcc_dwarf_pc_mips: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_PC; break; - case gcc_dwarf_sr_mips: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FLAGS; break; + case dwarf_r30_mips: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FP; break; + case dwarf_ra_mips: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_RA; break; + case dwarf_sp_mips: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_SP; break; + case dwarf_pc_mips: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_PC; break; + case dwarf_sr_mips: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FLAGS; break; default: break; } return true; @@ -409,6 +497,96 @@ EmulateInstructionMIPS::GetOpcodeForInstruction (const char *op_name) { "ADDiu", &EmulateInstructionMIPS::Emulate_ADDiu, "ADDIU rt,rs,immediate" }, { "SW", &EmulateInstructionMIPS::Emulate_SW, "SW rt,offset(rs)" }, { "LW", &EmulateInstructionMIPS::Emulate_LW, "LW rt,offset(base)" }, + //---------------------------------------------------------------------- + // MicroMIPS Prologue/Epilogue instructions + //---------------------------------------------------------------------- + { "ADDIUSP_MM", &EmulateInstructionMIPS::Emulate_ADDIUSP, "ADDIU immediate" }, + { "ADDIUS5_MM", &EmulateInstructionMIPS::Emulate_ADDIUS5, "ADDIUS5 rd,immediate" }, + { "SWSP_MM", &EmulateInstructionMIPS::Emulate_SWSP, "SWSP rt,offset(sp)" }, + { "SWM16_MM", &EmulateInstructionMIPS::Emulate_SWM16_32, "SWM16 reglist,offset(sp)" }, + { "SWM32_MM", &EmulateInstructionMIPS::Emulate_SWM16_32, "SWM32 reglist,offset(base)" }, + { "SWP_MM", &EmulateInstructionMIPS::Emulate_SWM16_32, "SWP rs1,offset(base)" }, + { "LWSP_MM", &EmulateInstructionMIPS::Emulate_LWSP, "LWSP rt,offset(sp)" }, + { "LWM16_MM", &EmulateInstructionMIPS::Emulate_LWM16_32, "LWM16 reglist,offset(sp)" }, + { "LWM32_MM", &EmulateInstructionMIPS::Emulate_LWM16_32, "LWM32 reglist,offset(base)" }, + { "LWP_MM", &EmulateInstructionMIPS::Emulate_LWM16_32, "LWP rd,offset(base)" }, + { "JRADDIUSP", &EmulateInstructionMIPS::Emulate_JRADDIUSP, "JRADDIUSP immediate" }, + //---------------------------------------------------------------------- + + // Load/Store instructions + //---------------------------------------------------------------------- + /* Following list of emulated instructions are required by implementation of hardware watchpoint + for MIPS in lldb. As we just need the address accessed by instructions, we have generalised + all these instructions in 2 functions depending on their addressing modes */ + + { "LB", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LB rt, offset(base)" }, + { "LBE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LBE rt, offset(base)" }, + { "LBU", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LBU rt, offset(base)" }, + { "LBUE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LBUE rt, offset(base)" }, + { "LDC1", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LDC1 ft, offset(base)" }, + { "LD", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LD rt, offset(base)" }, + { "LDL", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LDL rt, offset(base)" }, + { "LDR", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LDR rt, offset(base)" }, + { "LLD", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LLD rt, offset(base)" }, + { "LDC2", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LDC2 rt, offset(base)" }, + { "LDXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg, "LDXC1 fd, index (base)" }, + { "LH", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LH rt, offset(base)" }, + { "LHE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LHE rt, offset(base)" }, + { "LHU", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LHU rt, offset(base)" }, + { "LHUE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LHUE rt, offset(base)" }, + { "LL", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LL rt, offset(base)" }, + { "LLE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LLE rt, offset(base)" }, + { "LUXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg, "LUXC1 fd, index (base)" }, + { "LW", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LW rt, offset(base)" }, + { "LWC1", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LWC1 ft, offset(base)" }, + { "LWC2", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LWC2 rt, offset(base)" }, + { "LWE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LWE rt, offset(base)" }, + { "LWL", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LWL rt, offset(base)" }, + { "LWLE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LWLE rt, offset(base)" }, + { "LWR", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LWR rt, offset(base)" }, + { "LWRE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LWRE rt, offset(base)" }, + { "LWXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg, "LWXC1 fd, index (base)" }, + { "LLX", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LLX rt, offset(base)" }, + { "LLXE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LLXE rt, offset(base)" }, + { "LLDX", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LLDX rt, offset(base)" }, + + { "SB", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SB rt, offset(base)" }, + { "SBE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SBE rt, offset(base)" }, + { "SC", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SC rt, offset(base)" }, + { "SCE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SCE rt, offset(base)" }, + { "SCD", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SCD rt, offset(base)" }, + { "SD", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SD rt, offset(base)" }, + { "SDL", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SDL rt, offset(base)" }, + { "SDR", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SDR rt, offset(base)" }, + { "SDC1", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SDC1 ft, offset(base)" }, + { "SDC2", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SDC2 rt, offset(base)" }, + { "SDXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg, "SDXC1 fs, index(base)" }, + { "SH", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SH rt, offset(base)" }, + { "SHE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SHE rt, offset(base)" }, + { "SUXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg, "SUXC1 fs, index (base)" }, + { "SWC1", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SWC1 ft, offset(base)" }, + { "SWC2", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SWC2 rt, offset(base)" }, + { "SWE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SWE rt, offset(base)" }, + { "SWL", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SWL rt, offset(base)" }, + { "SWLE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SWLE rt, offset(base)" }, + { "SWR", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SWR rt, offset(base)" }, + { "SWRE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SWRE rt, offset(base)" }, + { "SWXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg, "SWXC1 fs, index (base)" }, + { "SCX", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SCX rt, offset(base)" }, + { "SCXE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SCXE rt, offset(base)" }, + { "SCDX", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SCDX rt, offset(base)" }, + + //---------------------------------------------------------------------- + // MicroMIPS Load/Store instructions + //---------------------------------------------------------------------- + { "LBU16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LBU16 rt, decoded_offset(base)" }, + { "LHU16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LHU16 rt, left_shifted_offset(base)" }, + { "LW16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LW16 rt, left_shifted_offset(base)" }, + { "LWGP_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LWGP rt, left_shifted_offset(gp)" }, + { "SH16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SH16 rt, left_shifted_offset(base)" }, + { "SW16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SW16 rt, left_shifted_offset(base)" }, + { "SW_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SWSP rt, left_shifted_offset(base)" }, + { "SB16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SB16 rt, offset(base)" }, //---------------------------------------------------------------------- // Branch instructions @@ -471,6 +649,34 @@ EmulateInstructionMIPS::GetOpcodeForInstruction (const char *op_name) { "BC1ANY2T", &EmulateInstructionMIPS::Emulate_BC1ANY2T, "BC1ANY2T cc, offset" }, { "BC1ANY4F", &EmulateInstructionMIPS::Emulate_BC1ANY4F, "BC1ANY4F cc, offset" }, { "BC1ANY4T", &EmulateInstructionMIPS::Emulate_BC1ANY4T, "BC1ANY4T cc, offset" }, + { "BNZ_B", &EmulateInstructionMIPS::Emulate_BNZB, "BNZ.b wt,s16" }, + { "BNZ_H", &EmulateInstructionMIPS::Emulate_BNZH, "BNZ.h wt,s16" }, + { "BNZ_W", &EmulateInstructionMIPS::Emulate_BNZW, "BNZ.w wt,s16" }, + { "BNZ_D", &EmulateInstructionMIPS::Emulate_BNZD, "BNZ.d wt,s16" }, + { "BZ_B", &EmulateInstructionMIPS::Emulate_BZB, "BZ.b wt,s16" }, + { "BZ_H", &EmulateInstructionMIPS::Emulate_BZH, "BZ.h wt,s16" }, + { "BZ_W", &EmulateInstructionMIPS::Emulate_BZW, "BZ.w wt,s16" }, + { "BZ_D", &EmulateInstructionMIPS::Emulate_BZD, "BZ.d wt,s16" }, + { "BNZ_V", &EmulateInstructionMIPS::Emulate_BNZV, "BNZ.V wt,s16" }, + { "BZ_V", &EmulateInstructionMIPS::Emulate_BZV, "BZ.V wt,s16" }, + + //---------------------------------------------------------------------- + // MicroMIPS Branch instructions + //---------------------------------------------------------------------- + { "B16_MM", &EmulateInstructionMIPS::Emulate_B16_MM, "B16 offset" }, + { "BEQZ16_MM", &EmulateInstructionMIPS::Emulate_Branch_MM, "BEQZ16 rs, offset" }, + { "BNEZ16_MM", &EmulateInstructionMIPS::Emulate_Branch_MM, "BNEZ16 rs, offset" }, + { "BEQZC_MM", &EmulateInstructionMIPS::Emulate_Branch_MM, "BEQZC rs, offset" }, + { "BNEZC_MM", &EmulateInstructionMIPS::Emulate_Branch_MM, "BNEZC rs, offset" }, + { "BGEZALS_MM", &EmulateInstructionMIPS::Emulate_Branch_MM, "BGEZALS rs, offset" }, + { "BLTZALS_MM", &EmulateInstructionMIPS::Emulate_Branch_MM, "BLTZALS rs, offset" }, + { "JALR16_MM", &EmulateInstructionMIPS::Emulate_JALRx16_MM, "JALR16 rs" }, + { "JALRS16_MM", &EmulateInstructionMIPS::Emulate_JALRx16_MM, "JALRS16 rs" }, + { "JR16_MM", &EmulateInstructionMIPS::Emulate_JR, "JR16 rs rs" }, + { "JRC16_MM", &EmulateInstructionMIPS::Emulate_JR, "JRC16 rs rs" }, + { "JALS_MM", &EmulateInstructionMIPS::Emulate_JALx, "JALS target" }, + { "JALX_MM", &EmulateInstructionMIPS::Emulate_JALx, "JALX target" }, + { "JALRS_MM", &EmulateInstructionMIPS::Emulate_JALRS, "JALRS rt, rs" }, }; static const size_t k_num_mips_opcodes = llvm::array_lengthof(g_opcodes); @@ -484,6 +690,76 @@ EmulateInstructionMIPS::GetOpcodeForInstruction (const char *op_name) return NULL; } +uint32_t +EmulateInstructionMIPS::GetSizeOfInstruction (lldb_private::DataExtractor& data, uint64_t inst_addr) +{ + uint64_t next_inst_size = 0; + llvm::MCInst mc_insn; + llvm::MCDisassembler::DecodeStatus decode_status; + llvm::ArrayRef<uint8_t> raw_insn (data.GetDataStart(), data.GetByteSize()); + + if (m_use_alt_disaasm) + decode_status = m_alt_disasm->getInstruction (mc_insn, next_inst_size, raw_insn, inst_addr, llvm::nulls(), llvm::nulls()); + else + decode_status = m_disasm->getInstruction (mc_insn, next_inst_size, raw_insn, inst_addr, llvm::nulls(), llvm::nulls()); + + if (decode_status != llvm::MCDisassembler::Success) + return false; + + return m_insn_info->get(mc_insn.getOpcode()).getSize(); +} + +bool +EmulateInstructionMIPS::SetInstruction (const Opcode &insn_opcode, const Address &inst_addr, Target *target) +{ + m_use_alt_disaasm = false; + + if (EmulateInstruction::SetInstruction (insn_opcode, inst_addr, target)) + { + if (inst_addr.GetAddressClass() == eAddressClassCodeAlternateISA) + { + Error error; + lldb::addr_t load_addr = LLDB_INVALID_ADDRESS; + + /* + * The address belongs to microMIPS function. To find the size of + * next instruction use microMIPS disassembler. + */ + m_use_alt_disaasm = true; + + uint32_t current_inst_size = insn_opcode.GetByteSize(); + uint8_t buf[sizeof(uint32_t)]; + uint64_t next_inst_addr = (m_addr & (~1ull)) + current_inst_size; + Address next_addr (next_inst_addr); + + const size_t bytes_read = target->ReadMemory (next_addr, /* Address of next instruction */ + true, /* prefer_file_cache */ + buf, + sizeof(uint32_t), + error, + &load_addr); + + if (bytes_read == 0) + return true; + + DataExtractor data (buf, sizeof(uint32_t), GetByteOrder(), GetAddressByteSize()); + m_next_inst_size = GetSizeOfInstruction (data, next_inst_addr); + return true; + } + else + { + /* + * If the address class is not eAddressClassCodeAlternateISA then + * the function is not microMIPS. In this case instruction size is + * always 4 bytes. + */ + m_next_inst_size = 4; + return true; + } + } + return false; +} + bool EmulateInstructionMIPS::ReadInstruction () { @@ -514,7 +790,11 @@ EmulateInstructionMIPS::EvaluateInstruction (uint32_t evaluate_options) { llvm::MCDisassembler::DecodeStatus decode_status; llvm::ArrayRef<uint8_t> raw_insn (data.GetDataStart(), data.GetByteSize()); - decode_status = m_disasm->getInstruction (mc_insn, insn_size, raw_insn, m_addr, llvm::nulls(), llvm::nulls()); + if (m_use_alt_disaasm) + decode_status = m_alt_disasm->getInstruction (mc_insn, insn_size, raw_insn, m_addr, llvm::nulls(), llvm::nulls()); + else + decode_status = m_disasm->getInstruction (mc_insn, insn_size, raw_insn, m_addr, llvm::nulls(), llvm::nulls()); + if (decode_status != llvm::MCDisassembler::Success) return false; } @@ -542,7 +822,7 @@ EmulateInstructionMIPS::EvaluateInstruction (uint32_t evaluate_options) if (auto_advance_pc) { - old_pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + old_pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; } @@ -554,7 +834,7 @@ EmulateInstructionMIPS::EvaluateInstruction (uint32_t evaluate_options) if (auto_advance_pc) { - new_pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + new_pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; @@ -563,7 +843,7 @@ EmulateInstructionMIPS::EvaluateInstruction (uint32_t evaluate_options) { new_pc += 4; Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, new_pc)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, new_pc)) return false; } } @@ -581,10 +861,10 @@ EmulateInstructionMIPS::CreateFunctionEntryUnwind (UnwindPlan &unwind_plan) const bool can_replace = false; // Our previous Call Frame Address is the stack pointer - row->GetCFAValue().SetIsRegisterPlusOffset(gcc_dwarf_sp_mips, 0); + row->GetCFAValue().SetIsRegisterPlusOffset(dwarf_sp_mips, 0); // Our previous PC is in the RA - row->SetRegisterLocationToRegister(gcc_dwarf_pc_mips, gcc_dwarf_ra_mips, can_replace); + row->SetRegisterLocationToRegister(dwarf_pc_mips, dwarf_ra_mips, can_replace); unwind_plan.AppendRow (row); @@ -592,6 +872,7 @@ EmulateInstructionMIPS::CreateFunctionEntryUnwind (UnwindPlan &unwind_plan) unwind_plan.SetSourceName ("EmulateInstructionMIPS"); unwind_plan.SetSourcedFromCompiler (eLazyBoolNo); unwind_plan.SetUnwindPlanValidAtAllInstructions (eLazyBoolYes); + unwind_plan.SetReturnAddressRegister (dwarf_ra_mips); return true; } @@ -601,18 +882,18 @@ EmulateInstructionMIPS::nonvolatile_reg_p (uint32_t regnum) { switch (regnum) { - case gcc_dwarf_r16_mips: - case gcc_dwarf_r17_mips: - case gcc_dwarf_r18_mips: - case gcc_dwarf_r19_mips: - case gcc_dwarf_r20_mips: - case gcc_dwarf_r21_mips: - case gcc_dwarf_r22_mips: - case gcc_dwarf_r23_mips: - case gcc_dwarf_gp_mips: - case gcc_dwarf_sp_mips: - case gcc_dwarf_r30_mips: - case gcc_dwarf_ra_mips: + case dwarf_r16_mips: + case dwarf_r17_mips: + case dwarf_r18_mips: + case dwarf_r19_mips: + case dwarf_r20_mips: + case dwarf_r21_mips: + case dwarf_r22_mips: + case dwarf_r23_mips: + case dwarf_gp_mips: + case dwarf_sp_mips: + case dwarf_r30_mips: + case dwarf_ra_mips: return true; default: return false; @@ -633,10 +914,10 @@ EmulateInstructionMIPS::Emulate_ADDiu (llvm::MCInst& insn) src = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); /* Check if this is addiu sp,<src>,imm16 */ - if (dst == gcc_dwarf_sp_mips) + if (dst == dwarf_sp_mips) { /* read <src> register */ - uint64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + src, 0, &success); + uint64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + src, 0, &success); if (!success) return false; @@ -644,13 +925,13 @@ EmulateInstructionMIPS::Emulate_ADDiu (llvm::MCInst& insn) Context context; RegisterInfo reg_info_sp; - if (GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_sp_mips, reg_info_sp)) + if (GetRegisterInfo (eRegisterKindDWARF, dwarf_sp_mips, reg_info_sp)) context.SetRegisterPlusOffset (reg_info_sp, imm); /* We are allocating bytes on stack */ context.type = eContextAdjustStackPointer; - WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_sp_mips, result); + WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_sp_mips, result); } return true; @@ -663,30 +944,206 @@ EmulateInstructionMIPS::Emulate_SW (llvm::MCInst& insn) uint32_t imm16 = insn.getOperand(2).getImm(); uint32_t imm = SignedBits(imm16, 15, 0); uint32_t src, base; + int32_t address; + Context bad_vaddr_context; + + RegisterInfo reg_info_base; src = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + base, reg_info_base)) + return false; + + /* read base register */ + address = (int32_t)ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success); + if (!success) + return false; + + /* destination address */ + address = address + imm; + + /* Set the bad_vaddr register with base address used in the instruction */ + bad_vaddr_context.type = eContextInvalid; + WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips, address); + /* We look for sp based non-volatile register stores */ - if (base == gcc_dwarf_sp_mips && nonvolatile_reg_p (src)) + if (base == dwarf_sp_mips && nonvolatile_reg_p (src)) + { + + RegisterInfo reg_info_src; + + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + src, reg_info_src)) + return false; + + Context context; + RegisterValue data_src; + context.type = eContextPushRegisterOnStack; + context.SetRegisterToRegisterPlusOffset (reg_info_src, reg_info_base, 0); + + uint8_t buffer [RegisterValue::kMaxRegisterByteSize]; + Error error; + + if (!ReadRegister (®_info_base, data_src)) + return false; + + if (data_src.GetAsMemoryData (®_info_src, buffer, reg_info_src.byte_size, eByteOrderLittle, error) == 0) + return false; + + if (!WriteMemory (context, address, buffer, reg_info_src.byte_size)) + return false; + + return true; + } + + return false; +} + +bool +EmulateInstructionMIPS::Emulate_LW (llvm::MCInst& insn) +{ + bool success =false; + uint32_t src, base; + int32_t imm, address; + Context bad_vaddr_context; + + src = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); + base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); + imm = insn.getOperand(2).getImm(); + + RegisterInfo reg_info_base; + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + base, reg_info_base)) + return false; + + /* read base register */ + address = (int32_t)ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success); + if (!success) + return false; + + /* destination address */ + address = address + imm; + + /* Set the bad_vaddr register with base address used in the instruction */ + bad_vaddr_context.type = eContextInvalid; + WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips, address); + + if (base == dwarf_sp_mips && nonvolatile_reg_p (src)) { - uint32_t address; - RegisterInfo reg_info_base; + RegisterValue data_src; RegisterInfo reg_info_src; - if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips + base, reg_info_base) - || !GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips + src, reg_info_src)) + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + src, reg_info_src)) return false; - /* read SP */ - address = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + base, 0, &success); + Context context; + context.type = eContextPopRegisterOffStack; + context.SetAddress (address); + + if (!WriteRegister (context, ®_info_src, data_src)) + return false; + + return true; + } + + return false; +} + +bool +EmulateInstructionMIPS::Emulate_ADDIUSP (llvm::MCInst& insn) +{ + bool success = false; + const uint32_t imm9 = insn.getOperand(0).getImm(); + uint64_t result; + + // This instruction operates implicitly on stack pointer, so read <sp> register. + uint64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_sp_mips, 0, &success); + if (!success) + return false; + + result = src_opd_val + imm9; + + Context context; + RegisterInfo reg_info_sp; + if (GetRegisterInfo (eRegisterKindDWARF, dwarf_sp_mips, reg_info_sp)) + context.SetRegisterPlusOffset (reg_info_sp, imm9); + + // We are adjusting the stack. + context.type = eContextAdjustStackPointer; + + WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_sp_mips, result); + return true; +} + +bool +EmulateInstructionMIPS::Emulate_ADDIUS5 (llvm::MCInst& insn) +{ + bool success = false; + uint32_t base; + const uint32_t imm4 = insn.getOperand(2).getImm(); + uint64_t result; + + // The source and destination register is same for this instruction. + base = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); + + // We are looking for stack adjustment only + if (base == dwarf_sp_mips) + { + // Read stack pointer register + uint64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success); if (!success) return false; - /* destination address */ - address = address + imm; + result = src_opd_val + imm4; Context context; + RegisterInfo reg_info_sp; + if (GetRegisterInfo (eRegisterKindDWARF, dwarf_sp_mips, reg_info_sp)) + context.SetRegisterPlusOffset (reg_info_sp, imm4); + + // We are adjusting the stack. + context.type = eContextAdjustStackPointer; + + WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_sp_mips, result); + } + + return true; +} + +bool +EmulateInstructionMIPS::Emulate_SWSP (llvm::MCInst& insn) +{ + bool success = false; + uint32_t imm5 = insn.getOperand(2).getImm(); + uint32_t src, base; + Context bad_vaddr_context; + uint32_t address; + + src = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); + base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); + + RegisterInfo reg_info_base; + + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + base, reg_info_base)) + return false; + + // read base register + address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success); + if (!success) + return false; + + // destination address + address = address + imm5; + + // We use bad_vaddr_context to store base address which is used by H/W watchpoint + // Set the bad_vaddr register with base address used in the instruction + bad_vaddr_context.type = eContextInvalid; + WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips, address); + + // We look for sp based non-volatile register stores. + if (base == dwarf_sp_mips && nonvolatile_reg_p (src)) + { + RegisterInfo reg_info_src; + Context context; RegisterValue data_src; context.type = eContextPushRegisterOnStack; context.SetRegisterToRegisterPlusOffset (reg_info_src, reg_info_base, 0); @@ -709,24 +1166,118 @@ EmulateInstructionMIPS::Emulate_SW (llvm::MCInst& insn) return false; } +/* Emulate SWM16,SWM32 and SWP instruction. + + SWM16 always has stack pointer as a base register (but it is still available in MCInst as an operand). + SWM32 and SWP can have base register other than stack pointer. +*/ bool -EmulateInstructionMIPS::Emulate_LW (llvm::MCInst& insn) +EmulateInstructionMIPS::Emulate_SWM16_32 (llvm::MCInst& insn) { + bool success = false; uint32_t src, base; + uint32_t num_operands = insn.getNumOperands(); // No of operands vary based on no of regs to store. - src = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); - base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); + // Base register is second last operand of the instruction. + base = m_reg_info->getEncodingValue (insn.getOperand(num_operands-2).getReg()); + + // We are looking for sp based stores so if base is not a stack pointer then don't proceed. + if (base != dwarf_sp_mips) + return false; + + // offset is always the last operand. + uint32_t offset = insn.getOperand(num_operands-1).getImm(); + + RegisterInfo reg_info_base; + RegisterInfo reg_info_src; + + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + base, reg_info_base)) + return false; + + // read SP + uint32_t base_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success); + if (!success) + return false; + + // Resulting base addrss + base_address = base_address + offset; + + // Total no of registers to be stored are num_operands-2. + for (uint32_t i = 0; i < num_operands - 2; i++) + { + // Get the register number to be stored. + src = m_reg_info->getEncodingValue (insn.getOperand(i).getReg()); + + /* + Record only non-volatile stores. + This check is required for SWP instruction because source operand could be any register. + SWM16 and SWM32 instruction always has saved registers as source operands. + */ + if (!nonvolatile_reg_p (src)) + return false; + + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + src, reg_info_src)) + return false; + + Context context; + RegisterValue data_src; + context.type = eContextPushRegisterOnStack; + context.SetRegisterToRegisterPlusOffset (reg_info_src, reg_info_base, 0); + + uint8_t buffer [RegisterValue::kMaxRegisterByteSize]; + Error error; + + if (!ReadRegister (®_info_base, data_src)) + return false; + + if (data_src.GetAsMemoryData (®_info_src, buffer, reg_info_src.byte_size, eByteOrderLittle, error) == 0) + return false; + + if (!WriteMemory (context, base_address, buffer, reg_info_src.byte_size)) + return false; + + // Stack address for next register + base_address = base_address + reg_info_src.byte_size; + } + return true; +} + +bool +EmulateInstructionMIPS::Emulate_LWSP (llvm::MCInst& insn) +{ + bool success = false; + uint32_t src = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); + uint32_t base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); + uint32_t imm5 = insn.getOperand(2).getImm(); + Context bad_vaddr_context; + + RegisterInfo reg_info_base; + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + base, reg_info_base)) + return false; - if (base == gcc_dwarf_sp_mips && nonvolatile_reg_p (src)) + // read base register + uint32_t base_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success); + if (!success) + return false; + + base_address = base_address + imm5; + + // We use bad_vaddr_context to store base address which is used by H/W watchpoint + // Set the bad_vaddr register with base address used in the instruction + bad_vaddr_context.type = eContextInvalid; + WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips, base_address); + + if (base == dwarf_sp_mips && nonvolatile_reg_p (src)) { RegisterValue data_src; RegisterInfo reg_info_src; - if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips + src, reg_info_src)) + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + src, reg_info_src)) return false; Context context; - context.type = eContextRegisterLoad; + context.type = eContextPopRegisterOffStack; + context.SetAddress (base_address); if (!WriteRegister (context, ®_info_src, data_src)) return false; @@ -737,6 +1288,105 @@ EmulateInstructionMIPS::Emulate_LW (llvm::MCInst& insn) return false; } +/* Emulate LWM16, LWM32 and LWP instructions. + + LWM16 always has stack pointer as a base register (but it is still available in MCInst as an operand). + LWM32 and LWP can have base register other than stack pointer. +*/ +bool +EmulateInstructionMIPS::Emulate_LWM16_32 (llvm::MCInst& insn) +{ + bool success = false; + uint32_t dst, base; + uint32_t num_operands = insn.getNumOperands(); // No of operands vary based on no of regs to store. + uint32_t imm = insn.getOperand(num_operands-1).getImm(); // imm is the last operand in the instruction. + + // Base register is second last operand of the instruction. + base = m_reg_info->getEncodingValue (insn.getOperand(num_operands-2).getReg()); + + // We are looking for sp based loads so if base is not a stack pointer then don't proceed. + if (base != dwarf_sp_mips) + return false; + + uint32_t base_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success); + if (!success) + return false; + + base_address = base_address + imm; + + RegisterValue data_dst; + RegisterInfo reg_info_dst; + + // Total no of registers to be re-stored are num_operands-2. + for (uint32_t i = 0; i < num_operands - 2; i++) + { + // Get the register number to be re-stored. + dst = m_reg_info->getEncodingValue (insn.getOperand(i).getReg()); + + /* + Record only non-volatile loads. + This check is required for LWP instruction because destination operand could be any register. + LWM16 and LWM32 instruction always has saved registers as destination operands. + */ + if (!nonvolatile_reg_p (dst)) + return false; + + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + dst, reg_info_dst)) + return false; + + Context context; + context.type = eContextPopRegisterOffStack; + context.SetAddress (base_address + (i*4)); + + if (!WriteRegister (context, ®_info_dst, data_dst)) + return false; + } + + return true; +} + +bool +EmulateInstructionMIPS::Emulate_JRADDIUSP (llvm::MCInst& insn) +{ + bool success = false; + int32_t imm5 = insn.getOperand(0).getImm(); + + /* JRADDIUSP immediate + * PC <- RA + * SP <- SP + zero_extend(Immediate << 2) + */ + + // This instruction operates implicitly on stack pointer, so read <sp> register. + int32_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_sp_mips, 0, &success); + if (!success) + return false; + + int32_t ra_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_ra_mips, 0, &success); + if (!success) + return false; + + int32_t result = src_opd_val + imm5; + + Context context; + + // Update the PC + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, ra_val)) + return false; + + RegisterInfo reg_info_sp; + if (GetRegisterInfo (eRegisterKindDWARF, dwarf_sp_mips, reg_info_sp)) + context.SetRegisterPlusOffset (reg_info_sp, imm5); + + // We are adjusting stack + context.type = eContextAdjustStackPointer; + + // update SP + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_sp_mips, result)) + return false; + + return true; +} + bool EmulateInstructionMIPS::Emulate_BEQ (llvm::MCInst& insn) { @@ -754,15 +1404,15 @@ EmulateInstructionMIPS::Emulate_BEQ (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; - rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -774,13 +1424,270 @@ EmulateInstructionMIPS::Emulate_BEQ (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; } bool +EmulateInstructionMIPS::Emulate_B16_MM (llvm::MCInst& insn) +{ + bool success = false; + int32_t offset, pc, target; + uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize(); + + offset = insn.getOperand(0).getImm(); + + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); + if (!success) + return false; + + // unconditional branch + target = pc + offset; + + Context context; + context.type = eContextRelativeBranchImmediate; + context.SetImmediate (current_inst_size + offset); + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) + return false; + + return true; +} + +/* + BEQZC, BNEZC are 32 bit compact instructions without a delay slot. + BEQZ16, BNEZ16 are 16 bit instructions with delay slot. + BGEZALS, BLTZALS are 16 bit instructions with short (2-byte) delay slot. +*/ +bool +EmulateInstructionMIPS::Emulate_Branch_MM (llvm::MCInst& insn) +{ + bool success = false; + int32_t target = 0; + uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize(); + const char *op_name = m_insn_info->getName (insn.getOpcode ()); + bool update_ra = false; + uint32_t ra_offset = 0; + + /* + * BEQZ16 rs, offset + * condition <- (GPR[rs] = 0) + * if condition then + * PC = PC + sign_ext (offset || 0) + * + * BNEZ16 rs, offset + * condition <- (GPR[rs] != 0) + * if condition then + * PC = PC + sign_ext (offset || 0) + * + * BEQZC rs, offset (compact instruction: No delay slot) + * condition <- (GPR[rs] == 0) + * if condition then + * PC = PC + 4 + sign_ext (offset || 0) + */ + + uint32_t rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); + int32_t offset = insn.getOperand(1).getImm(); + + int32_t pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); + if (!success) + return false; + + int32_t rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); + if (!success) + return false; + + if (!strcasecmp (op_name, "BEQZ16_MM")) + { + if (rs_val == 0) + target = pc + offset; + else + target = pc + current_inst_size + m_next_inst_size; // Skip delay slot instruction. + } + else if (!strcasecmp (op_name, "BNEZ16_MM")) + { + if (rs_val != 0) + target = pc + offset; + else + target = pc + current_inst_size + m_next_inst_size; // Skip delay slot instruction. + } + else if (!strcasecmp (op_name, "BEQZC_MM")) + { + if (rs_val == 0) + target = pc + 4 + offset; + else + target = pc + 4; // 32 bit instruction and does not have delay slot instruction. + } + else if (!strcasecmp (op_name, "BNEZC_MM")) + { + if (rs_val != 0) + target = pc + 4 + offset; + else + target = pc + 4; // 32 bit instruction and does not have delay slot instruction. + } + else if (!strcasecmp (op_name, "BGEZALS_MM")) + { + if (rs_val >= 0) + target = pc + offset; + else + target = pc + 6; // 32 bit instruction with short (2-byte) delay slot + + update_ra = true; + ra_offset = 6; + } + else if (!strcasecmp (op_name, "BLTZALS_MM")) + { + if (rs_val >= 0) + target = pc + offset; + else + target = pc + 6; // 32 bit instruction with short (2-byte) delay slot + + update_ra = true; + ra_offset = 6; + } + + Context context; + context.type = eContextRelativeBranchImmediate; + context.SetImmediate (current_inst_size + offset); + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) + return false; + + if (update_ra) + { + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + ra_offset)) + return false; + } + return true; +} + +/* Emulate micromips jump instructions. + JALR16,JALRS16 +*/ +bool +EmulateInstructionMIPS::Emulate_JALRx16_MM (llvm::MCInst& insn) +{ + bool success = false; + uint32_t ra_offset = 0; + const char *op_name = m_insn_info->getName (insn.getOpcode ()); + + uint32_t rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); + + uint32_t pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); + if (!success) + return false; + + uint32_t rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); + if (!success) + return false; + + if (!strcasecmp (op_name, "JALR16_MM")) + ra_offset = 6; // 2-byte instruction with 4-byte delay slot. + else if (!strcasecmp (op_name, "JALRS16_MM")) + ra_offset = 4; // 2-byte instruction with 2-byte delay slot. + + Context context; + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, rs_val)) + return false; + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + ra_offset)) + return false; + + return true; +} + +/* Emulate JALS and JALX instructions. + JALS 32 bit instruction with short (2-byte) delay slot. + JALX 32 bit instruction with 4-byte delay slot. +*/ +bool +EmulateInstructionMIPS::Emulate_JALx (llvm::MCInst& insn) +{ + bool success = false; + uint32_t offset=0, target=0, pc=0, ra_offset=0; + const char *op_name = m_insn_info->getName (insn.getOpcode ()); + + /* + * JALS target + * RA = PC + 6 + * offset = sign_ext (offset << 1) + * PC = PC[31-27] | offset + * JALX target + * RA = PC + 8 + * offset = sign_ext (offset << 2) + * PC = PC[31-28] | offset + */ + offset = insn.getOperand(0).getImm(); + + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); + if (!success) + return false; + + // These are PC-region branches and not PC-relative. + if (!strcasecmp (op_name, "JALS_MM")) + { + // target address is in the “current” 128 MB-aligned region + target = (pc & 0xF8000000UL) | offset; + ra_offset = 6; + } + else if (!strcasecmp (op_name, "JALX_MM")) + { + // target address is in the “current” 256 MB-aligned region + target = (pc & 0xF0000000UL) | offset; + ra_offset = 8; + } + + Context context; + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) + return false; + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + ra_offset)) + return false; + + return true; +} + +bool +EmulateInstructionMIPS::Emulate_JALRS (llvm::MCInst& insn) +{ + bool success = false; + uint32_t rs=0, rt=0; + int32_t pc=0, rs_val=0; + + /* + JALRS rt, rs + GPR[rt] <- PC + 6 + PC <- GPR[rs] + */ + + rt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); + rs = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); + + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); + if (!success) + return false; + + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); + if (!success) + return false; + + Context context; + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, rs_val)) + return false; + + // This is 4-byte instruction with 2-byte delay slot. + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_zero_mips + rt, pc + 6)) + return false; + + return true; +} + +bool EmulateInstructionMIPS::Emulate_BNE (llvm::MCInst& insn) { bool success = false; @@ -797,15 +1704,15 @@ EmulateInstructionMIPS::Emulate_BNE (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; - rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -817,7 +1724,7 @@ EmulateInstructionMIPS::Emulate_BNE (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -840,15 +1747,15 @@ EmulateInstructionMIPS::Emulate_BEQL (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; - rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -860,7 +1767,7 @@ EmulateInstructionMIPS::Emulate_BEQL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -883,15 +1790,15 @@ EmulateInstructionMIPS::Emulate_BNEL (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; - rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -903,7 +1810,7 @@ EmulateInstructionMIPS::Emulate_BNEL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -926,11 +1833,11 @@ EmulateInstructionMIPS::Emulate_BGEZL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -942,7 +1849,7 @@ EmulateInstructionMIPS::Emulate_BGEZL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -965,11 +1872,11 @@ EmulateInstructionMIPS::Emulate_BLTZL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -981,7 +1888,7 @@ EmulateInstructionMIPS::Emulate_BLTZL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -1004,11 +1911,11 @@ EmulateInstructionMIPS::Emulate_BGTZL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1020,7 +1927,7 @@ EmulateInstructionMIPS::Emulate_BGTZL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -1043,11 +1950,11 @@ EmulateInstructionMIPS::Emulate_BLEZL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1059,7 +1966,7 @@ EmulateInstructionMIPS::Emulate_BLEZL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -1082,11 +1989,11 @@ EmulateInstructionMIPS::Emulate_BGTZ (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1098,7 +2005,7 @@ EmulateInstructionMIPS::Emulate_BGTZ (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -1121,11 +2028,11 @@ EmulateInstructionMIPS::Emulate_BLEZ (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1137,7 +2044,7 @@ EmulateInstructionMIPS::Emulate_BLEZ (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -1160,11 +2067,11 @@ EmulateInstructionMIPS::Emulate_BLTZ (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1176,7 +2083,7 @@ EmulateInstructionMIPS::Emulate_BLTZ (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -1199,11 +2106,11 @@ EmulateInstructionMIPS::Emulate_BGEZALL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1215,10 +2122,10 @@ EmulateInstructionMIPS::Emulate_BGEZALL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 8)) return false; return true; @@ -1238,7 +2145,7 @@ EmulateInstructionMIPS::Emulate_BAL (llvm::MCInst& insn) */ offset = insn.getOperand(0).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; @@ -1246,10 +2153,10 @@ EmulateInstructionMIPS::Emulate_BAL (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 8)) return false; return true; @@ -1269,7 +2176,7 @@ EmulateInstructionMIPS::Emulate_BALC (llvm::MCInst& insn) */ offset = insn.getOperand(0).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; @@ -1277,10 +2184,10 @@ EmulateInstructionMIPS::Emulate_BALC (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 4)) return false; return true; @@ -1305,11 +2212,11 @@ EmulateInstructionMIPS::Emulate_BGEZAL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1320,10 +2227,10 @@ EmulateInstructionMIPS::Emulate_BGEZAL (llvm::MCInst& insn) else target = pc + 8; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 8)) return false; return true; @@ -1348,11 +2255,11 @@ EmulateInstructionMIPS::Emulate_BLTZAL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1363,10 +2270,10 @@ EmulateInstructionMIPS::Emulate_BLTZAL (llvm::MCInst& insn) else target = pc + 8; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 8)) return false; return true; @@ -1391,11 +2298,11 @@ EmulateInstructionMIPS::Emulate_BLTZALL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1406,10 +2313,10 @@ EmulateInstructionMIPS::Emulate_BLTZALL (llvm::MCInst& insn) else target = pc + 8; /* skip delay slot */ - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 8)) return false; return true; @@ -1435,11 +2342,11 @@ EmulateInstructionMIPS::Emulate_BLEZALC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1450,10 +2357,10 @@ EmulateInstructionMIPS::Emulate_BLEZALC (llvm::MCInst& insn) else target = pc + 4; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 4)) return false; return true; @@ -1478,11 +2385,11 @@ EmulateInstructionMIPS::Emulate_BGEZALC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1493,10 +2400,10 @@ EmulateInstructionMIPS::Emulate_BGEZALC (llvm::MCInst& insn) else target = pc + 4; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 4)) return false; return true; @@ -1521,11 +2428,11 @@ EmulateInstructionMIPS::Emulate_BLTZALC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1536,10 +2443,10 @@ EmulateInstructionMIPS::Emulate_BLTZALC (llvm::MCInst& insn) else target = pc + 4; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 4)) return false; return true; @@ -1564,11 +2471,11 @@ EmulateInstructionMIPS::Emulate_BGTZALC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1579,10 +2486,10 @@ EmulateInstructionMIPS::Emulate_BGTZALC (llvm::MCInst& insn) else target = pc + 4; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 4)) return false; return true; @@ -1606,11 +2513,11 @@ EmulateInstructionMIPS::Emulate_BEQZALC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1621,10 +2528,10 @@ EmulateInstructionMIPS::Emulate_BEQZALC (llvm::MCInst& insn) else target = pc + 4; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 4)) return false; return true; @@ -1648,11 +2555,11 @@ EmulateInstructionMIPS::Emulate_BNEZALC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1663,10 +2570,10 @@ EmulateInstructionMIPS::Emulate_BNEZALC (llvm::MCInst& insn) else target = pc + 4; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 4)) return false; return true; @@ -1689,11 +2596,11 @@ EmulateInstructionMIPS::Emulate_BGEZ (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1704,7 +2611,7 @@ EmulateInstructionMIPS::Emulate_BGEZ (llvm::MCInst& insn) else target = pc + 8; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -1723,7 +2630,7 @@ EmulateInstructionMIPS::Emulate_BC (llvm::MCInst& insn) */ offset = insn.getOperand(0).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; @@ -1731,7 +2638,7 @@ EmulateInstructionMIPS::Emulate_BC (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -1754,15 +2661,15 @@ EmulateInstructionMIPS::Emulate_BEQC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; - rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -1774,7 +2681,7 @@ EmulateInstructionMIPS::Emulate_BEQC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -1797,15 +2704,15 @@ EmulateInstructionMIPS::Emulate_BNEC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; - rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -1817,7 +2724,7 @@ EmulateInstructionMIPS::Emulate_BNEC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -1841,15 +2748,15 @@ EmulateInstructionMIPS::Emulate_BLTC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; - rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -1861,7 +2768,7 @@ EmulateInstructionMIPS::Emulate_BLTC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -1885,15 +2792,15 @@ EmulateInstructionMIPS::Emulate_BGEC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; - rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -1905,7 +2812,7 @@ EmulateInstructionMIPS::Emulate_BGEC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -1929,15 +2836,15 @@ EmulateInstructionMIPS::Emulate_BLTUC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; - rt_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -1949,7 +2856,7 @@ EmulateInstructionMIPS::Emulate_BLTUC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -1973,15 +2880,15 @@ EmulateInstructionMIPS::Emulate_BGEUC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; - rt_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -1993,7 +2900,7 @@ EmulateInstructionMIPS::Emulate_BGEUC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2016,11 +2923,11 @@ EmulateInstructionMIPS::Emulate_BLTZC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -2032,7 +2939,7 @@ EmulateInstructionMIPS::Emulate_BLTZC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2055,11 +2962,11 @@ EmulateInstructionMIPS::Emulate_BLEZC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -2071,7 +2978,7 @@ EmulateInstructionMIPS::Emulate_BLEZC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2094,11 +3001,11 @@ EmulateInstructionMIPS::Emulate_BGEZC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -2110,7 +3017,7 @@ EmulateInstructionMIPS::Emulate_BGEZC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2133,11 +3040,11 @@ EmulateInstructionMIPS::Emulate_BGTZC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -2149,7 +3056,7 @@ EmulateInstructionMIPS::Emulate_BGTZC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2172,11 +3079,11 @@ EmulateInstructionMIPS::Emulate_BEQZC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -2188,7 +3095,7 @@ EmulateInstructionMIPS::Emulate_BEQZC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2211,11 +3118,11 @@ EmulateInstructionMIPS::Emulate_BNEZC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -2227,7 +3134,7 @@ EmulateInstructionMIPS::Emulate_BNEZC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2258,15 +3165,15 @@ EmulateInstructionMIPS::Emulate_BOVC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; - rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -2278,7 +3185,7 @@ EmulateInstructionMIPS::Emulate_BOVC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2302,15 +3209,15 @@ EmulateInstructionMIPS::Emulate_BNVC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; - rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -2322,7 +3229,7 @@ EmulateInstructionMIPS::Emulate_BNVC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2341,7 +3248,7 @@ EmulateInstructionMIPS::Emulate_J (llvm::MCInst& insn) */ offset = insn.getOperand(0).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; @@ -2350,7 +3257,7 @@ EmulateInstructionMIPS::Emulate_J (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, pc)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, pc)) return false; return true; @@ -2369,7 +3276,7 @@ EmulateInstructionMIPS::Emulate_JAL (llvm::MCInst& insn) */ offset = insn.getOperand(0).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; @@ -2378,10 +3285,10 @@ EmulateInstructionMIPS::Emulate_JAL (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 8)) return false; return true; @@ -2402,20 +3309,20 @@ EmulateInstructionMIPS::Emulate_JALR (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); rs = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, rs_val)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, rs_val)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_zero_mips + rt, pc + 8)) return false; return true; @@ -2437,11 +3344,11 @@ EmulateInstructionMIPS::Emulate_JIALC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -2449,10 +3356,10 @@ EmulateInstructionMIPS::Emulate_JIALC (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 4)) return false; return true; @@ -2473,7 +3380,7 @@ EmulateInstructionMIPS::Emulate_JIC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -2481,7 +3388,7 @@ EmulateInstructionMIPS::Emulate_JIC (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2500,13 +3407,13 @@ EmulateInstructionMIPS::Emulate_JR (llvm::MCInst& insn) */ rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, rs_val)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, rs_val)) return false; return true; @@ -2529,11 +3436,11 @@ EmulateInstructionMIPS::Emulate_BC1F (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips, 0, &success); + fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips, 0, &success); if (!success) return false; @@ -2547,7 +3454,7 @@ EmulateInstructionMIPS::Emulate_BC1F (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2570,11 +3477,11 @@ EmulateInstructionMIPS::Emulate_BC1T (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips, 0, &success); + fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips, 0, &success); if (!success) return false; @@ -2588,7 +3495,7 @@ EmulateInstructionMIPS::Emulate_BC1T (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2611,11 +3518,11 @@ EmulateInstructionMIPS::Emulate_BC1FL (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips, 0, &success); + fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips, 0, &success); if (!success) return false; @@ -2629,7 +3536,7 @@ EmulateInstructionMIPS::Emulate_BC1FL (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2652,11 +3559,11 @@ EmulateInstructionMIPS::Emulate_BC1TL (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips, 0, &success); + fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips, 0, &success); if (!success) return false; @@ -2670,7 +3577,7 @@ EmulateInstructionMIPS::Emulate_BC1TL (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2694,11 +3601,11 @@ EmulateInstructionMIPS::Emulate_BC1EQZ (llvm::MCInst& insn) ft = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - ft_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + ft, 0, &success); + ft_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + ft, 0, &success); if (!success) return false; @@ -2709,7 +3616,7 @@ EmulateInstructionMIPS::Emulate_BC1EQZ (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2733,11 +3640,11 @@ EmulateInstructionMIPS::Emulate_BC1NEZ (llvm::MCInst& insn) ft = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - ft_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + ft, 0, &success); + ft_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + ft, 0, &success); if (!success) return false; @@ -2748,7 +3655,7 @@ EmulateInstructionMIPS::Emulate_BC1NEZ (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2772,11 +3679,11 @@ EmulateInstructionMIPS::Emulate_BC1ANY2F (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips, 0, &success); + fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips, 0, &success); if (!success) return false; @@ -2791,7 +3698,7 @@ EmulateInstructionMIPS::Emulate_BC1ANY2F (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2815,11 +3722,11 @@ EmulateInstructionMIPS::Emulate_BC1ANY2T (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips, 0, &success); + fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips, 0, &success); if (!success) return false; @@ -2834,7 +3741,7 @@ EmulateInstructionMIPS::Emulate_BC1ANY2T (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2860,11 +3767,11 @@ EmulateInstructionMIPS::Emulate_BC1ANY4F (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips, 0, &success); + fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips, 0, &success); if (!success) return false; @@ -2879,7 +3786,7 @@ EmulateInstructionMIPS::Emulate_BC1ANY4F (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2905,11 +3812,11 @@ EmulateInstructionMIPS::Emulate_BC1ANY4T (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips, 0, &success); + fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips, 0, &success); if (!success) return false; @@ -2924,8 +3831,234 @@ EmulateInstructionMIPS::Emulate_BC1ANY4T (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) + return false; + + return true; +} + +bool +EmulateInstructionMIPS::Emulate_BNZB (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 1, true); +} + +bool +EmulateInstructionMIPS::Emulate_BNZH (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 2, true); +} + +bool +EmulateInstructionMIPS::Emulate_BNZW (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 4, true); +} + +bool +EmulateInstructionMIPS::Emulate_BNZD (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 8, true); +} + +bool +EmulateInstructionMIPS::Emulate_BZB (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 1, false); +} + +bool +EmulateInstructionMIPS::Emulate_BZH (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 2, false); +} + +bool +EmulateInstructionMIPS::Emulate_BZW (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 4, false); +} + +bool +EmulateInstructionMIPS::Emulate_BZD (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 8, false); +} + +bool +EmulateInstructionMIPS::Emulate_MSA_Branch_DF (llvm::MCInst& insn, int element_byte_size, bool bnz) +{ + bool success = false, branch_hit = true; + int32_t target = 0; + RegisterValue reg_value; + uint8_t * ptr = NULL; + + uint32_t wt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); + int32_t offset = insn.getOperand(1).getImm(); + + int32_t pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); + if (!success) + return false; + + if (ReadRegister (eRegisterKindDWARF, dwarf_w0_mips + wt, reg_value)) + ptr = (uint8_t *)reg_value.GetBytes(); + else + return false; + + for(int i = 0; i < 16 / element_byte_size; i++) + { + switch(element_byte_size) + { + case 1: + if((*ptr == 0 && bnz) || (*ptr != 0 && !bnz) ) + branch_hit = false; + break; + case 2: + if((*(uint16_t *)ptr == 0 && bnz) || (*(uint16_t *)ptr != 0 && !bnz)) + branch_hit = false; + break; + case 4: + if((*(uint32_t *)ptr == 0 && bnz) || (*(uint32_t *)ptr != 0 && !bnz)) + branch_hit = false; + break; + case 8: + if((*(uint64_t *)ptr == 0 && bnz) || (*(uint64_t *)ptr != 0 && !bnz)) + branch_hit = false; + break; + } + if(!branch_hit) + break; + ptr = ptr + element_byte_size; + } + + if(branch_hit) + target = pc + offset; + else + target = pc + 8; + + Context context; + context.type = eContextRelativeBranchImmediate; + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; } + +bool +EmulateInstructionMIPS::Emulate_BNZV (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_V (insn, true); +} + +bool +EmulateInstructionMIPS::Emulate_BZV (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_V (insn, false); +} + +bool +EmulateInstructionMIPS::Emulate_MSA_Branch_V (llvm::MCInst& insn, bool bnz) +{ + bool success = false; + int32_t target = 0; + llvm::APInt wr_val = llvm::APInt::getNullValue(128); + llvm::APInt fail_value = llvm::APInt::getMaxValue(128); + llvm::APInt zero_value = llvm::APInt::getNullValue(128); + RegisterValue reg_value; + + uint32_t wt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); + int32_t offset = insn.getOperand(1).getImm(); + + int32_t pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); + if (!success) + return false; + + if (ReadRegister (eRegisterKindDWARF, dwarf_w0_mips + wt, reg_value)) + wr_val = reg_value.GetAsUInt128(fail_value); + else + return false; + + if((llvm::APInt::isSameValue(zero_value, wr_val) && !bnz) || (!llvm::APInt::isSameValue(zero_value, wr_val) && bnz)) + target = pc + offset; + else + target = pc + 8; + + Context context; + context.type = eContextRelativeBranchImmediate; + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) + return false; + + return true; +} + +bool +EmulateInstructionMIPS::Emulate_LDST_Imm (llvm::MCInst& insn) +{ + bool success = false; + uint32_t base; + int32_t imm, address; + Context bad_vaddr_context; + + uint32_t num_operands = insn.getNumOperands(); + base = m_reg_info->getEncodingValue (insn.getOperand(num_operands-2).getReg()); + imm = insn.getOperand(num_operands-1).getImm(); + + RegisterInfo reg_info_base; + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + base, reg_info_base)) + return false; + + /* read base register */ + address =(int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success); + if (!success) + return false; + + /* destination address */ + address = address + imm; + + /* Set the bad_vaddr register with base address used in the instruction */ + bad_vaddr_context.type = eContextInvalid; + WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips, address); + + return true; +} + +bool +EmulateInstructionMIPS::Emulate_LDST_Reg (llvm::MCInst& insn) +{ + bool success = false; + uint32_t base, index; + int32_t address, index_address; + Context bad_vaddr_context; + + uint32_t num_operands = insn.getNumOperands(); + base = m_reg_info->getEncodingValue (insn.getOperand(num_operands-2).getReg()); + index = m_reg_info->getEncodingValue (insn.getOperand(num_operands-1).getReg()); + + RegisterInfo reg_info_base, reg_info_index; + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + base, reg_info_base)) + return false; + + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + index, reg_info_index)) + return false; + + /* read base register */ + address =(int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success); + if (!success) + return false; + + /* read index register */ + index_address =(int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + index, 0, &success); + if (!success) + return false; + + /* destination address */ + address = address + index_address; + + /* Set the bad_vaddr register with base address used in the instruction */ + bad_vaddr_context.type = eContextInvalid; + WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips, address); + + return true; +} |