diff options
Diffstat (limited to 'src/arm/bcm5301x.dtsi')
| -rw-r--r-- | src/arm/bcm5301x.dtsi | 138 |
1 files changed, 117 insertions, 21 deletions
diff --git a/src/arm/bcm5301x.dtsi b/src/arm/bcm5301x.dtsi index 78aec6270c2f..65a1309bd6e2 100644 --- a/src/arm/bcm5301x.dtsi +++ b/src/arm/bcm5301x.dtsi @@ -8,6 +8,7 @@ * Licensed under the GNU/GPL. See COPYING for details. */ +#include <dt-bindings/clock/bcm-nsp.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> @@ -27,7 +28,7 @@ compatible = "ns16550"; reg = <0x0300 0x100>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <100000000>; + clocks = <&iprocslow>; status = "disabled"; }; @@ -35,63 +36,103 @@ compatible = "ns16550"; reg = <0x0400 0x100>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <100000000>; + clocks = <&iprocslow>; status = "disabled"; }; }; mpcore { compatible = "simple-bus"; - ranges = <0x00000000 0x19020000 0x00003000>; + ranges = <0x00000000 0x19000000 0x00023000>; #address-cells = <1>; #size-cells = <1>; - scu@0000 { + a9pll: arm_clk@00000 { + #clock-cells = <0>; + compatible = "brcm,nsp-armpll"; + clocks = <&osc>; + reg = <0x00000 0x1000>; + }; + + scu@20000 { compatible = "arm,cortex-a9-scu"; - reg = <0x0000 0x100>; + reg = <0x20000 0x100>; }; - timer@0200 { + timer@20200 { compatible = "arm,cortex-a9-global-timer"; - reg = <0x0200 0x100>; + reg = <0x20200 0x100>; interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_periph>; + clocks = <&periph_clk>; }; - local-timer@0600 { + local-timer@20600 { compatible = "arm,cortex-a9-twd-timer"; - reg = <0x0600 0x100>; + reg = <0x20600 0x100>; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_periph>; + clocks = <&periph_clk>; }; - gic: interrupt-controller@1000 { + gic: interrupt-controller@21000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - reg = <0x1000 0x1000>, - <0x0100 0x100>; + reg = <0x21000 0x1000>, + <0x20100 0x100>; }; - L2: cache-controller@2000 { + L2: cache-controller@22000 { compatible = "arm,pl310-cache"; - reg = <0x2000 0x1000>; + reg = <0x22000 0x1000>; cache-unified; + arm,shared-override; + prefetch-data = <1>; + prefetch-instr = <1>; cache-level = <2>; }; }; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + clocks { #address-cells = <1>; - #size-cells = <0>; + #size-cells = <1>; + ranges; - /* As long as we do not have a real clock driver us this - * fixed clock */ - clk_periph: periph { + osc: oscillator { + #clock-cells = <0>; compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + iprocmed: iprocmed { #clock-cells = <0>; - clock-frequency = <400000000>; + compatible = "fixed-factor-clock"; + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; + clock-div = <2>; + clock-mult = <1>; + }; + + iprocslow: iprocslow { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; + clock-div = <4>; + clock-mult = <1>; + }; + + periph_clk: periph_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&a9pll>; + clock-div = <2>; + clock-mult = <1>; }; }; @@ -108,6 +149,30 @@ /* ChipCommon */ <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + /* PCIe Controller 0 */ + <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + + /* PCIe Controller 1 */ + <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + + /* PCIe Controller 2 */ + <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + /* USB 2.0 Controller */ <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, @@ -143,4 +208,35 @@ #gpio-cells = <2>; }; }; + + lcpll0: lcpll0@1800c100 { + #clock-cells = <1>; + compatible = "brcm,nsp-lcpll0"; + reg = <0x1800c100 0x14>; + clocks = <&osc>; + clock-output-names = "lcpll0", "pcie_phy", "sdio", + "ddr_phy"; + }; + + genpll: genpll@1800c140 { + #clock-cells = <1>; + compatible = "brcm,nsp-genpll"; + reg = <0x1800c140 0x24>; + clocks = <&osc>; + clock-output-names = "genpll", "phy", "ethernetclk", + "usbclk", "iprocfast", "sata1", + "sata2"; + }; + + nand: nand@18028000 { + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; + reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; + reg-names = "nand", "iproc-idm", "iproc-ext"; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + brcm,nand-has-wp; + }; }; |