diff options
Diffstat (limited to 'src/arm64/broadcom/ns2.dtsi')
-rw-r--r-- | src/arm64/broadcom/ns2.dtsi | 281 |
1 files changed, 188 insertions, 93 deletions
diff --git a/src/arm64/broadcom/ns2.dtsi b/src/arm64/broadcom/ns2.dtsi index a510d3a8e647..ec68ec1a80c8 100644 --- a/src/arm64/broadcom/ns2.dtsi +++ b/src/arm64/broadcom/ns2.dtsi @@ -1,7 +1,7 @@ /* * BSD LICENSE * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. + * Copyright (c) 2015 Broadcom. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -33,8 +33,6 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/bcm-ns2.h> -/memreserve/ 0x84b00000 0x00000008; - / { compatible = "brcm,ns2"; interrupt-parent = <&gic>; @@ -49,8 +47,7 @@ device_type = "cpu"; compatible = "arm,cortex-a57", "arm,armv8"; reg = <0 0>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x84b00000>; + enable-method = "psci"; next-level-cache = <&CLUSTER0_L2>; }; @@ -58,8 +55,7 @@ device_type = "cpu"; compatible = "arm,cortex-a57", "arm,armv8"; reg = <0 1>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x84b00000>; + enable-method = "psci"; next-level-cache = <&CLUSTER0_L2>; }; @@ -67,8 +63,7 @@ device_type = "cpu"; compatible = "arm,cortex-a57", "arm,armv8"; reg = <0 2>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x84b00000>; + enable-method = "psci"; next-level-cache = <&CLUSTER0_L2>; }; @@ -76,8 +71,7 @@ device_type = "cpu"; compatible = "arm,cortex-a57", "arm,armv8"; reg = <0 3>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x84b00000>; + enable-method = "psci"; next-level-cache = <&CLUSTER0_L2>; }; @@ -86,6 +80,11 @@ }; }; + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) | @@ -110,30 +109,77 @@ <&A57_3>; }; - clocks { - #address-cells = <1>; - #size-cells = <1>; + pcie0: pcie@20020000 { + compatible = "brcm,iproc-pcie"; + reg = <0 0x20020000 0 0x1000>; - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 281 IRQ_TYPE_NONE>; + + linux,pci-domain = <0>; + + bus-range = <0x00 0xff>; - iprocmed: iprocmed { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; - clock-div = <2>; - clock-mult = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>; + + brcm,pcie-ob; + brcm,pcie-ob-oarr-size; + brcm,pcie-ob-axi-offset = <0x00000000>; + brcm,pcie-ob-window-size = <256>; + + status = "disabled"; + + msi-parent = <&msi0>; + msi0: msi@20020000 { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 277 IRQ_TYPE_NONE>, + <GIC_SPI 278 IRQ_TYPE_NONE>, + <GIC_SPI 279 IRQ_TYPE_NONE>, + <GIC_SPI 280 IRQ_TYPE_NONE>; + brcm,num-eq-region = <1>; + brcm,num-msi-msg-region = <1>; }; + }; + + pcie4: pcie@50020000 { + compatible = "brcm,iproc-pcie"; + reg = <0 0x50020000 0 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 305 IRQ_TYPE_NONE>; + + linux,pci-domain = <4>; + + bus-range = <0x00 0xff>; - iprocslow: iprocslow { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; - clock-div = <4>; - clock-mult = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>; + + brcm,pcie-ob; + brcm,pcie-ob-oarr-size; + brcm,pcie-ob-axi-offset = <0x30000000>; + brcm,pcie-ob-window-size = <256>; + + status = "disabled"; + + msi-parent = <&msi4>; + msi4: msi@50020000 { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 301 IRQ_TYPE_NONE>, + <GIC_SPI 302 IRQ_TYPE_NONE>, + <GIC_SPI 303 IRQ_TYPE_NONE>, + <GIC_SPI 304 IRQ_TYPE_NONE>; }; }; @@ -143,6 +189,27 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + #include "ns2-clock.dtsi" + + dma0: dma@61360000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x61360000 0x1000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&iprocslow>; + clock-names = "apb_pclk"; + }; + smmu: mmu@64000000 { compatible = "arm,mmu-500"; reg = <0x64000000 0x40000>; @@ -184,68 +251,6 @@ mmu-masters; }; - lcpll_ddr: lcpll_ddr@6501d058 { - #clock-cells = <1>; - compatible = "brcm,ns2-lcpll-ddr"; - reg = <0x6501d058 0x20>, - <0x6501c020 0x4>, - <0x6501d04c 0x4>; - clocks = <&osc>; - clock-output-names = "lcpll_ddr", "pcie_sata_usb", - "ddr", "ddr_ch2_unused", - "ddr_ch3_unused", "ddr_ch4_unused", - "ddr_ch5_unused"; - }; - - lcpll_ports: lcpll_ports@6501d078 { - #clock-cells = <1>; - compatible = "brcm,ns2-lcpll-ports"; - reg = <0x6501d078 0x20>, - <0x6501c020 0x4>, - <0x6501d054 0x4>; - clocks = <&osc>; - clock-output-names = "lcpll_ports", "wan", "rgmii", - "ports_ch2_unused", - "ports_ch3_unused", - "ports_ch4_unused", - "ports_ch5_unused"; - }; - - genpll_scr: genpll_scr@6501d098 { - #clock-cells = <1>; - compatible = "brcm,ns2-genpll-scr"; - reg = <0x6501d098 0x32>, - <0x6501c020 0x4>, - <0x6501d044 0x4>; - clocks = <&osc>; - clock-output-names = "genpll_scr", "scr", "fs", - "audio_ref", "scr_ch3_unused", - "scr_ch4_unused", "scr_ch5_unused"; - }; - - genpll_sw: genpll_sw@6501d0c4 { - #clock-cells = <1>; - compatible = "brcm,ns2-genpll-sw"; - reg = <0x6501d0c4 0x32>, - <0x6501c020 0x4>, - <0x6501d044 0x4>; - clocks = <&osc>; - clock-output-names = "genpll_sw", "rpe", "250", "nic", - "chimp", "port", "sdio"; - }; - - crmu: crmu@65024000 { - compatible = "syscon"; - reg = <0x65024000 0x100>; - }; - - reboot@65024000 { - compatible ="syscon-reboot"; - regmap = <&crmu>; - offset = <0x90>; - mask = <0xfffffffd>; - }; - gic: interrupt-controller@65210000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -254,6 +259,48 @@ <0x65220000 0x1000>, <0x65240000 0x2000>, <0x65260000 0x1000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + + timer0: timer@66030000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x66030000 0x1000>; + interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&iprocslow>, + <&iprocslow>, + <&iprocslow>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + + timer1: timer@66040000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x66040000 0x1000>; + interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&iprocslow>, + <&iprocslow>, + <&iprocslow>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + + timer2: timer@66050000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x66050000 0x1000>; + interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&iprocslow>, + <&iprocslow>, + <&iprocslow>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + + timer3: timer@66060000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x66060000 0x1000>; + interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&iprocslow>, + <&iprocslow>, + <&iprocslow>; + clock-names = "timer1", "timer2", "apb_pclk"; }; i2c0: i2c@66080000 { @@ -266,6 +313,14 @@ status = "disabled"; }; + wdt0: watchdog@66090000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x66090000 0x1000>; + interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&iprocslow>, <&iprocslow>; + clock-names = "wdogclk", "apb_pclk"; + }; + i2c1: i2c@660b0000 { compatible = "brcm,iproc-i2c"; reg = <0x660b0000 0x100>; @@ -286,11 +341,51 @@ status = "disabled"; }; + ssp0: ssp@66180000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x66180000 0x1000>; + interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&iprocslow>, <&iprocslow>; + clock-names = "spiclk", "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ssp1: ssp@66190000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x66190000 0x1000>; + interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&iprocslow>, <&iprocslow>; + clock-names = "spiclk", "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + hwrng: hwrng@66220000 { compatible = "brcm,iproc-rng200"; reg = <0x66220000 0x28>; }; + sdio0: sdhci@66420000 { + compatible = "brcm,sdhci-iproc-cygnus"; + reg = <0x66420000 0x100>; + interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; + bus-width = <8>; + clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>; + status = "disabled"; + }; + + sdio1: sdhci@66430000 { + compatible = "brcm,sdhci-iproc-cygnus"; + reg = <0x66430000 0x100>; + interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; + bus-width = <8>; + clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>; + status = "disabled"; + }; + nand: nand@66460000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; reg = <0x66460000 0x600>, |