diff options
Diffstat (limited to 'sys/arm/include')
88 files changed, 11090 insertions, 0 deletions
diff --git a/sys/arm/include/_align.h b/sys/arm/include/_align.h new file mode 100644 index 000000000000..a8c6df4304f8 --- /dev/null +++ b/sys/arm/include/_align.h @@ -0,0 +1,54 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (c) 2001 David E. O'Brien + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * William Jolitz. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: @(#)param.h 5.8 (Berkeley) 6/28/91 + * $FreeBSD$ + */ + +#ifndef _ARM_INCLUDE__ALIGN_H_ +#define _ARM_INCLUDE__ALIGN_H_ + +/* + * Round p (pointer or byte index) up to the hardware-required alignment which + * is sufficient for any data type, pointer or numeric. The resulting type + * is equivelent to arm's uintptr_t (but is purposely spelled "unsigned" here). + */ +#define _ALIGNBYTES (sizeof(int) - 1) +#define _ALIGN(p) (((unsigned)(p) + _ALIGNBYTES) & ~_ALIGNBYTES) + +#endif /* !_ARM_INCLUDE__ALIGN_H_ */ diff --git a/sys/arm/include/_bus.h b/sys/arm/include/_bus.h new file mode 100644 index 000000000000..803dda2e2763 --- /dev/null +++ b/sys/arm/include/_bus.h @@ -0,0 +1,47 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2005 M. Warner Losh <imp@FreeBSD.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification, immediately at the beginning of the file. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef ARM_INCLUDE__BUS_H +#define ARM_INCLUDE__BUS_H + +/* + * Addresses (in bus space). + */ +typedef u_long bus_addr_t; +typedef u_long bus_size_t; + +/* + * Access methods for bus space. + */ +typedef struct bus_space *bus_space_tag_t; +typedef u_long bus_space_handle_t; + +#endif /* ARM_INCLUDE__BUS_H */ diff --git a/sys/arm/include/_inttypes.h b/sys/arm/include/_inttypes.h new file mode 100644 index 000000000000..d8c1ce8a6cb9 --- /dev/null +++ b/sys/arm/include/_inttypes.h @@ -0,0 +1,215 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-NetBSD + * + * Copyright (c) 2001 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Klaus Klein. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * From: $NetBSD: int_fmtio.h,v 1.2 2001/04/26 16:25:21 kleink Exp $ + * $FreeBSD$ + */ + +#ifndef _MACHINE_INTTYPES_H_ +#define _MACHINE_INTTYPES_H_ + +/* + * Macros for format specifiers. + */ + +/* fprintf(3) macros for signed integers. */ + +#define PRId8 "d" /* int8_t */ +#define PRId16 "d" /* int16_t */ +#define PRId32 "d" /* int32_t */ +#define PRId64 "lld" /* int64_t */ +#define PRIdLEAST8 "d" /* int_least8_t */ +#define PRIdLEAST16 "d" /* int_least16_t */ +#define PRIdLEAST32 "d" /* int_least32_t */ +#define PRIdLEAST64 "lld" /* int_least64_t */ +#define PRIdFAST8 "d" /* int_fast8_t */ +#define PRIdFAST16 "d" /* int_fast16_t */ +#define PRIdFAST32 "d" /* int_fast32_t */ +#define PRIdFAST64 "lld" /* int_fast64_t */ +#define PRIdMAX "jd" /* intmax_t */ +#define PRIdPTR "d" /* intptr_t */ + +#define PRIi8 "i" /* int8_t */ +#define PRIi16 "i" /* int16_t */ +#define PRIi32 "i" /* int32_t */ +#define PRIi64 "lli" /* int64_t */ +#define PRIiLEAST8 "i" /* int_least8_t */ +#define PRIiLEAST16 "i" /* int_least16_t */ +#define PRIiLEAST32 "i" /* int_least32_t */ +#define PRIiLEAST64 "lli" /* int_least64_t */ +#define PRIiFAST8 "i" /* int_fast8_t */ +#define PRIiFAST16 "i" /* int_fast16_t */ +#define PRIiFAST32 "i" /* int_fast32_t */ +#define PRIiFAST64 "lli" /* int_fast64_t */ +#define PRIiMAX "ji" /* intmax_t */ +#define PRIiPTR "i" /* intptr_t */ + +/* fprintf(3) macros for unsigned integers. */ + +#define PRIo8 "o" /* uint8_t */ +#define PRIo16 "o" /* uint16_t */ +#define PRIo32 "o" /* uint32_t */ +#define PRIo64 "llo" /* uint64_t */ +#define PRIoLEAST8 "o" /* uint_least8_t */ +#define PRIoLEAST16 "o" /* uint_least16_t */ +#define PRIoLEAST32 "o" /* uint_least32_t */ +#define PRIoLEAST64 "llo" /* uint_least64_t */ +#define PRIoFAST8 "o" /* uint_fast8_t */ +#define PRIoFAST16 "o" /* uint_fast16_t */ +#define PRIoFAST32 "o" /* uint_fast32_t */ +#define PRIoFAST64 "llo" /* uint_fast64_t */ +#define PRIoMAX "jo" /* uintmax_t */ +#define PRIoPTR "o" /* uintptr_t */ + +#define PRIu8 "u" /* uint8_t */ +#define PRIu16 "u" /* uint16_t */ +#define PRIu32 "u" /* uint32_t */ +#define PRIu64 "llu" /* uint64_t */ +#define PRIuLEAST8 "u" /* uint_least8_t */ +#define PRIuLEAST16 "u" /* uint_least16_t */ +#define PRIuLEAST32 "u" /* uint_least32_t */ +#define PRIuLEAST64 "llu" /* uint_least64_t */ +#define PRIuFAST8 "u" /* uint_fast8_t */ +#define PRIuFAST16 "u" /* uint_fast16_t */ +#define PRIuFAST32 "u" /* uint_fast32_t */ +#define PRIuFAST64 "llu" /* uint_fast64_t */ +#define PRIuMAX "ju" /* uintmax_t */ +#define PRIuPTR "u" /* uintptr_t */ + +#define PRIx8 "x" /* uint8_t */ +#define PRIx16 "x" /* uint16_t */ +#define PRIx32 "x" /* uint32_t */ +#define PRIx64 "llx" /* uint64_t */ +#define PRIxLEAST8 "x" /* uint_least8_t */ +#define PRIxLEAST16 "x" /* uint_least16_t */ +#define PRIxLEAST32 "x" /* uint_least32_t */ +#define PRIxLEAST64 "llx" /* uint_least64_t */ +#define PRIxFAST8 "x" /* uint_fast8_t */ +#define PRIxFAST16 "x" /* uint_fast16_t */ +#define PRIxFAST32 "x" /* uint_fast32_t */ +#define PRIxFAST64 "llx" /* uint_fast64_t */ +#define PRIxMAX "jx" /* uintmax_t */ +#define PRIxPTR "x" /* uintptr_t */ + +#define PRIX8 "X" /* uint8_t */ +#define PRIX16 "X" /* uint16_t */ +#define PRIX32 "X" /* uint32_t */ +#define PRIX64 "llX" /* uint64_t */ +#define PRIXLEAST8 "X" /* uint_least8_t */ +#define PRIXLEAST16 "X" /* uint_least16_t */ +#define PRIXLEAST32 "X" /* uint_least32_t */ +#define PRIXLEAST64 "llX" /* uint_least64_t */ +#define PRIXFAST8 "X" /* uint_fast8_t */ +#define PRIXFAST16 "X" /* uint_fast16_t */ +#define PRIXFAST32 "X" /* uint_fast32_t */ +#define PRIXFAST64 "llX" /* uint_fast64_t */ +#define PRIXMAX "jX" /* uintmax_t */ +#define PRIXPTR "X" /* uintptr_t */ + +/* fscanf(3) macros for signed integers. */ + +#define SCNd8 "hhd" /* int8_t */ +#define SCNd16 "hd" /* int16_t */ +#define SCNd32 "d" /* int32_t */ +#define SCNd64 "lld" /* int64_t */ +#define SCNdLEAST8 "hhd" /* int_least8_t */ +#define SCNdLEAST16 "hd" /* int_least16_t */ +#define SCNdLEAST32 "d" /* int_least32_t */ +#define SCNdLEAST64 "lld" /* int_least64_t */ +#define SCNdFAST8 "d" /* int_fast8_t */ +#define SCNdFAST16 "d" /* int_fast16_t */ +#define SCNdFAST32 "d" /* int_fast32_t */ +#define SCNdFAST64 "lld" /* int_fast64_t */ +#define SCNdMAX "jd" /* intmax_t */ +#define SCNdPTR "d" /* intptr_t */ + +#define SCNi8 "hhi" /* int8_t */ +#define SCNi16 "hi" /* int16_t */ +#define SCNi32 "i" /* int32_t */ +#define SCNi64 "lli" /* int64_t */ +#define SCNiLEAST8 "hhi" /* int_least8_t */ +#define SCNiLEAST16 "hi" /* int_least16_t */ +#define SCNiLEAST32 "i" /* int_least32_t */ +#define SCNiLEAST64 "lli" /* int_least64_t */ +#define SCNiFAST8 "i" /* int_fast8_t */ +#define SCNiFAST16 "i" /* int_fast16_t */ +#define SCNiFAST32 "i" /* int_fast32_t */ +#define SCNiFAST64 "lli" /* int_fast64_t */ +#define SCNiMAX "ji" /* intmax_t */ +#define SCNiPTR "i" /* intptr_t */ + +/* fscanf(3) macros for unsigned integers. */ + +#define SCNo8 "hho" /* uint8_t */ +#define SCNo16 "ho" /* uint16_t */ +#define SCNo32 "o" /* uint32_t */ +#define SCNo64 "llo" /* uint64_t */ +#define SCNoLEAST8 "hho" /* uint_least8_t */ +#define SCNoLEAST16 "ho" /* uint_least16_t */ +#define SCNoLEAST32 "o" /* uint_least32_t */ +#define SCNoLEAST64 "llo" /* uint_least64_t */ +#define SCNoFAST8 "o" /* uint_fast8_t */ +#define SCNoFAST16 "o" /* uint_fast16_t */ +#define SCNoFAST32 "o" /* uint_fast32_t */ +#define SCNoFAST64 "llo" /* uint_fast64_t */ +#define SCNoMAX "jo" /* uintmax_t */ +#define SCNoPTR "o" /* uintptr_t */ + +#define SCNu8 "hhu" /* uint8_t */ +#define SCNu16 "hu" /* uint16_t */ +#define SCNu32 "u" /* uint32_t */ +#define SCNu64 "llu" /* uint64_t */ +#define SCNuLEAST8 "hhu" /* uint_least8_t */ +#define SCNuLEAST16 "hu" /* uint_least16_t */ +#define SCNuLEAST32 "u" /* uint_least32_t */ +#define SCNuLEAST64 "llu" /* uint_least64_t */ +#define SCNuFAST8 "u" /* uint_fast8_t */ +#define SCNuFAST16 "u" /* uint_fast16_t */ +#define SCNuFAST32 "u" /* uint_fast32_t */ +#define SCNuFAST64 "llu" /* uint_fast64_t */ +#define SCNuMAX "ju" /* uintmax_t */ +#define SCNuPTR "u" /* uintptr_t */ + +#define SCNx8 "hhx" /* uint8_t */ +#define SCNx16 "hx" /* uint16_t */ +#define SCNx32 "x" /* uint32_t */ +#define SCNx64 "llx" /* uint64_t */ +#define SCNxLEAST8 "hhx" /* uint_least8_t */ +#define SCNxLEAST16 "hx" /* uint_least16_t */ +#define SCNxLEAST32 "x" /* uint_least32_t */ +#define SCNxLEAST64 "llx" /* uint_least64_t */ +#define SCNxFAST8 "x" /* uint_fast8_t */ +#define SCNxFAST16 "x" /* uint_fast16_t */ +#define SCNxFAST32 "x" /* uint_fast32_t */ +#define SCNxFAST64 "llx" /* uint_fast64_t */ +#define SCNxMAX "jx" /* uintmax_t */ +#define SCNxPTR "x" /* uintptr_t */ + +#endif /* !_MACHINE_INTTYPES_H_ */ diff --git a/sys/arm/include/_limits.h b/sys/arm/include/_limits.h new file mode 100644 index 000000000000..fe816e50f9cb --- /dev/null +++ b/sys/arm/include/_limits.h @@ -0,0 +1,89 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 1988, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)limits.h 8.3 (Berkeley) 1/4/94 + * $FreeBSD$ + */ + +#ifndef _MACHINE__LIMITS_H_ +#define _MACHINE__LIMITS_H_ + +/* + * According to ANSI (section 2.2.4.2), the values below must be usable by + * #if preprocessing directives. Additionally, the expression must have the + * same type as would an expression that is an object of the corresponding + * type converted according to the integral promotions. The subtraction for + * INT_MIN, etc., is so the value is not unsigned; e.g., 0x80000000 is an + * unsigned int for 32-bit two's complement ANSI compilers (section 3.1.3.2). + */ + +#define __CHAR_BIT 8 /* number of bits in a char */ + +#define __SCHAR_MAX 0x7f /* max value for a signed char */ +#define __SCHAR_MIN (-0x7f - 1) /* min value for a signed char */ + +#define __UCHAR_MAX 0xff /* max value for an unsigned char */ + +#define __USHRT_MAX 0xffff /* max value for an unsigned short */ +#define __SHRT_MAX 0x7fff /* max value for a short */ +#define __SHRT_MIN (-0x7fff - 1) /* min value for a short */ + +#define __UINT_MAX 0xffffffff /* max value for an unsigned int */ +#define __INT_MAX 0x7fffffff /* max value for an int */ +#define __INT_MIN (-0x7fffffff - 1) /* min value for an int */ + +#define __ULONG_MAX 0xffffffffUL /* max value for an unsigned long */ +#define __LONG_MAX 0x7fffffffL /* max value for a long */ +#define __LONG_MIN (-0x7fffffffL - 1) /* min value for a long */ + + /* max value for an unsigned long long */ +#define __ULLONG_MAX 0xffffffffffffffffULL +#define __LLONG_MAX 0x7fffffffffffffffLL /* max value for a long long */ +#define __LLONG_MIN (-0x7fffffffffffffffLL - 1) /* min for a long long */ + +#define __SSIZE_MAX __INT_MAX /* max value for a ssize_t */ + +#define __SIZE_T_MAX __UINT_MAX /* max value for a size_t */ + +#define __OFF_MAX __LLONG_MAX /* max value for a off_t */ +#define __OFF_MIN __LLONG_MIN /* min value for a off_t */ + +/* Quads and long longs are the same size. Ensure they stay in sync. */ +#define __UQUAD_MAX __ULLONG_MAX /* max value for a uquad_t */ +#define __QUAD_MAX __LLONG_MAX /* max value for a quad_t */ +#define __QUAD_MIN __LLONG_MIN /* min value for a quad_t */ + +#define __LONG_BIT 32 +#define __WORD_BIT 32 + +/* Minimum signal stack size. */ +#define __MINSIGSTKSZ (1024 * 4) + +#endif /* !_MACHINE__LIMITS_H_ */ diff --git a/sys/arm/include/_stdint.h b/sys/arm/include/_stdint.h new file mode 100644 index 000000000000..2032b7368143 --- /dev/null +++ b/sys/arm/include/_stdint.h @@ -0,0 +1,160 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-NetBSD + * + * Copyright (c) 2001, 2002 Mike Barcroft <mike@FreeBSD.org> + * Copyright (c) 2001 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Klaus Klein. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE__STDINT_H_ +#define _MACHINE__STDINT_H_ + +#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) + +#define INT8_C(c) (c) +#define INT16_C(c) (c) +#define INT32_C(c) (c) +#define INT64_C(c) (c ## LL) + +#define UINT8_C(c) (c) +#define UINT16_C(c) (c) +#define UINT32_C(c) (c ## U) +#define UINT64_C(c) (c ## ULL) + +#define INTMAX_C(c) INT64_C(c) +#define UINTMAX_C(c) UINT64_C(c) + +#endif /* !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) */ + +#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) + +/* + * ISO/IEC 9899:1999 + * 7.18.2.1 Limits of exact-width integer types + */ +/* Minimum values of exact-width signed integer types. */ +#define INT8_MIN (-0x7f-1) +#define INT16_MIN (-0x7fff-1) +#define INT32_MIN (-0x7fffffff-1) +#define INT64_MIN (-0x7fffffffffffffffLL-1) + +/* Maximum values of exact-width signed integer types. */ +#define INT8_MAX 0x7f +#define INT16_MAX 0x7fff +#define INT32_MAX 0x7fffffff +#define INT64_MAX 0x7fffffffffffffffLL + +/* Maximum values of exact-width unsigned integer types. */ +#define UINT8_MAX 0xff +#define UINT16_MAX 0xffff +#define UINT32_MAX 0xffffffffU +#define UINT64_MAX 0xffffffffffffffffULL + +/* + * ISO/IEC 9899:1999 + * 7.18.2.2 Limits of minimum-width integer types + */ +/* Minimum values of minimum-width signed integer types. */ +#define INT_LEAST8_MIN INT8_MIN +#define INT_LEAST16_MIN INT16_MIN +#define INT_LEAST32_MIN INT32_MIN +#define INT_LEAST64_MIN INT64_MIN + +/* Maximum values of minimum-width signed integer types. */ +#define INT_LEAST8_MAX INT8_MAX +#define INT_LEAST16_MAX INT16_MAX +#define INT_LEAST32_MAX INT32_MAX +#define INT_LEAST64_MAX INT64_MAX + +/* Maximum values of minimum-width unsigned integer types. */ +#define UINT_LEAST8_MAX UINT8_MAX +#define UINT_LEAST16_MAX UINT16_MAX +#define UINT_LEAST32_MAX UINT32_MAX +#define UINT_LEAST64_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.2.3 Limits of fastest minimum-width integer types + */ +/* Minimum values of fastest minimum-width signed integer types. */ +#define INT_FAST8_MIN INT32_MIN +#define INT_FAST16_MIN INT32_MIN +#define INT_FAST32_MIN INT32_MIN +#define INT_FAST64_MIN INT64_MIN + +/* Maximum values of fastest minimum-width signed integer types. */ +#define INT_FAST8_MAX INT32_MAX +#define INT_FAST16_MAX INT32_MAX +#define INT_FAST32_MAX INT32_MAX +#define INT_FAST64_MAX INT64_MAX + +/* Maximum values of fastest minimum-width unsigned integer types. */ +#define UINT_FAST8_MAX UINT32_MAX +#define UINT_FAST16_MAX UINT32_MAX +#define UINT_FAST32_MAX UINT32_MAX +#define UINT_FAST64_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.2.4 Limits of integer types capable of holding object pointers + */ +#define INTPTR_MIN INT32_MIN +#define INTPTR_MAX INT32_MAX +#define UINTPTR_MAX UINT32_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.2.5 Limits of greatest-width integer types + */ +#define INTMAX_MIN INT64_MIN +#define INTMAX_MAX INT64_MAX +#define UINTMAX_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.3 Limits of other integer types + */ +/* Limits of ptrdiff_t. */ +#define PTRDIFF_MIN INT32_MIN +#define PTRDIFF_MAX INT32_MAX + +/* Limits of sig_atomic_t. */ +#define SIG_ATOMIC_MIN INT32_MIN +#define SIG_ATOMIC_MAX INT32_MAX + +/* Limit of size_t. */ +#define SIZE_MAX UINT32_MAX + +/* Limits of wint_t. */ +#define WINT_MIN INT32_MIN +#define WINT_MAX INT32_MAX + +#endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */ + +#endif /* !_MACHINE__STDINT_H_ */ diff --git a/sys/arm/include/_types.h b/sys/arm/include/_types.h new file mode 100644 index 000000000000..14ab76c5fbde --- /dev/null +++ b/sys/arm/include/_types.h @@ -0,0 +1,114 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (c) 2002 Mike Barcroft <mike@FreeBSD.org> + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * From: @(#)ansi.h 8.2 (Berkeley) 1/4/94 + * From: @(#)types.h 8.3 (Berkeley) 1/5/94 + * $FreeBSD$ + */ + +#ifndef _MACHINE__TYPES_H_ +#define _MACHINE__TYPES_H_ + +#ifndef _SYS_CDEFS_H_ +#error this file needs sys/cdefs.h as a prerequisite +#endif + +/* + * Basic types upon which most other types are built. + */ +typedef signed char __int8_t; +typedef unsigned char __uint8_t; +typedef short __int16_t; +typedef unsigned short __uint16_t; +typedef int __int32_t; +typedef unsigned int __uint32_t; +#ifndef lint +__extension__ +#endif +/* LONGLONG */ +typedef long long __int64_t; +#ifndef lint +__extension__ +#endif +/* LONGLONG */ +typedef unsigned long long __uint64_t; + +/* + * Standard type definitions. + */ +typedef __uint32_t __clock_t; /* clock()... */ +typedef __int32_t __critical_t; +#ifndef _STANDALONE +typedef double __double_t; +typedef float __float_t; +#endif +typedef __int32_t __intfptr_t; +typedef __int64_t __intmax_t; +typedef __int32_t __intptr_t; +typedef __int32_t __int_fast8_t; +typedef __int32_t __int_fast16_t; +typedef __int32_t __int_fast32_t; +typedef __int64_t __int_fast64_t; +typedef __int8_t __int_least8_t; +typedef __int16_t __int_least16_t; +typedef __int32_t __int_least32_t; +typedef __int64_t __int_least64_t; +typedef __int32_t __ptrdiff_t; /* ptr1 - ptr2 */ +typedef __int32_t __register_t; +typedef __int32_t __segsz_t; /* segment size (in pages) */ +typedef __uint32_t __size_t; /* sizeof() */ +typedef __int32_t __ssize_t; /* byte count or error */ +typedef __int64_t __time_t; /* time()... */ +typedef __uint32_t __uintfptr_t; +typedef __uint64_t __uintmax_t; +typedef __uint32_t __uintptr_t; +typedef __uint32_t __uint_fast8_t; +typedef __uint32_t __uint_fast16_t; +typedef __uint32_t __uint_fast32_t; +typedef __uint64_t __uint_fast64_t; +typedef __uint8_t __uint_least8_t; +typedef __uint16_t __uint_least16_t; +typedef __uint32_t __uint_least32_t; +typedef __uint64_t __uint_least64_t; +typedef __uint32_t __u_register_t; +typedef __uint32_t __vm_offset_t; +typedef __uint32_t __vm_paddr_t; +typedef __uint32_t __vm_size_t; + +typedef unsigned int ___wchar_t; +#define __WCHAR_MIN 0 /* min value for a wchar_t */ +#define __WCHAR_MAX __UINT_MAX /* max value for a wchar_t */ + +#endif /* !_MACHINE__TYPES_H_ */ diff --git a/sys/arm/include/acle-compat.h b/sys/arm/include/acle-compat.h new file mode 100644 index 000000000000..93e965a04795 --- /dev/null +++ b/sys/arm/include/acle-compat.h @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2014 ARM Ltd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef __ARM_ARCH + +/* ACLE standardises a set of pre-defines that describe the ARM architecture. + These were mostly implemented in GCC around GCC-4.8; older versions + have no, or only partial support. To provide a level of backwards + compatibility we try to work out what the definitions should be, given + the older pre-defines that GCC did produce. This isn't complete, but + it should be enough for use by routines that depend on this header. */ + +/* No need to handle ARMv8, GCC had ACLE support before that. */ + +#define __ARM_ACLE 101 + +# ifdef __ARM_ARCH_7__ +/* The common subset of ARMv7 in all profiles. */ +# define __ARM_ARCH 7 +# define __ARM_ARCH_ISA_THUMB 2 +# define __ARM_FEATURE_CLZ +# define __ARM_FEATURE_LDREX 7 +# define __ARM_FEATURE_UNALIGNED +# endif + +# if defined (__ARM_ARCH_7A__) || defined (__ARM_ARCH_7R__) +# define __ARM_ARCH 7 +# define __ARM_ARCH_ISA_THUMB 2 +# define __ARM_ARCH_ISA_ARM +# define __ARM_FEATURE_CLZ +# define __ARM_FEATURE_SIMD32 +# define __ARM_FEATURE_DSP +# define __ARM_FEATURE_QBIT +# define __ARM_FEATURE_SAT +# define __ARM_FEATURE_LDREX 15 +# define __ARM_FEATURE_UNALIGNED +# ifdef __ARM_ARCH_7A__ +# define __ARM_ARCH_PROFILE 'A' +# else +# define __ARM_ARCH_PROFILE 'R' +# endif +# endif + +# ifdef __ARM_ARCH_7EM__ +# define __ARM_ARCH 7 +# define __ARM_ARCH_ISA_THUMB 2 +# define __ARM_FEATURE_CLZ +# define __ARM_FEATURE_SIMD32 +# define __ARM_FEATURE_DSP +# define __ARM_FEATURE_QBIT +# define __ARM_FEATURE_SAT +# define __ARM_FEATURE_LDREX 7 +# define __ARM_FEATURE_UNALIGNED +# define __ARM_ARCH_PROFILE 'M' +# endif + +# ifdef __ARM_ARCH_7M__ +# define __ARM_ARCH 7 +# define __ARM_ARCH_ISA_THUMB 2 +# define __ARM_FEATURE_CLZ +# define __ARM_FEATURE_QBIT +# define __ARM_FEATURE_SAT +# define __ARM_FEATURE_LDREX 7 +# define __ARM_FEATURE_UNALIGNED +# define __ARM_ARCH_PROFILE 'M' +# endif + +# ifdef __ARM_ARCH_6T2__ +# define __ARM_ARCH 6 +# define __ARM_ARCH_ISA_THUMB 2 +# define __ARM_ARCH_ISA_ARM +# define __ARM_FEATURE_CLZ +# define __ARM_FEATURE_SIMD32 +# define __ARM_FEATURE_DSP +# define __ARM_FEATURE_QBIT +# define __ARM_FEATURE_SAT +# define __ARM_FEATURE_LDREX 4 +# define __ARM_FEATURE_UNALIGNED +# endif + +# ifdef __ARM_ARCH_6M__ +# define __ARM_ARCH 6 +# define __ARM_ARCH_ISA_THUMB 1 +# define __ARM_ARCH_PROFILE 'M' +# endif + +# if defined (__ARM_ARCH_6__) || defined (__ARM_ARCH_6J__) \ + || defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6Z__) \ + || defined (__ARM_ARCH_6ZK__) +# define __ARM_ARCH 6 +# define __ARM_ARCH_ISA_THUMB 1 +# define __ARM_ARCH_ISA_ARM +# define __ARM_FEATURE_CLZ +# define __ARM_FEATURE_SIMD32 +# define __ARM_FEATURE_DSP +# define __ARM_FEATURE_QBIT +# define __ARM_FEATURE_SAT +# define __ARM_FEATURE_UNALIGNED +# ifndef __thumb__ +# if defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6ZK__) +# define __ARM_FEATURE_LDREX 15 +# else +# define __ARM_FEATURE_LDREX 4 +# endif +# endif +# endif + +# if defined (__ARM_ARCH_5TE__) || defined (__ARM_ARCH_5E__) +# define __ARM_ARCH 5 +# define __ARM_ARCH_ISA_ARM +# ifdef __ARM_ARCH_5TE__ +# define __ARM_ARCH_ISA_THUMB 1 +# endif +# define __ARM_FEATURE_CLZ +# define __ARM_FEATURE_DSP +# endif + +# if defined (__ARM_ARCH_5T__) || defined (__ARM_ARCH_5__) +# define __ARM_ARCH 5 +# define __ARM_ARCH_ISA_ARM +# ifdef __ARM_ARCH_5TE__ +# define __ARM_ARCH_ISA_THUMB 1 +# endif +# define __ARM_FEATURE_CLZ +# endif + +# ifdef __ARM_ARCH_4T__ +# define __ARM_ARCH 4 +# define __ARM_ARCH_ISA_ARM +# define __ARM_ARCH_ISA_THUMB 1 +# endif + +# ifdef __ARM_ARCH_4__ +# define __ARM_ARCH 4 +# define __ARM_ARCH_ISA_ARM +# endif + +# if defined (__ARM_ARCH_3__) || defined (__ARM_ARCH_3M__) +# define __ARM_ARCH 3 +# define __ARM_ARCH_ISA_ARM +# endif + +# ifdef __ARM_ARCH_2__ +# define __ARM_ARCH 2 +# define __ARM_ARCH_ISA_ARM +# endif + +# ifdef __ARMEB__ +# define __ARM_BIG_ENDIAN +# endif + +/* If we still don't know what the target architecture is, then we're + probably not using GCC. */ +# ifndef __ARM_ARCH +# error Unable to determine architecture version. +# endif + +#endif /* __ARM_ARCH */ diff --git a/sys/arm/include/armreg.h b/sys/arm/include/armreg.h new file mode 100644 index 000000000000..02fad3a7fd59 --- /dev/null +++ b/sys/arm/include/armreg.h @@ -0,0 +1,458 @@ +/* $NetBSD: armreg.h,v 1.37 2007/01/06 00:50:54 christos Exp $ */ + +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (c) 1998, 2001 Ben Harris + * Copyright (c) 1994-1996 Mark Brinicombe. + * Copyright (c) 1994 Brini. + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Brini. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef MACHINE_ARMREG_H +#define MACHINE_ARMREG_H + +#ifndef _SYS_CDEFS_H_ +#error Please include sys/cdefs.h before including machine/armreg.h +#endif + +#define INSN_SIZE 4 +#define INSN_COND_MASK 0xf0000000 /* Condition mask */ +#define PSR_MODE 0x0000001f /* mode mask */ +#define PSR_USR32_MODE 0x00000010 +#define PSR_FIQ32_MODE 0x00000011 +#define PSR_IRQ32_MODE 0x00000012 +#define PSR_SVC32_MODE 0x00000013 +#define PSR_MON32_MODE 0x00000016 +#define PSR_ABT32_MODE 0x00000017 +#define PSR_HYP32_MODE 0x0000001a +#define PSR_UND32_MODE 0x0000001b +#define PSR_SYS32_MODE 0x0000001f +#define PSR_32_MODE 0x00000010 +#define PSR_T 0x00000020 /* Instruction set bit */ +#define PSR_F 0x00000040 /* FIQ disable bit */ +#define PSR_I 0x00000080 /* IRQ disable bit */ +#define PSR_A 0x00000100 /* Imprecise abort bit */ +#define PSR_E 0x00000200 /* Data endianess bit */ +#define PSR_GE 0x000f0000 /* Greater than or equal to bits */ +#define PSR_J 0x01000000 /* Java bit */ +#define PSR_Q 0x08000000 /* Sticky overflow bit */ +#define PSR_V 0x10000000 /* Overflow bit */ +#define PSR_C 0x20000000 /* Carry bit */ +#define PSR_Z 0x40000000 /* Zero bit */ +#define PSR_N 0x80000000 /* Negative bit */ +#define PSR_FLAGS 0xf0000000 /* Flags mask. */ + +/* The high-order byte is always the implementor */ +#define CPU_ID_IMPLEMENTOR_MASK 0xff000000 +#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ +#define CPU_ID_DEC 0x44000000 /* 'D' */ +#define CPU_ID_MOTOROLA 0x4D000000 /* 'M' */ +#define CPU_ID_QUALCOM 0x51000000 /* 'Q' */ +#define CPU_ID_TI 0x54000000 /* 'T' */ +#define CPU_ID_MARVELL 0x56000000 /* 'V' */ +#define CPU_ID_INTEL 0x69000000 /* 'i' */ +#define CPU_ID_FARADAY 0x66000000 /* 'f' */ + +#define CPU_ID_VARIANT_SHIFT 20 +#define CPU_ID_VARIANT_MASK 0x00f00000 + +/* How to decide what format the CPUID is in. */ +#define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) +#define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) +#define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) + +/* On recent ARMs this byte holds the architecture and variant (sub-model) */ +#define CPU_ID_ARCH_MASK 0x000f0000 +#define CPU_ID_ARCH_V3 0x00000000 +#define CPU_ID_ARCH_V4 0x00010000 +#define CPU_ID_ARCH_V4T 0x00020000 +#define CPU_ID_ARCH_V5 0x00030000 +#define CPU_ID_ARCH_V5T 0x00040000 +#define CPU_ID_ARCH_V5TE 0x00050000 +#define CPU_ID_ARCH_V5TEJ 0x00060000 +#define CPU_ID_ARCH_V6 0x00070000 +#define CPU_ID_CPUID_SCHEME 0x000f0000 + +/* Next three nybbles are part number */ +#define CPU_ID_PARTNO_MASK 0x0000fff0 + +/* Intel XScale has sub fields in part number */ +#define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ +#define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ +#define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ + +/* And finally, the revision number. */ +#define CPU_ID_REVISION_MASK 0x0000000f + +/* Individual CPUs are probably best IDed by everything but the revision. */ +#define CPU_ID_CPU_MASK 0xfffffff0 + +/* ARM9 and later CPUs */ +#define CPU_ID_ARM920T 0x41129200 +#define CPU_ID_ARM920T_ALT 0x41009200 +#define CPU_ID_ARM922T 0x41029220 +#define CPU_ID_ARM926EJS 0x41069260 +#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ +#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ +#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ +#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ +#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ +#define CPU_ID_ARM1022ES 0x4105a220 +#define CPU_ID_ARM1026EJS 0x4106a260 +#define CPU_ID_ARM1136JS 0x4107b360 +#define CPU_ID_ARM1136JSR1 0x4117b360 +#define CPU_ID_ARM1176JZS 0x410fb760 + +/* CPUs that follow the CPUID scheme */ +#define CPU_ID_SCHEME_MASK \ + (CPU_ID_IMPLEMENTOR_MASK | CPU_ID_ARCH_MASK | CPU_ID_PARTNO_MASK) + +#define CPU_ID_CORTEXA5 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc050) +#define CPU_ID_CORTEXA7 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc070) +#define CPU_ID_CORTEXA8 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc080) +#define CPU_ID_CORTEXA8R1 (CPU_ID_CORTEXA8 | (1 << CPU_ID_VARIANT_SHIFT)) +#define CPU_ID_CORTEXA8R2 (CPU_ID_CORTEXA8 | (2 << CPU_ID_VARIANT_SHIFT)) +#define CPU_ID_CORTEXA8R3 (CPU_ID_CORTEXA8 | (3 << CPU_ID_VARIANT_SHIFT)) +#define CPU_ID_CORTEXA9 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc090) +#define CPU_ID_CORTEXA9R1 (CPU_ID_CORTEXA9 | (1 << CPU_ID_VARIANT_SHIFT)) +#define CPU_ID_CORTEXA9R2 (CPU_ID_CORTEXA9 | (2 << CPU_ID_VARIANT_SHIFT)) +#define CPU_ID_CORTEXA9R3 (CPU_ID_CORTEXA9 | (3 << CPU_ID_VARIANT_SHIFT)) +#define CPU_ID_CORTEXA9R4 (CPU_ID_CORTEXA9 | (4 << CPU_ID_VARIANT_SHIFT)) +/* XXX: Cortex-A12 is the old name for this part, it has been renamed the A17 */ +#define CPU_ID_CORTEXA12 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc0d0) +#define CPU_ID_CORTEXA12R0 (CPU_ID_CORTEXA12 | (0 << CPU_ID_VARIANT_SHIFT)) +#define CPU_ID_CORTEXA15 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc0f0) +#define CPU_ID_CORTEXA15R0 (CPU_ID_CORTEXA15 | (0 << CPU_ID_VARIANT_SHIFT)) +#define CPU_ID_CORTEXA15R1 (CPU_ID_CORTEXA15 | (1 << CPU_ID_VARIANT_SHIFT)) +#define CPU_ID_CORTEXA15R2 (CPU_ID_CORTEXA15 | (2 << CPU_ID_VARIANT_SHIFT)) +#define CPU_ID_CORTEXA15R3 (CPU_ID_CORTEXA15 | (3 << CPU_ID_VARIANT_SHIFT)) +#define CPU_ID_CORTEXA53 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xd030) +#define CPU_ID_CORTEXA57 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xd070) +#define CPU_ID_CORTEXA72 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xd080) + +#define CPU_ID_KRAIT300 (CPU_ID_QUALCOM | CPU_ID_CPUID_SCHEME | 0x06f0) +/* Snapdragon S4 Pro/APQ8064 */ +#define CPU_ID_KRAIT300R0 (CPU_ID_KRAIT300 | (0 << CPU_ID_VARIANT_SHIFT)) +#define CPU_ID_KRAIT300R1 (CPU_ID_KRAIT300 | (1 << CPU_ID_VARIANT_SHIFT)) + +#define CPU_ID_TI925T 0x54029250 +#define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */ +#define CPU_ID_MV88FR331 0x56153310 /* Marvell Feroceon 88FR331 Core */ +#define CPU_ID_MV88FR571_VD 0x56155710 /* Marvell Feroceon 88FR571-VD Core (ID from datasheet) */ + +/* + * LokiPlus core has also ID set to 0x41159260 and this define cause execution of unsupported + * L2-cache instructions so need to disable it. 0x41159260 is a generic ARM926E-S ID. + */ +#ifdef SOC_MV_LOKIPLUS +#define CPU_ID_MV88FR571_41 0x00000000 +#else +#define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */ +#endif + +#define CPU_ID_MV88SV581X_V7 0x561F5810 /* Marvell Sheeva 88SV581x v7 Core */ +#define CPU_ID_MV88SV584X_V7 0x562F5840 /* Marvell Sheeva 88SV584x v7 Core */ +/* Marvell's CPUIDs with ARM ID in implementor field */ +#define CPU_ID_ARM_88SV581X_V7 0x413FC080 /* Marvell Sheeva 88SV581x v7 Core */ + +#define CPU_ID_FA526 0x66015260 +#define CPU_ID_FA626TE 0x66056260 +#define CPU_ID_80200 0x69052000 +#define CPU_ID_PXA250 0x69052100 /* sans core revision */ +#define CPU_ID_PXA210 0x69052120 +#define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ +#define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ +#define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ +#define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ +#define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ +#define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ +#define CPU_ID_PXA27X 0x69054110 +#define CPU_ID_80321_400 0x69052420 +#define CPU_ID_80321_600 0x69052430 +#define CPU_ID_80321_400_B0 0x69052c20 +#define CPU_ID_80321_600_B0 0x69052c30 +#define CPU_ID_80219_400 0x69052e20 /* A0 stepping/revision. */ +#define CPU_ID_80219_600 0x69052e30 /* A0 stepping/revision. */ +#define CPU_ID_81342 0x69056810 +#define CPU_ID_IXP425 0x690541c0 +#define CPU_ID_IXP425_533 0x690541c0 +#define CPU_ID_IXP425_400 0x690541d0 +#define CPU_ID_IXP425_266 0x690541f0 +#define CPU_ID_IXP435 0x69054040 +#define CPU_ID_IXP465 0x69054200 + +/* CPUID registers */ +#define ARM_PFR0_ARM_ISA_MASK 0x0000000f + +#define ARM_PFR0_THUMB_MASK 0x000000f0 +#define ARM_PFR0_THUMB 0x10 +#define ARM_PFR0_THUMB2 0x30 + +#define ARM_PFR0_JAZELLE_MASK 0x00000f00 +#define ARM_PFR0_THUMBEE_MASK 0x0000f000 + +#define ARM_PFR1_ARMV4_MASK 0x0000000f +#define ARM_PFR1_SEC_EXT_MASK 0x000000f0 +#define ARM_PFR1_MICROCTRL_MASK 0x00000f00 + +/* + * Post-ARM3 CP15 registers: + * + * 1 Control register + * + * 2 Translation Table Base + * + * 3 Domain Access Control + * + * 4 Reserved + * + * 5 Fault Status + * + * 6 Fault Address + * + * 7 Cache/write-buffer Control + * + * 8 TLB Control + * + * 9 Cache Lockdown + * + * 10 TLB Lockdown + * + * 11 Reserved + * + * 12 Reserved + * + * 13 Process ID (for FCSE) + * + * 14 Reserved + * + * 15 Implementation Dependent + */ + +/* Some of the definitions below need cleaning up for V3/V4 architectures */ + +/* CPU control register (CP15 register 1) */ +#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ +#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ +#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ +#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ +#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ +#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ +#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ +#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ +#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ +#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ +#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ +#define CPU_CONTROL_SW_ENABLE 0x00000400 /* SW: SWP instruction enable */ +#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ +#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ +#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ +#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ +#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ +#define CPU_CONTROL_HAF_ENABLE 0x00020000 /* HA: Hardware Access Flag Enable */ +#define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ +#define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ +#define CPU_CONTROL_V6_EXTPAGE 0x00800000 /* XP: ARMv6 extended page tables */ +#define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */ +#define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */ +#define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */ +#define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */ +#define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: TEX Remap*/ +#define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access Flag enable */ +#define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */ + +#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE + +/* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */ +#define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */ +#define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ +#define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */ +#define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */ +#define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ +#define ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */ +#define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */ +#define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */ + +/* ARM1136 Auxiliary Control Register (CP15 register 1, opcode2 1) */ +#define ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */ + /* This is an undocumented flag + * used to work around a cache bug + * in r0 steppings. See errata + * 364296. + */ +/* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */ +#define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */ +#define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */ +#define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */ +#define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */ + +/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */ +#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ +#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ +/* Note: XSCale core 3 uses those for LLR DCcahce attributes */ +#define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ +#define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ +#define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ +#define XSCALE_AUXCTL_MD_MASK 0x00000030 + +/* Xscale Core 3 only */ +#define XSCALE_AUXCTL_LLR 0x00000400 /* Enable L2 for LLR Cache */ + +/* Marvell Extra Features Register (CP15 register 1, opcode2 0) */ +#define MV_DC_REPLACE_LOCK 0x80000000 /* Replace DCache Lock */ +#define MV_DC_STREAM_ENABLE 0x20000000 /* DCache Streaming Switch */ +#define MV_WA_ENABLE 0x10000000 /* Enable Write Allocate */ +#define MV_L2_PREFETCH_DISABLE 0x01000000 /* L2 Cache Prefetch Disable */ +#define MV_L2_INV_EVICT_ERR 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */ +#define MV_L2_ENABLE 0x00400000 /* L2 Cache enable */ +#define MV_IC_REPLACE_LOCK 0x00080000 /* Replace ICache Lock */ +#define MV_BGH_ENABLE 0x00040000 /* Branch Global History Register Enable */ +#define MV_BTB_DISABLE 0x00020000 /* Branch Target Buffer Disable */ +#define MV_L1_PARERR_ENABLE 0x00010000 /* L1 Parity Error Enable */ + +/* Cache type register definitions */ +#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ +#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ +#define CPU_CT_S (1U << 24) /* split cache */ +#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ +#define CPU_CT_FORMAT(x) ((x) >> 29) +/* Cache type register definitions for ARM v7 */ +#define CPU_CT_IMINLINE(x) ((x) & 0xf) /* I$ min line size */ +#define CPU_CT_DMINLINE(x) (((x) >> 16) & 0xf) /* D$ min line size */ + +#define CPU_CT_CTYPE_WT 0 /* write-through */ +#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ +#define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ +#define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ +#define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ + +#define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ +#define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ +#define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ +#define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ + +#define CPU_CT_ARMV7 0x4 +/* ARM v7 Cache type definitions */ +#define CPUV7_CT_CTYPE_WT (1U << 31) +#define CPUV7_CT_CTYPE_WB (1 << 30) +#define CPUV7_CT_CTYPE_RA (1 << 29) +#define CPUV7_CT_CTYPE_WA (1 << 28) + +#define CPUV7_CT_xSIZE_LEN(x) ((x) & 0x7) /* line size */ +#define CPUV7_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x3ff) /* associativity */ +#define CPUV7_CT_xSIZE_SET(x) (((x) >> 13) & 0x7fff) /* num sets */ + +#define CPUV7_L2CTLR_NPROC_SHIFT 24 +#define CPUV7_L2CTLR_NPROC(r) ((((r) >> CPUV7_L2CTLR_NPROC_SHIFT) & 3) + 1) + +#define CPU_CLIDR_CTYPE(reg,x) (((reg) >> ((x) * 3)) & 0x7) +#define CPU_CLIDR_LOUIS(reg) (((reg) >> 21) & 0x7) +#define CPU_CLIDR_LOC(reg) (((reg) >> 24) & 0x7) +#define CPU_CLIDR_LOUU(reg) (((reg) >> 27) & 0x7) + +#define CACHE_ICACHE 1 +#define CACHE_DCACHE 2 +#define CACHE_SEP_CACHE 3 +#define CACHE_UNI_CACHE 4 + +/* Fault status register definitions */ +#define FAULT_USER 0x10 + +#define FAULT_ALIGN 0x001 /* Alignment Fault */ +#define FAULT_DEBUG 0x002 /* Debug Event */ +#define FAULT_ACCESS_L1 0x003 /* Access Bit (L1) */ +#define FAULT_ICACHE 0x004 /* Instruction cache maintenance */ +#define FAULT_TRAN_L1 0x005 /* Translation Fault (L1) */ +#define FAULT_ACCESS_L2 0x006 /* Access Bit (L2) */ +#define FAULT_TRAN_L2 0x007 /* Translation Fault (L2) */ +#define FAULT_EA_PREC 0x008 /* External Abort */ +#define FAULT_DOMAIN_L1 0x009 /* Domain Fault (L1) */ +#define FAULT_DOMAIN_L2 0x00B /* Domain Fault (L2) */ +#define FAULT_EA_TRAN_L1 0x00C /* External Translation Abort (L1) */ +#define FAULT_PERM_L1 0x00D /* Permission Fault (L1) */ +#define FAULT_EA_TRAN_L2 0x00E /* External Translation Abort (L2) */ +#define FAULT_PERM_L2 0x00F /* Permission Fault (L2) */ +#define FAULT_TLB_CONFLICT 0x010 /* TLB Conflict Abort */ +#define FAULT_EA_IMPREC 0x016 /* Asynchronous External Abort */ +#define FAULT_PE_IMPREC 0x018 /* Asynchronous Parity Error */ +#define FAULT_PARITY 0x019 /* Parity Error */ +#define FAULT_PE_TRAN_L1 0x01C /* Parity Error on Translation (L1) */ +#define FAULT_PE_TRAN_L2 0x01E /* Parity Error on Translation (L2) */ + +#define FSR_TO_FAULT(fsr) (((fsr) & 0xF) | \ + ((((fsr) & (1 << 10)) >> (10 - 4)))) +#define FSR_LPAE (1 << 9) /* LPAE indicator */ +#define FSR_WNR (1 << 11) /* Write-not-Read access */ +#define FSR_EXT (1 << 12) /* DECERR/SLVERR for external*/ +#define FSR_CM (1 << 13) /* Cache maintenance fault */ + +/* + * Address of the vector page, low and high versions. + */ +#ifndef __ASSEMBLER__ +#define ARM_VECTORS_LOW 0x00000000U +#define ARM_VECTORS_HIGH 0xffff0000U +#else +#define ARM_VECTORS_LOW 0 +#define ARM_VECTORS_HIGH 0xffff0000 +#endif + +/* + * ARM Instructions + * + * 3 3 2 2 2 + * 1 0 9 8 7 0 + * +-------+-------------------------------------------------------+ + * | cond | instruction dependant | + * |c c c c| | + * +-------+-------------------------------------------------------+ + */ + +#define INSN_SIZE 4 /* Always 4 bytes */ +#define INSN_COND_MASK 0xf0000000 /* Condition mask */ +#define INSN_COND_AL 0xe0000000 /* Always condition */ + +/* ARM register defines */ +#define ARM_REG_SIZE 4 +#define ARM_REG_NUM_PC 15 +#define ARM_REG_NUM_LR 14 +#define ARM_REG_NUM_SP 13 + +#define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ + +/* ARM Hypervisor Related Defines */ +#define ARM_CP15_HDCR_HPMN 0x0000001f + +#endif /* !MACHINE_ARMREG_H */ diff --git a/sys/arm/include/asm.h b/sys/arm/include/asm.h new file mode 100644 index 000000000000..1974908b65c1 --- /dev/null +++ b/sys/arm/include/asm.h @@ -0,0 +1,261 @@ +/* $NetBSD: asm.h,v 1.5 2003/08/07 16:26:53 agc Exp $ */ + +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * William Jolitz. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: @(#)asm.h 5.5 (Berkeley) 5/7/91 + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_ASM_H_ +#define _MACHINE_ASM_H_ +#include <sys/cdefs.h> +#include <machine/sysreg.h> + +#define _C_LABEL(x) x +#define _ASM_LABEL(x) x + +#ifndef _ALIGN_TEXT +# define _ALIGN_TEXT .align 2 +#endif + +#ifndef _STANDALONE +#define STOP_UNWINDING .cantunwind +#define _FNSTART .fnstart +#define _FNEND .fnend +#define _SAVE(...) .save __VA_ARGS__ +#else +#define STOP_UNWINDING +#define _FNSTART +#define _FNEND +#define _SAVE(...) +#endif + +/* + * gas/arm uses @ as a single comment character and thus cannot be used here. + * It recognises the # instead of an @ symbol in .type directives. + */ +#define _ASM_TYPE_FUNCTION #function +#define _ASM_TYPE_OBJECT #object + +/* XXX Is this still the right prologue for profiling? */ +#ifdef GPROF +#define _PROF_PROLOGUE \ + mov ip, lr; \ + bl __mcount +#else +#define _PROF_PROLOGUE +#endif + +/* + * EENTRY()/EEND() mark "extra" entry/exit points from a function. + * LEENTRY()/LEEND() are the same for local symbols. + * The unwind info cannot handle the concept of a nested function, or a function + * with multiple .fnstart directives, but some of our assembler code is written + * with multiple labels to allow entry at several points. The EENTRY() macro + * defines such an extra entry point without a new .fnstart, so that it's + * basically just a label that you can jump to. The EEND() macro does nothing + * at all, except document the exit point associated with the same-named entry. + */ +#define GLOBAL(x) .global x + +#ifdef __thumb__ +#define _FUNC_MODE .code 16; .thumb_func +#else +#define _FUNC_MODE .code 32 +#endif + +#define _LEENTRY(x) .type x,_ASM_TYPE_FUNCTION; _FUNC_MODE; x: +#define _LEEND(x) /* nothing */ +#define _EENTRY(x) GLOBAL(x); _LEENTRY(x) +#define _EEND(x) _LEEND(x) + +#define _LENTRY(x) .text; _ALIGN_TEXT; _LEENTRY(x); _FNSTART +#define _LEND(x) .size x, . - x; _FNEND +#define _ENTRY(x) .text; _ALIGN_TEXT; _EENTRY(x); _FNSTART +#define _END(x) _LEND(x) + +#define ENTRY(y) _ENTRY(_C_LABEL(y)); _PROF_PROLOGUE +#define EENTRY(y) _EENTRY(_C_LABEL(y)); +#define ENTRY_NP(y) _ENTRY(_C_LABEL(y)) +#define EENTRY_NP(y) _EENTRY(_C_LABEL(y)) +#define END(y) _END(_C_LABEL(y)) +#define EEND(y) _EEND(_C_LABEL(y)) +#define ASENTRY(y) _ENTRY(_ASM_LABEL(y)); _PROF_PROLOGUE +#define ASLENTRY(y) _LENTRY(_ASM_LABEL(y)); _PROF_PROLOGUE +#define ASEENTRY(y) _EENTRY(_ASM_LABEL(y)); +#define ASLEENTRY(y) _LEENTRY(_ASM_LABEL(y)); +#define ASENTRY_NP(y) _ENTRY(_ASM_LABEL(y)) +#define ASLENTRY_NP(y) _LENTRY(_ASM_LABEL(y)) +#define ASEENTRY_NP(y) _EENTRY(_ASM_LABEL(y)) +#define ASLEENTRY_NP(y) _LEENTRY(_ASM_LABEL(y)) +#define ASEND(y) _END(_ASM_LABEL(y)) +#define ASLEND(y) _LEND(_ASM_LABEL(y)) +#define ASEEND(y) _EEND(_ASM_LABEL(y)) +#define ASLEEND(y) _LEEND(_ASM_LABEL(y)) + +#define ASMSTR .asciz + +#if defined(PIC) +#define PLT_SYM(x) PIC_SYM(x, PLT) +#define GOT_SYM(x) PIC_SYM(x, GOT) +#define GOT_GET(x,got,sym) \ + ldr x, sym; \ + ldr x, [x, got] +#define GOT_INIT(got,gotsym,pclabel) \ + ldr got, gotsym; \ + pclabel: add got, pc +#ifdef __thumb__ +#define GOT_INITSYM(gotsym,pclabel) \ + .align 2; \ + gotsym: .word _C_LABEL(_GLOBAL_OFFSET_TABLE_) - (pclabel+4) +#else +#define GOT_INITSYM(gotsym,pclabel) \ + .align 2; \ + gotsym: .word _C_LABEL(_GLOBAL_OFFSET_TABLE_) - (pclabel+8) +#endif + +#ifdef __STDC__ +#define PIC_SYM(x,y) x ## ( ## y ## ) +#else +#define PIC_SYM(x,y) x/**/(/**/y/**/) +#endif + +#else +#define PLT_SYM(x) x +#define GOT_SYM(x) x +#define GOT_GET(x,got,sym) \ + ldr x, sym; +#define GOT_INIT(got,gotsym,pclabel) +#define GOT_INITSYM(gotsym,pclabel) +#define PIC_SYM(x,y) x +#endif /* PIC */ + +#undef __FBSDID +#if !defined(lint) && !defined(STRIP_FBSDID) +#define __FBSDID(s) .ident s +#else +#define __FBSDID(s) /* nothing */ +#endif + +#define WEAK_ALIAS(alias,sym) \ + .weak alias; \ + alias = sym + +#ifdef __STDC__ +#define WARN_REFERENCES(sym,msg) \ + .stabs msg ## ,30,0,0,0 ; \ + .stabs __STRING(_C_LABEL(sym)) ## ,1,0,0,0 +#else +#define WARN_REFERENCES(sym,msg) \ + .stabs msg,30,0,0,0 ; \ + .stabs __STRING(sym),1,0,0,0 +#endif /* __STDC__ */ + +/* Exactly one of the __ARM_ARCH_*__ macros will be defined by the compiler. */ +/* The _ARM_ARCH_* macros are deprecated and will be removed soon. */ +/* This should be moved into another header so it can be used in + * both asm and C code. machine/asm.h cannot be included in C code. */ +#if defined (__ARM_ARCH_7__) || defined (__ARM_ARCH_7A__) +#define _ARM_ARCH_7 +#define _HAVE_ARMv7_INSTRUCTIONS 1 +#endif + +#if defined (_HAVE_ARMv7_INSTRUCTIONS) || defined (__ARM_ARCH_6__) || \ + defined (__ARM_ARCH_6J__) || defined (__ARM_ARCH_6K__) || \ + defined (__ARM_ARCH_6KZ__) || \ + defined (__ARM_ARCH_6Z__) || defined (__ARM_ARCH_6ZK__) +#define _ARM_ARCH_6 +#define _HAVE_ARMv6_INSTRUCTIONS 1 +#endif + +#if defined (_HAVE_ARMv6_INSTRUCTIONS) || defined (__ARM_ARCH_5TE__) || \ + defined (__ARM_ARCH_5TEJ__) || defined (__ARM_ARCH_5E__) +#define _ARM_ARCH_5E +#define _HAVE_ARMv5E_INSTRUCTIONS 1 +#endif + +#if defined (_HAVE_ARMv5E_INSTRUCTIONS) || defined (__ARM_ARCH_5__) || \ + defined (__ARM_ARCH_5T__) +#define _ARM_ARCH_5 +#define _HAVE_ARMv5_INSTRUCTIONS 1 +#endif + +#if defined (_HAVE_ARMv5_INSTRUCTIONS) || defined (__ARM_ARCH_4T__) +#define _ARM_ARCH_4T +#define _HAVE_ARMv4T_INSTRUCTIONS 1 +#endif + +/* FreeBSD requires ARMv4, so this is always set. */ +#define _HAVE_ARMv4_INSTRUCTIONS 1 + +#if defined (_HAVE_ARMv4T_INSTRUCTIONS) +# define RET bx lr +# define RETeq bxeq lr +# define RETne bxne lr +# define RETc(c) bx##c lr +#else +# define RET mov pc, lr +# define RETeq moveq pc, lr +# define RETne movne pc, lr +# define RETc(c) mov##c pc, lr +#endif + +#if __ARM_ARCH >= 7 +#define ISB isb +#define DSB dsb +#define DMB dmb +#define WFI wfi + +#if defined(__ARM_ARCH_7VE__) || defined(__clang__) +#define MSR_ELR_HYP(regnum) msr elr_hyp, lr +#define ERET eret +#else +#define MSR_ELR_HYP(regnum) .word (0xe12ef300 | regnum) +#define ERET .word 0xe160006e +#endif + +#elif __ARM_ARCH == 6 +#define ISB mcr CP15_CP15ISB +#define DSB mcr CP15_CP15DSB +#define DMB mcr CP15_CP15DMB +#define WFI mcr CP15_CP15WFI +#else +#define ISB mcr CP15_CP15ISB +#define DSB mcr CP15_CP15DSB /* DSB and DMB are the */ +#define DMB mcr CP15_CP15DSB /* same prior to v6.*/ +/* No form of WFI available on v4, define nothing to get an error on use. */ +#endif + +#endif /* !_MACHINE_ASM_H_ */ diff --git a/sys/arm/include/asmacros.h b/sys/arm/include/asmacros.h new file mode 100644 index 000000000000..a41af82febba --- /dev/null +++ b/sys/arm/include/asmacros.h @@ -0,0 +1,59 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2012 Olivier Houchard <cognet@FreeBSD.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_ASMACROS_H_ +#define _MACHINE_ASMACROS_H_ + +#include <machine/asm.h> + +#ifdef _KERNEL + +#ifdef LOCORE + +#define GET_CURTHREAD_PTR(tmp) \ + mrc p15, 0, tmp, c13, c0, 4 + +#define ELFNOTE(section, type, vendor, desctype, descdata...) \ + .pushsection section ; \ + .balign 4 ; \ + .long 2f - 1f /* namesz */ ; \ + .long 4f - 3f /* descsz */ ; \ + .long type /* type */ ; \ + 1: .asciz vendor /* vendor name */ ; \ + 2: .balign 4 ; \ + 3: desctype descdata /* node */ ; \ + 4: .balign 4 ; \ + .popsection + +#endif /* LOCORE */ + +#endif /* _KERNEL */ + +#endif /* !_MACHINE_ASMACROS_H_ */ diff --git a/sys/arm/include/atags.h b/sys/arm/include/atags.h new file mode 100644 index 000000000000..baf39b5c0c69 --- /dev/null +++ b/sys/arm/include/atags.h @@ -0,0 +1,130 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2012 M. Warner Losh <imp@FreeBSD.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef __MACHINE_ATAGS_H__ +#define __MACHINE_ATAGS_H__ + +/* + * Linux boot ABI compatable ATAG definitions. All these structures + * assume tight packing, but since they are all uint32_t's, I've not + * bothered to do the usual alignment dance. + */ + +#define LBABI_MAX_COMMAND_LINE 1024 + +struct arm_lbabi_header +{ + uint32_t size; /* Size of this node, including header */ + uint32_t tag; /* Node type */ +}; + +#define ATAG_NONE 0x00000000 /* End of atags list */ +#define ATAG_CORE 0x54410001 /* List must start with ATAG_CORE */ +#define ATAG_MEM 0x54410002 /* Multiple ATAG_MEM nodes possible */ +#define ATAG_VIDEOTEXT 0x54410003 /* Video parameters */ +#define ATAG_RAMDISK 0x54410004 /* Describes the ramdisk parameters */ +#define ATAG_INITRD 0x54410005 /* Deprecated ramdisk -- used va not pa */ +#define ATAG_INITRD2 0x54420005 /* compressed ramdisk image */ +#define ATAG_SERIAL 0x54410006 /* 64-bits of serial number */ +#define ATAG_REVISION 0x54410007 /* Board revision */ +#define ATAG_VIDEOLFB 0x54410008 /* vesafb framebuffer */ +#define ATAG_CMDLINE 0x54410009 /* Command line */ + +/* + * ATAG_CORE data + */ +struct arm_lbabi_core +{ + uint32_t flags; /* bit 0 == read-only */ + uint32_t pagesize; + uint32_t rootdev; +}; + +/* + * ATAG_MEM data -- Can be more than one to describe different + * banks. + */ +struct arm_lbabi_mem32 +{ + uint32_t size; + uint32_t start; /* start of physical memory */ +}; + +/* + * ATAG_INITRD2 - Compressed ramdisk image details + */ +struct arm_lbabi_initrd +{ + uint32_t start; /* pa of start */ + uint32_t size; /* How big the ram disk is */ +}; + +/* + * ATAG_SERIAL - serial number + */ +struct arm_lbabi_serial_number +{ + uint32_t low; + uint32_t high; +}; + +/* + * ATAG_REVISION - board revision + */ +struct arm_lbabi_revision +{ + uint32_t rev; +}; + +/* + * ATAG_CMDLINE - Command line from uboot + */ +struct arm_lbabi_command_line +{ + char command[1]; /* Minimum command length */ +}; + +struct arm_lbabi_tag +{ + struct arm_lbabi_header tag_hdr; + union { + struct arm_lbabi_core tag_core; + struct arm_lbabi_mem32 tag_mem; + struct arm_lbabi_initrd tag_initrd; + struct arm_lbabi_serial_number tag_sn; + struct arm_lbabi_revision tag_rev; + struct arm_lbabi_command_line tag_cmd; + } u; +}; + +#define ATAG_TAG(a) (a)->tag_hdr.tag +#define ATAG_SIZE(a) ((a)->tag_hdr.size * sizeof(uint32_t)) +#define ATAG_NEXT(a) (struct arm_lbabi_tag *)((char *)(a) + ATAG_SIZE(a)) + +#endif /* __MACHINE_ATAGS_H__ */ diff --git a/sys/arm/include/atomic-v6.h b/sys/arm/include/atomic-v6.h new file mode 100644 index 000000000000..b81ad6447ef7 --- /dev/null +++ b/sys/arm/include/atomic-v6.h @@ -0,0 +1,1050 @@ +/* $NetBSD: atomic.h,v 1.1 2002/10/19 12:22:34 bsh Exp $ */ + +/*- + * Copyright (C) 2003-2004 Olivier Houchard + * Copyright (C) 1994-1997 Mark Brinicombe + * Copyright (C) 1994 Brini + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Brini. + * 4. The name of Brini may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_ATOMIC_V6_H_ +#define _MACHINE_ATOMIC_V6_H_ + +#ifndef _MACHINE_ATOMIC_H_ +#error Do not include this file directly, use <machine/atomic.h> +#endif + +#if __ARM_ARCH >= 7 +#define isb() __asm __volatile("isb" : : : "memory") +#define dsb() __asm __volatile("dsb" : : : "memory") +#define dmb() __asm __volatile("dmb" : : : "memory") +#else +#define isb() __asm __volatile("mcr p15, 0, %0, c7, c5, 4" : : "r" (0) : "memory") +#define dsb() __asm __volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0) : "memory") +#define dmb() __asm __volatile("mcr p15, 0, %0, c7, c10, 5" : : "r" (0) : "memory") +#endif + +#define mb() dmb() +#define wmb() dmb() +#define rmb() dmb() + +#define ARM_HAVE_ATOMIC64 + +#define ATOMIC_ACQ_REL_LONG(NAME) \ +static __inline void \ +atomic_##NAME##_acq_long(__volatile u_long *p, u_long v) \ +{ \ + atomic_##NAME##_long(p, v); \ + dmb(); \ +} \ + \ +static __inline void \ +atomic_##NAME##_rel_long(__volatile u_long *p, u_long v) \ +{ \ + dmb(); \ + atomic_##NAME##_long(p, v); \ +} + +#define ATOMIC_ACQ_REL(NAME, WIDTH) \ +static __inline void \ +atomic_##NAME##_acq_##WIDTH(__volatile uint##WIDTH##_t *p, uint##WIDTH##_t v)\ +{ \ + atomic_##NAME##_##WIDTH(p, v); \ + dmb(); \ +} \ + \ +static __inline void \ +atomic_##NAME##_rel_##WIDTH(__volatile uint##WIDTH##_t *p, uint##WIDTH##_t v)\ +{ \ + dmb(); \ + atomic_##NAME##_##WIDTH(p, v); \ +} + +static __inline void +atomic_add_32(volatile uint32_t *p, uint32_t val) +{ + uint32_t tmp = 0, tmp2 = 0; + + __asm __volatile( + "1: ldrex %0, [%2] \n" + " add %0, %0, %3 \n" + " strex %1, %0, [%2] \n" + " cmp %1, #0 \n" + " it ne \n" + " bne 1b \n" + : "=&r" (tmp), "+r" (tmp2) + ,"+r" (p), "+r" (val) : : "cc", "memory"); +} + +static __inline void +atomic_add_64(volatile uint64_t *p, uint64_t val) +{ + uint64_t tmp; + uint32_t exflag; + + __asm __volatile( + "1: \n" + " ldrexd %Q[tmp], %R[tmp], [%[ptr]] \n" + " adds %Q[tmp], %Q[val] \n" + " adc %R[tmp], %R[tmp], %R[val] \n" + " strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]] \n" + " teq %[exf], #0 \n" + " it ne \n" + " bne 1b \n" + : [exf] "=&r" (exflag), + [tmp] "=&r" (tmp) + : [ptr] "r" (p), + [val] "r" (val) + : "cc", "memory"); +} + +static __inline void +atomic_add_long(volatile u_long *p, u_long val) +{ + + atomic_add_32((volatile uint32_t *)p, val); +} + +ATOMIC_ACQ_REL(add, 32) +ATOMIC_ACQ_REL(add, 64) +ATOMIC_ACQ_REL_LONG(add) + +static __inline void +atomic_clear_32(volatile uint32_t *address, uint32_t setmask) +{ + uint32_t tmp = 0, tmp2 = 0; + + __asm __volatile( + "1: ldrex %0, [%2] \n" + " bic %0, %0, %3 \n" + " strex %1, %0, [%2] \n" + " cmp %1, #0 \n" + " it ne \n" + " bne 1b \n" + : "=&r" (tmp), "+r" (tmp2), "+r" (address), "+r" (setmask) + : : "cc", "memory"); +} + +static __inline void +atomic_clear_64(volatile uint64_t *p, uint64_t val) +{ + uint64_t tmp; + uint32_t exflag; + + __asm __volatile( + "1: \n" + " ldrexd %Q[tmp], %R[tmp], [%[ptr]] \n" + " bic %Q[tmp], %Q[val] \n" + " bic %R[tmp], %R[val] \n" + " strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]] \n" + " teq %[exf], #0 \n" + " it ne \n" + " bne 1b \n" + : [exf] "=&r" (exflag), + [tmp] "=&r" (tmp) + : [ptr] "r" (p), + [val] "r" (val) + : "cc", "memory"); +} + +static __inline void +atomic_clear_long(volatile u_long *address, u_long setmask) +{ + + atomic_clear_32((volatile uint32_t *)address, setmask); +} + +ATOMIC_ACQ_REL(clear, 32) +ATOMIC_ACQ_REL(clear, 64) +ATOMIC_ACQ_REL_LONG(clear) + +#define ATOMIC_FCMPSET_CODE(RET, TYPE, SUF) \ + { \ + TYPE tmp; \ + \ + __asm __volatile( \ + "1: ldrex" SUF " %[tmp], [%[ptr]] \n" \ + " ldr" SUF " %[ret], [%[oldv]] \n" \ + " teq %[tmp], %[ret] \n" \ + " ittee ne \n" \ + " str" SUF "ne %[tmp], [%[oldv]] \n" \ + " movne %[ret], #0 \n" \ + " strex" SUF "eq %[ret], %[newv], [%[ptr]] \n" \ + " eorseq %[ret], #1 \n" \ + " beq 1b \n" \ + : [ret] "=&r" (RET), \ + [tmp] "=&r" (tmp) \ + : [ptr] "r" (_ptr), \ + [oldv] "r" (_old), \ + [newv] "r" (_new) \ + : "cc", "memory"); \ + } + +#define ATOMIC_FCMPSET_CODE64(RET) \ + { \ + uint64_t cmp, tmp; \ + \ + __asm __volatile( \ + "1: ldrexd %Q[tmp], %R[tmp], [%[ptr]] \n" \ + " ldrd %Q[cmp], %R[cmp], [%[oldv]] \n" \ + " teq %Q[tmp], %Q[cmp] \n" \ + " it eq \n" \ + " teqeq %R[tmp], %R[cmp] \n" \ + " ittee ne \n" \ + " movne %[ret], #0 \n" \ + " strdne %[cmp], [%[oldv]] \n" \ + " strexdeq %[ret], %Q[newv], %R[newv], [%[ptr]] \n" \ + " eorseq %[ret], #1 \n" \ + " beq 1b \n" \ + : [ret] "=&r" (RET), \ + [cmp] "=&r" (cmp), \ + [tmp] "=&r" (tmp) \ + : [ptr] "r" (_ptr), \ + [oldv] "r" (_old), \ + [newv] "r" (_new) \ + : "cc", "memory"); \ + } + +static __inline int +atomic_fcmpset_8(volatile uint8_t *_ptr, uint8_t *_old, uint8_t _new) +{ + int ret; + + ATOMIC_FCMPSET_CODE(ret, uint8_t, "b"); + return (ret); +} +#define atomic_fcmpset_8 atomic_fcmpset_8 + +static __inline int +atomic_fcmpset_acq_8(volatile uint8_t *_ptr, uint8_t *_old, uint8_t _new) +{ + int ret; + + ATOMIC_FCMPSET_CODE(ret, uint8_t, "b"); + dmb(); + return (ret); +} + +static __inline int +atomic_fcmpset_rel_8(volatile uint8_t *_ptr, uint8_t *_old, uint8_t _new) +{ + int ret; + + dmb(); + ATOMIC_FCMPSET_CODE(ret, uint8_t, "b"); + return (ret); +} + +static __inline int +atomic_fcmpset_16(volatile uint16_t *_ptr, uint16_t *_old, uint16_t _new) +{ + int ret; + + ATOMIC_FCMPSET_CODE(ret, uint16_t, "h"); + return (ret); +} +#define atomic_fcmpset_16 atomic_fcmpset_16 + +static __inline int +atomic_fcmpset_acq_16(volatile uint16_t *_ptr, uint16_t *_old, uint16_t _new) +{ + int ret; + + ATOMIC_FCMPSET_CODE(ret, uint16_t, "h"); + dmb(); + return (ret); +} + +static __inline int +atomic_fcmpset_rel_16(volatile uint16_t *_ptr, uint16_t *_old, uint16_t _new) +{ + int ret; + + dmb(); + ATOMIC_FCMPSET_CODE(ret, uint16_t, "h"); + return (ret); +} + +static __inline int +atomic_fcmpset_32(volatile uint32_t *_ptr, uint32_t *_old, uint32_t _new) +{ + int ret; + + ATOMIC_FCMPSET_CODE(ret, uint32_t, ""); + return (ret); +} + +static __inline int +atomic_fcmpset_acq_32(volatile uint32_t *_ptr, uint32_t *_old, uint32_t _new) +{ + int ret; + + ATOMIC_FCMPSET_CODE(ret, uint32_t, ""); + dmb(); + return (ret); +} + +static __inline int +atomic_fcmpset_rel_32(volatile uint32_t *_ptr, uint32_t *_old, uint32_t _new) +{ + int ret; + + dmb(); + ATOMIC_FCMPSET_CODE(ret, uint32_t, ""); + return (ret); +} + +static __inline int +atomic_fcmpset_long(volatile u_long *_ptr, u_long *_old, u_long _new) +{ + int ret; + + ATOMIC_FCMPSET_CODE(ret, u_long, ""); + return (ret); +} + +static __inline int +atomic_fcmpset_acq_long(volatile u_long *_ptr, u_long *_old, u_long _new) +{ + int ret; + + ATOMIC_FCMPSET_CODE(ret, u_long, ""); + dmb(); + return (ret); +} + +static __inline int +atomic_fcmpset_rel_long(volatile u_long *_ptr, u_long *_old, u_long _new) +{ + int ret; + + dmb(); + ATOMIC_FCMPSET_CODE(ret, u_long, ""); + return (ret); +} + +static __inline int +atomic_fcmpset_64(volatile uint64_t *_ptr, uint64_t *_old, uint64_t _new) +{ + int ret; + + ATOMIC_FCMPSET_CODE64(ret); + return (ret); +} + +static __inline int +atomic_fcmpset_acq_64(volatile uint64_t *_ptr, uint64_t *_old, uint64_t _new) +{ + int ret; + + ATOMIC_FCMPSET_CODE64(ret); + dmb(); + return (ret); +} + +static __inline int +atomic_fcmpset_rel_64(volatile uint64_t *_ptr, uint64_t *_old, uint64_t _new) +{ + int ret; + + dmb(); + ATOMIC_FCMPSET_CODE64(ret); + return (ret); +} + +#define ATOMIC_CMPSET_CODE(RET, SUF) \ + { \ + __asm __volatile( \ + "1: ldrex" SUF " %[ret], [%[ptr]] \n" \ + " teq %[ret], %[oldv] \n" \ + " itee ne \n" \ + " movne %[ret], #0 \n" \ + " strex" SUF "eq %[ret], %[newv], [%[ptr]] \n" \ + " eorseq %[ret], #1 \n" \ + " beq 1b \n" \ + : [ret] "=&r" (RET) \ + : [ptr] "r" (_ptr), \ + [oldv] "r" (_old), \ + [newv] "r" (_new) \ + : "cc", "memory"); \ + } + +#define ATOMIC_CMPSET_CODE64(RET) \ + { \ + uint64_t tmp; \ + \ + __asm __volatile( \ + "1: ldrexd %Q[tmp], %R[tmp], [%[ptr]] \n" \ + " teq %Q[tmp], %Q[oldv] \n" \ + " it eq \n" \ + " teqeq %R[tmp], %R[oldv] \n" \ + " itee ne \n" \ + " movne %[ret], #0 \n" \ + " strexdeq %[ret], %Q[newv], %R[newv], [%[ptr]] \n" \ + " eorseq %[ret], #1 \n" \ + " beq 1b \n" \ + : [ret] "=&r" (RET), \ + [tmp] "=&r" (tmp) \ + : [ptr] "r" (_ptr), \ + [oldv] "r" (_old), \ + [newv] "r" (_new) \ + : "cc", "memory"); \ + } + +static __inline int +atomic_cmpset_8(volatile uint8_t *_ptr, uint8_t _old, uint8_t _new) +{ + int ret; + + ATOMIC_CMPSET_CODE(ret, "b"); + return (ret); +} +#define atomic_cmpset_8 atomic_cmpset_8 + +static __inline int +atomic_cmpset_acq_8(volatile uint8_t *_ptr, uint8_t _old, uint8_t _new) +{ + int ret; + + ATOMIC_CMPSET_CODE(ret, "b"); + dmb(); + return (ret); +} + +static __inline int +atomic_cmpset_rel_8(volatile uint8_t *_ptr, uint8_t _old, uint8_t _new) +{ + int ret; + + dmb(); + ATOMIC_CMPSET_CODE(ret, "b"); + return (ret); +} + +static __inline int +atomic_cmpset_16(volatile uint16_t *_ptr, uint16_t _old, uint16_t _new) +{ + int ret; + + ATOMIC_CMPSET_CODE(ret, "h"); + return (ret); +} +#define atomic_cmpset_16 atomic_cmpset_16 + +static __inline int +atomic_cmpset_acq_16(volatile uint16_t *_ptr, uint16_t _old, uint16_t _new) +{ + int ret; + + ATOMIC_CMPSET_CODE(ret, "h"); + dmb(); + return (ret); +} + +static __inline int +atomic_cmpset_rel_16(volatile uint16_t *_ptr, uint16_t _old, uint16_t _new) +{ + int ret; + + dmb(); + ATOMIC_CMPSET_CODE(ret, "h"); + return (ret); +} + +static __inline int +atomic_cmpset_32(volatile uint32_t *_ptr, uint32_t _old, uint32_t _new) +{ + int ret; + + ATOMIC_CMPSET_CODE(ret, ""); + return (ret); +} + +static __inline int +atomic_cmpset_acq_32(volatile uint32_t *_ptr, uint32_t _old, uint32_t _new) +{ + int ret; + + ATOMIC_CMPSET_CODE(ret, ""); + dmb(); + return (ret); +} + +static __inline int +atomic_cmpset_rel_32(volatile uint32_t *_ptr, uint32_t _old, uint32_t _new) +{ + int ret; + + dmb(); + ATOMIC_CMPSET_CODE(ret, ""); + return (ret); +} + +static __inline int +atomic_cmpset_long(volatile u_long *_ptr, u_long _old, u_long _new) +{ + int ret; + + ATOMIC_CMPSET_CODE(ret, ""); + return (ret); +} + +static __inline int +atomic_cmpset_acq_long(volatile u_long *_ptr, u_long _old, u_long _new) +{ + int ret; + + ATOMIC_CMPSET_CODE(ret, ""); + dmb(); + return (ret); +} + +static __inline int +atomic_cmpset_rel_long(volatile u_long *_ptr, u_long _old, u_long _new) +{ + int ret; + + dmb(); + ATOMIC_CMPSET_CODE(ret, ""); + return (ret); +} + +static __inline int +atomic_cmpset_64(volatile uint64_t *_ptr, uint64_t _old, uint64_t _new) +{ + int ret; + + ATOMIC_CMPSET_CODE64(ret); + return (ret); +} + +static __inline int +atomic_cmpset_acq_64(volatile uint64_t *_ptr, uint64_t _old, uint64_t _new) +{ + int ret; + + ATOMIC_CMPSET_CODE64(ret); + dmb(); + return (ret); +} + +static __inline int +atomic_cmpset_rel_64(volatile uint64_t *_ptr, uint64_t _old, uint64_t _new) +{ + int ret; + + dmb(); + ATOMIC_CMPSET_CODE64(ret); + return (ret); +} + +static __inline uint32_t +atomic_fetchadd_32(volatile uint32_t *p, uint32_t val) +{ + uint32_t tmp = 0, tmp2 = 0, ret = 0; + + __asm __volatile( + "1: ldrex %0, [%3] \n" + " add %1, %0, %4 \n" + " strex %2, %1, [%3] \n" + " cmp %2, #0 \n" + " it ne \n" + " bne 1b \n" + : "+r" (ret), "=&r" (tmp), "+r" (tmp2), "+r" (p), "+r" (val) + : : "cc", "memory"); + return (ret); +} + +static __inline uint64_t +atomic_fetchadd_64(volatile uint64_t *p, uint64_t val) +{ + uint64_t ret, tmp; + uint32_t exflag; + + __asm __volatile( + "1: \n" + " ldrexd %Q[ret], %R[ret], [%[ptr]] \n" + " adds %Q[tmp], %Q[ret], %Q[val] \n" + " adc %R[tmp], %R[ret], %R[val] \n" + " strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]] \n" + " teq %[exf], #0 \n" + " it ne \n" + " bne 1b \n" + : [ret] "=&r" (ret), + [exf] "=&r" (exflag), + [tmp] "=&r" (tmp) + : [ptr] "r" (p), + [val] "r" (val) + : "cc", "memory"); + return (ret); +} + +static __inline u_long +atomic_fetchadd_long(volatile u_long *p, u_long val) +{ + + return (atomic_fetchadd_32((volatile uint32_t *)p, val)); +} + +static __inline uint32_t +atomic_load_acq_32(volatile uint32_t *p) +{ + uint32_t v; + + v = *p; + dmb(); + return (v); +} + +static __inline uint64_t +atomic_load_64(volatile uint64_t *p) +{ + uint64_t ret; + + /* + * The only way to atomically load 64 bits is with LDREXD which puts the + * exclusive monitor into the exclusive state, so reset it to open state + * with CLREX because we don't actually need to store anything. + */ + __asm __volatile( + "ldrexd %Q[ret], %R[ret], [%[ptr]] \n" + "clrex \n" + : [ret] "=&r" (ret) + : [ptr] "r" (p) + : "cc", "memory"); + return (ret); +} + +static __inline uint64_t +atomic_load_acq_64(volatile uint64_t *p) +{ + uint64_t ret; + + ret = atomic_load_64(p); + dmb(); + return (ret); +} + +static __inline u_long +atomic_load_acq_long(volatile u_long *p) +{ + u_long v; + + v = *p; + dmb(); + return (v); +} + +static __inline uint32_t +atomic_readandclear_32(volatile uint32_t *p) +{ + uint32_t ret, tmp = 0, tmp2 = 0; + + __asm __volatile( + "1: ldrex %0, [%3] \n" + " mov %1, #0 \n" + " strex %2, %1, [%3] \n" + " cmp %2, #0 \n" + " it ne \n" + " bne 1b \n" + : "=r" (ret), "=&r" (tmp), "+r" (tmp2), "+r" (p) + : : "cc", "memory"); + return (ret); +} + +static __inline uint64_t +atomic_readandclear_64(volatile uint64_t *p) +{ + uint64_t ret, tmp; + uint32_t exflag; + + __asm __volatile( + "1: \n" + " ldrexd %Q[ret], %R[ret], [%[ptr]] \n" + " mov %Q[tmp], #0 \n" + " mov %R[tmp], #0 \n" + " strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]] \n" + " teq %[exf], #0 \n" + " it ne \n" + " bne 1b \n" + : [ret] "=&r" (ret), + [exf] "=&r" (exflag), + [tmp] "=&r" (tmp) + : [ptr] "r" (p) + : "cc", "memory"); + return (ret); +} + +static __inline u_long +atomic_readandclear_long(volatile u_long *p) +{ + + return (atomic_readandclear_32((volatile uint32_t *)p)); +} + +static __inline void +atomic_set_32(volatile uint32_t *address, uint32_t setmask) +{ + uint32_t tmp = 0, tmp2 = 0; + + __asm __volatile( + "1: ldrex %0, [%2] \n" + " orr %0, %0, %3 \n" + " strex %1, %0, [%2] \n" + " cmp %1, #0 \n" + " it ne \n" + " bne 1b \n" + : "=&r" (tmp), "+r" (tmp2), "+r" (address), "+r" (setmask) + : : "cc", "memory"); +} + +static __inline void +atomic_set_64(volatile uint64_t *p, uint64_t val) +{ + uint64_t tmp; + uint32_t exflag; + + __asm __volatile( + "1: \n" + " ldrexd %Q[tmp], %R[tmp], [%[ptr]] \n" + " orr %Q[tmp], %Q[val] \n" + " orr %R[tmp], %R[val] \n" + " strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]] \n" + " teq %[exf], #0 \n" + " it ne \n" + " bne 1b \n" + : [exf] "=&r" (exflag), + [tmp] "=&r" (tmp) + : [ptr] "r" (p), + [val] "r" (val) + : "cc", "memory"); +} + +static __inline void +atomic_set_long(volatile u_long *address, u_long setmask) +{ + + atomic_set_32((volatile uint32_t *)address, setmask); +} + +ATOMIC_ACQ_REL(set, 32) +ATOMIC_ACQ_REL(set, 64) +ATOMIC_ACQ_REL_LONG(set) + +static __inline void +atomic_subtract_32(volatile uint32_t *p, uint32_t val) +{ + uint32_t tmp = 0, tmp2 = 0; + + __asm __volatile( + "1: ldrex %0, [%2] \n" + " sub %0, %0, %3 \n" + " strex %1, %0, [%2] \n" + " cmp %1, #0 \n" + " it ne \n" + " bne 1b \n" + : "=&r" (tmp), "+r" (tmp2), "+r" (p), "+r" (val) + : : "cc", "memory"); +} + +static __inline void +atomic_subtract_64(volatile uint64_t *p, uint64_t val) +{ + uint64_t tmp; + uint32_t exflag; + + __asm __volatile( + "1: \n" + " ldrexd %Q[tmp], %R[tmp], [%[ptr]] \n" + " subs %Q[tmp], %Q[val] \n" + " sbc %R[tmp], %R[tmp], %R[val] \n" + " strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]] \n" + " teq %[exf], #0 \n" + " it ne \n" + " bne 1b \n" + : [exf] "=&r" (exflag), + [tmp] "=&r" (tmp) + : [ptr] "r" (p), + [val] "r" (val) + : "cc", "memory"); +} + +static __inline void +atomic_subtract_long(volatile u_long *p, u_long val) +{ + + atomic_subtract_32((volatile uint32_t *)p, val); +} + +ATOMIC_ACQ_REL(subtract, 32) +ATOMIC_ACQ_REL(subtract, 64) +ATOMIC_ACQ_REL_LONG(subtract) + +static __inline void +atomic_store_64(volatile uint64_t *p, uint64_t val) +{ + uint64_t tmp; + uint32_t exflag; + + /* + * The only way to atomically store 64 bits is with STREXD, which will + * succeed only if paired up with a preceeding LDREXD using the same + * address, so we read and discard the existing value before storing. + */ + __asm __volatile( + "1: \n" + " ldrexd %Q[tmp], %R[tmp], [%[ptr]] \n" + " strexd %[exf], %Q[val], %R[val], [%[ptr]] \n" + " teq %[exf], #0 \n" + " it ne \n" + " bne 1b \n" + : [tmp] "=&r" (tmp), + [exf] "=&r" (exflag) + : [ptr] "r" (p), + [val] "r" (val) + : "cc", "memory"); +} + +static __inline void +atomic_store_rel_32(volatile uint32_t *p, uint32_t v) +{ + + dmb(); + *p = v; +} + +static __inline void +atomic_store_rel_64(volatile uint64_t *p, uint64_t val) +{ + + dmb(); + atomic_store_64(p, val); +} + +static __inline void +atomic_store_rel_long(volatile u_long *p, u_long v) +{ + + dmb(); + *p = v; +} + +static __inline int +atomic_testandclear_32(volatile uint32_t *ptr, u_int bit) +{ + int newv, oldv, result; + + __asm __volatile( + " mov ip, #1 \n" + " lsl ip, ip, %[bit] \n" + /* Done with %[bit] as input, reuse below as output. */ + "1: \n" + " ldrex %[oldv], [%[ptr]] \n" + " bic %[newv], %[oldv], ip \n" + " strex %[bit], %[newv], [%[ptr]] \n" + " teq %[bit], #0 \n" + " it ne \n" + " bne 1b \n" + " ands %[bit], %[oldv], ip \n" + " it ne \n" + " movne %[bit], #1 \n" + : [bit] "=&r" (result), + [oldv] "=&r" (oldv), + [newv] "=&r" (newv) + : [ptr] "r" (ptr), + "[bit]" (bit & 0x1f) + : "cc", "ip", "memory"); + + return (result); +} + +static __inline int +atomic_testandclear_int(volatile u_int *p, u_int v) +{ + + return (atomic_testandclear_32((volatile uint32_t *)p, v)); +} + +static __inline int +atomic_testandclear_long(volatile u_long *p, u_int v) +{ + + return (atomic_testandclear_32((volatile uint32_t *)p, v)); +} +#define atomic_testandclear_long atomic_testandclear_long + + +static __inline int +atomic_testandclear_64(volatile uint64_t *p, u_int v) +{ + volatile uint32_t *p32; + + p32 = (volatile uint32_t *)p; + /* + * Assume little-endian, + * atomic_testandclear_32() uses only last 5 bits of v + */ + if ((v & 0x20) != 0) + p32++; + return (atomic_testandclear_32(p32, v)); +} + +static __inline int +atomic_testandset_32(volatile uint32_t *ptr, u_int bit) +{ + int newv, oldv, result; + + __asm __volatile( + " mov ip, #1 \n" + " lsl ip, ip, %[bit] \n" + /* Done with %[bit] as input, reuse below as output. */ + "1: \n" + " ldrex %[oldv], [%[ptr]] \n" + " orr %[newv], %[oldv], ip \n" + " strex %[bit], %[newv], [%[ptr]] \n" + " teq %[bit], #0 \n" + " it ne \n" + " bne 1b \n" + " ands %[bit], %[oldv], ip \n" + " it ne \n" + " movne %[bit], #1 \n" + : [bit] "=&r" (result), + [oldv] "=&r" (oldv), + [newv] "=&r" (newv) + : [ptr] "r" (ptr), + "[bit]" (bit & 0x1f) + : "cc", "ip", "memory"); + + return (result); +} + +static __inline int +atomic_testandset_int(volatile u_int *p, u_int v) +{ + + return (atomic_testandset_32((volatile uint32_t *)p, v)); +} + +static __inline int +atomic_testandset_long(volatile u_long *p, u_int v) +{ + + return (atomic_testandset_32((volatile uint32_t *)p, v)); +} +#define atomic_testandset_long atomic_testandset_long + +static __inline int +atomic_testandset_64(volatile uint64_t *p, u_int v) +{ + volatile uint32_t *p32; + + p32 = (volatile uint32_t *)p; + /* + * Assume little-endian, + * atomic_testandset_32() uses only last 5 bits of v + */ + if ((v & 0x20) != 0) + p32++; + return (atomic_testandset_32(p32, v)); +} + +static __inline uint32_t +atomic_swap_32(volatile uint32_t *p, uint32_t v) +{ + uint32_t ret, exflag; + + __asm __volatile( + "1: ldrex %[ret], [%[ptr]] \n" + " strex %[exf], %[val], [%[ptr]] \n" + " teq %[exf], #0 \n" + " it ne \n" + " bne 1b \n" + : [ret] "=&r" (ret), + [exf] "=&r" (exflag) + : [val] "r" (v), + [ptr] "r" (p) + : "cc", "memory"); + return (ret); +} + +static __inline uint64_t +atomic_swap_64(volatile uint64_t *p, uint64_t v) +{ + uint64_t ret; + uint32_t exflag; + + __asm __volatile( + "1: ldrexd %Q[ret], %R[ret], [%[ptr]] \n" + " strexd %[exf], %Q[val], %R[val], [%[ptr]] \n" + " teq %[exf], #0 \n" + " it ne \n" + " bne 1b \n" + : [ret] "=&r" (ret), + [exf] "=&r" (exflag) + : [val] "r" (v), + [ptr] "r" (p) + : "cc", "memory"); + return (ret); +} + +#undef ATOMIC_ACQ_REL +#undef ATOMIC_ACQ_REL_LONG + +static __inline void +atomic_thread_fence_acq(void) +{ + + dmb(); +} + +static __inline void +atomic_thread_fence_rel(void) +{ + + dmb(); +} + +static __inline void +atomic_thread_fence_acq_rel(void) +{ + + dmb(); +} + +static __inline void +atomic_thread_fence_seq_cst(void) +{ + + dmb(); +} + +#endif /* _MACHINE_ATOMIC_V6_H_ */ diff --git a/sys/arm/include/atomic.h b/sys/arm/include/atomic.h new file mode 100644 index 000000000000..f5d98d920ebd --- /dev/null +++ b/sys/arm/include/atomic.h @@ -0,0 +1,104 @@ +/* $NetBSD: atomic.h,v 1.1 2002/10/19 12:22:34 bsh Exp $ */ + +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (C) 2003-2004 Olivier Houchard + * Copyright (C) 1994-1997 Mark Brinicombe + * Copyright (C) 1994 Brini + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Brini. + * 4. The name of Brini may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_ATOMIC_H_ +#define _MACHINE_ATOMIC_H_ + +#include <sys/atomic_common.h> + +#include <machine/armreg.h> + +#ifndef _KERNEL +#include <machine/sysarch.h> +#endif + +#include <machine/atomic-v6.h> + +static __inline u_long +atomic_swap_long(volatile u_long *p, u_long v) +{ + + return (atomic_swap_32((volatile uint32_t *)p, v)); +} + +#define atomic_clear_ptr atomic_clear_32 +#define atomic_clear_acq_ptr atomic_clear_acq_32 +#define atomic_clear_rel_ptr atomic_clear_rel_32 +#define atomic_set_ptr atomic_set_32 +#define atomic_set_acq_ptr atomic_set_acq_32 +#define atomic_set_rel_ptr atomic_set_rel_32 +#define atomic_fcmpset_ptr atomic_fcmpset_32 +#define atomic_fcmpset_rel_ptr atomic_fcmpset_rel_32 +#define atomic_fcmpset_acq_ptr atomic_fcmpset_acq_32 +#define atomic_cmpset_ptr atomic_cmpset_32 +#define atomic_cmpset_acq_ptr atomic_cmpset_acq_32 +#define atomic_cmpset_rel_ptr atomic_cmpset_rel_32 +#define atomic_load_acq_ptr atomic_load_acq_32 +#define atomic_store_rel_ptr atomic_store_rel_32 +#define atomic_swap_ptr atomic_swap_32 +#define atomic_readandclear_ptr atomic_readandclear_32 + +#define atomic_add_int atomic_add_32 +#define atomic_add_acq_int atomic_add_acq_32 +#define atomic_add_rel_int atomic_add_rel_32 +#define atomic_subtract_int atomic_subtract_32 +#define atomic_subtract_acq_int atomic_subtract_acq_32 +#define atomic_subtract_rel_int atomic_subtract_rel_32 +#define atomic_clear_int atomic_clear_32 +#define atomic_clear_acq_int atomic_clear_acq_32 +#define atomic_clear_rel_int atomic_clear_rel_32 +#define atomic_set_int atomic_set_32 +#define atomic_set_acq_int atomic_set_acq_32 +#define atomic_set_rel_int atomic_set_rel_32 +#define atomic_fcmpset_int atomic_fcmpset_32 +#define atomic_fcmpset_acq_int atomic_fcmpset_acq_32 +#define atomic_fcmpset_rel_int atomic_fcmpset_rel_32 +#define atomic_cmpset_int atomic_cmpset_32 +#define atomic_cmpset_acq_int atomic_cmpset_acq_32 +#define atomic_cmpset_rel_int atomic_cmpset_rel_32 +#define atomic_fetchadd_int atomic_fetchadd_32 +#define atomic_readandclear_int atomic_readandclear_32 +#define atomic_load_acq_int atomic_load_acq_32 +#define atomic_store_rel_int atomic_store_rel_32 +#define atomic_swap_int atomic_swap_32 + +#include <sys/_atomic_subword.h> + +#endif /* _MACHINE_ATOMIC_H_ */ diff --git a/sys/arm/include/blockio.h b/sys/arm/include/blockio.h new file mode 100644 index 000000000000..963ddfc082fe --- /dev/null +++ b/sys/arm/include/blockio.h @@ -0,0 +1,58 @@ +/* $NetBSD: blockio.h,v 1.2 2001/06/02 10:44:56 bjh21 Exp $ */ + +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2001 Ben Harris + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + * + */ +/* + * blockio.h - low level functions for bulk PIO data transfer + */ + +#ifndef _MACHINE_BLOCKIO_H_ +#define _MACHINE_BLOCKIO_H_ + +/* + * All these take three arguments: + * I/O address + * Memory address + * Number of bytes to copy + */ + +void read_multi_1(u_int, void *, u_int); +void write_multi_1(u_int, const void *, u_int); +#define read_multi_2 insw16 +#define write_multi_2 outsw16 + +void insw(u_int, void *, u_int); +void outsw(u_int, void *, u_int); +void insw16(u_int, void *, u_int); +void outsw16(u_int, void *, u_int); + +#endif /* !_MACHINE_BLOCKIO_H_ */ diff --git a/sys/arm/include/bus.h b/sys/arm/include/bus.h new file mode 100644 index 000000000000..e1c7098a69f0 --- /dev/null +++ b/sys/arm/include/bus.h @@ -0,0 +1,784 @@ +/* $NetBSD: bus.h,v 1.11 2003/07/28 17:35:54 thorpej Exp $ */ + +/*- + * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, + * NASA Ames Research Center. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (c) 1996 Charles M. Hannum. All rights reserved. + * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Christopher G. Demetriou + * for the NetBSD Project. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_BUS_H_ +#define _MACHINE_BUS_H_ + +#include <machine/_bus.h> + +/* + * int bus_space_map (bus_space_tag_t t, bus_addr_t addr, + * bus_size_t size, int flags, bus_space_handle_t *bshp); + * + * Map a region of bus space. + */ + +#define BUS_SPACE_MAP_CACHEABLE 0x01 +#define BUS_SPACE_MAP_LINEAR 0x02 +#define BUS_SPACE_MAP_PREFETCHABLE 0x04 + +/* + * Bus space for ARM. + * + * The functions used most often are grouped together at the beginning to ensure + * that all the data fits into a single cache line. The inline implementations + * of single read/write access these values a lot. + */ +struct bus_space { + /* Read/write single and barrier: the most commonly used functions. */ + uint8_t (*bs_r_1)(bus_space_tag_t, bus_space_handle_t, bus_size_t); + uint32_t (*bs_r_4)(bus_space_tag_t, bus_space_handle_t, bus_size_t); + void (*bs_w_1)(bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint8_t); + void (*bs_w_4)(bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint32_t); + void (*bs_barrier)(bus_space_tag_t, bus_space_handle_t, + bus_size_t, bus_size_t, int); + + /* Backlink to parent (if copied), and implementation private data. */ + struct bus_space *bs_parent; + void *bs_privdata; + + /* mapping/unmapping */ + int (*bs_map) (bus_space_tag_t, bus_addr_t, bus_size_t, + int, bus_space_handle_t *); + void (*bs_unmap) (bus_space_tag_t, bus_space_handle_t, bus_size_t); + int (*bs_subregion) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, bus_size_t, bus_space_handle_t *); + + /* allocation/deallocation */ + int (*bs_alloc) (bus_space_tag_t, bus_addr_t, bus_addr_t, + bus_size_t, bus_size_t, bus_size_t, int, + bus_addr_t *, bus_space_handle_t *); + void (*bs_free) (bus_space_tag_t, bus_space_handle_t, + bus_size_t); + + /* Read single, the less commonly used functions. */ + uint16_t (*bs_r_2) (bus_space_tag_t, bus_space_handle_t, bus_size_t); + uint64_t (*bs_r_8) (bus_space_tag_t, bus_space_handle_t, bus_size_t); + + /* read multiple */ + void (*bs_rm_1) (bus_space_tag_t, bus_space_handle_t, bus_size_t, + uint8_t *, bus_size_t); + void (*bs_rm_2) (bus_space_tag_t, bus_space_handle_t, bus_size_t, + uint16_t *, bus_size_t); + void (*bs_rm_4) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint32_t *, bus_size_t); + void (*bs_rm_8) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint64_t *, bus_size_t); + + /* read region */ + void (*bs_rr_1) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint8_t *, bus_size_t); + void (*bs_rr_2) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint16_t *, bus_size_t); + void (*bs_rr_4) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint32_t *, bus_size_t); + void (*bs_rr_8) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint64_t *, bus_size_t); + + /* Write single, the less commonly used functions. */ + void (*bs_w_2) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint16_t); + void (*bs_w_8) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint64_t); + + /* write multiple */ + void (*bs_wm_1) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint8_t *, bus_size_t); + void (*bs_wm_2) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint16_t *, bus_size_t); + void (*bs_wm_4) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint32_t *, bus_size_t); + void (*bs_wm_8) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint64_t *, bus_size_t); + + /* write region */ + void (*bs_wr_1) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint8_t *, bus_size_t); + void (*bs_wr_2) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint16_t *, bus_size_t); + void (*bs_wr_4) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint32_t *, bus_size_t); + void (*bs_wr_8) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint64_t *, bus_size_t); + + /* set multiple */ + void (*bs_sm_1) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint8_t, bus_size_t); + void (*bs_sm_2) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint16_t, bus_size_t); + void (*bs_sm_4) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint32_t, bus_size_t); + void (*bs_sm_8) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint64_t, bus_size_t); + + /* set region */ + void (*bs_sr_1) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint8_t, bus_size_t); + void (*bs_sr_2) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint16_t, bus_size_t); + void (*bs_sr_4) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint32_t, bus_size_t); + void (*bs_sr_8) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint64_t, bus_size_t); + + /* copy */ + void (*bs_c_1) (bus_space_tag_t, bus_space_handle_t, bus_size_t, + bus_space_handle_t, bus_size_t, bus_size_t); + void (*bs_c_2) (bus_space_tag_t, bus_space_handle_t, bus_size_t, + bus_space_handle_t, bus_size_t, bus_size_t); + void (*bs_c_4) (bus_space_tag_t, bus_space_handle_t, bus_size_t, + bus_space_handle_t, bus_size_t, bus_size_t); + void (*bs_c_8) (bus_space_tag_t, bus_space_handle_t, bus_size_t, + bus_space_handle_t, bus_size_t, bus_size_t); + + /* read stream (single) */ + uint8_t (*bs_r_1_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t); + uint16_t (*bs_r_2_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t); + uint32_t (*bs_r_4_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t); + uint64_t (*bs_r_8_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t); + + /* read multiple stream */ + void (*bs_rm_1_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t, + uint8_t *, bus_size_t); + void (*bs_rm_2_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t, + uint16_t *, bus_size_t); + void (*bs_rm_4_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint32_t *, bus_size_t); + void (*bs_rm_8_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint64_t *, bus_size_t); + + /* read region stream */ + void (*bs_rr_1_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint8_t *, bus_size_t); + void (*bs_rr_2_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint16_t *, bus_size_t); + void (*bs_rr_4_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint32_t *, bus_size_t); + void (*bs_rr_8_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint64_t *, bus_size_t); + + /* write stream (single) */ + void (*bs_w_1_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint8_t); + void (*bs_w_2_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint16_t); + void (*bs_w_4_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint32_t); + void (*bs_w_8_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint64_t); + + /* write multiple stream */ + void (*bs_wm_1_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint8_t *, bus_size_t); + void (*bs_wm_2_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint16_t *, bus_size_t); + void (*bs_wm_4_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint32_t *, bus_size_t); + void (*bs_wm_8_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint64_t *, bus_size_t); + + /* write region stream */ + void (*bs_wr_1_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint8_t *, bus_size_t); + void (*bs_wr_2_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint16_t *, bus_size_t); + void (*bs_wr_4_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint32_t *, bus_size_t); + void (*bs_wr_8_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint64_t *, bus_size_t); +}; + +/* + * Utility macros; INTERNAL USE ONLY. + */ +#define __bs_c(a,b) __CONCAT(a,b) +#define __bs_opname(op,size) __bs_c(__bs_c(__bs_c(bs_,op),_),size) + +#define __bs_nonsingle(type, sz, t, h, o, a, c) \ + (*(t)->__bs_opname(type,sz))((t), h, o, a, c) +#define __bs_set(type, sz, t, h, o, v, c) \ + (*(t)->__bs_opname(type,sz))((t), h, o, v, c) +#define __bs_copy(sz, t, h1, o1, h2, o2, cnt) \ + (*(t)->__bs_opname(c,sz))((t), h1, o1, h2, o2, cnt) + +#define __bs_opname_s(op,size) __bs_c(__bs_c(__bs_c(__bs_c(bs_,op),_),size),_s) +#define __bs_rs_s(sz, t, h, o) \ + (*(t)->__bs_opname_s(r,sz))((t), h, o) +#define __bs_ws_s(sz, t, h, o, v) \ + (*(t)->__bs_opname_s(w,sz))((t), h, o, v) +#define __bs_nonsingle_s(type, sz, t, h, o, a, c) \ + (*(t)->__bs_opname_s(type,sz))((t), h, o, a, c) + +#define __generate_inline_bs_rs(IFN, MBR, TYP) \ + static inline TYP \ + IFN(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o) \ + { \ + \ + if (__predict_true(t->MBR == NULL)) \ + return (*(volatile TYP *)(h + o)); \ + else \ + return (t->MBR(t, h, o)); \ + } + +#define __generate_inline_bs_ws(IFN, MBR, TYP) \ + static inline void \ + IFN(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, TYP v)\ + { \ + \ + if (__predict_true(t->MBR == NULL)) \ + *(volatile TYP *)(h + o) = v; \ + else \ + t->MBR(t, h, o, v); \ + } + +/* + * Mapping and unmapping operations. + */ +#define bus_space_map(t, a, s, c, hp) \ + (*(t)->bs_map)((t), (a), (s), (c), (hp)) +#define bus_space_unmap(t, h, s) \ + (*(t)->bs_unmap)((t), (h), (s)) +#define bus_space_subregion(t, h, o, s, hp) \ + (*(t)->bs_subregion)((t), (h), (o), (s), (hp)) + +/* + * Allocation and deallocation operations. + */ +#define bus_space_alloc(t, rs, re, s, a, b, c, ap, hp) \ + (*(t)->bs_alloc)((t), (rs), (re), (s), (a), (b), \ + (c), (ap), (hp)) +#define bus_space_free(t, h, s) \ + (*(t)->bs_free)((t), (h), (s)) + +/* + * Bus barrier operations. + */ +#define bus_space_barrier(t, h, o, l, f) \ + (*(t)->bs_barrier)((t), (h), (o), (l), (f)) + +#define BUS_SPACE_BARRIER_READ 0x01 +#define BUS_SPACE_BARRIER_WRITE 0x02 + +/* + * Bus read (single) operations. + */ +__generate_inline_bs_rs(bus_space_read_1, bs_r_1, uint8_t); +__generate_inline_bs_rs(bus_space_read_2, bs_r_2, uint16_t); +__generate_inline_bs_rs(bus_space_read_4, bs_r_4, uint32_t); +__generate_inline_bs_rs(bus_space_read_8, bs_r_8, uint64_t); + +__generate_inline_bs_rs(bus_space_read_stream_1, bs_r_1_s, uint8_t); +__generate_inline_bs_rs(bus_space_read_stream_2, bs_r_2_s, uint16_t); +__generate_inline_bs_rs(bus_space_read_stream_4, bs_r_4_s, uint32_t); +__generate_inline_bs_rs(bus_space_read_stream_8, bs_r_8_s, uint64_t); + +/* + * Bus read multiple operations. + */ +#define bus_space_read_multi_1(t, h, o, a, c) \ + __bs_nonsingle(rm,1,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_2(t, h, o, a, c) \ + __bs_nonsingle(rm,2,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_4(t, h, o, a, c) \ + __bs_nonsingle(rm,4,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_8(t, h, o, a, c) \ + __bs_nonsingle(rm,8,(t),(h),(o),(a),(c)) + +#define bus_space_read_multi_stream_1(t, h, o, a, c) \ + __bs_nonsingle_s(rm,1,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_stream_2(t, h, o, a, c) \ + __bs_nonsingle_s(rm,2,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_stream_4(t, h, o, a, c) \ + __bs_nonsingle_s(rm,4,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_stream_8(t, h, o, a, c) \ + __bs_nonsingle_s(rm,8,(t),(h),(o),(a),(c)) + +/* + * Bus read region operations. + */ +#define bus_space_read_region_1(t, h, o, a, c) \ + __bs_nonsingle(rr,1,(t),(h),(o),(a),(c)) +#define bus_space_read_region_2(t, h, o, a, c) \ + __bs_nonsingle(rr,2,(t),(h),(o),(a),(c)) +#define bus_space_read_region_4(t, h, o, a, c) \ + __bs_nonsingle(rr,4,(t),(h),(o),(a),(c)) +#define bus_space_read_region_8(t, h, o, a, c) \ + __bs_nonsingle(rr,8,(t),(h),(o),(a),(c)) + +#define bus_space_read_region_stream_1(t, h, o, a, c) \ + __bs_nonsingle_s(rr,1,(t),(h),(o),(a),(c)) +#define bus_space_read_region_stream_2(t, h, o, a, c) \ + __bs_nonsingle_s(rr,2,(t),(h),(o),(a),(c)) +#define bus_space_read_region_stream_4(t, h, o, a, c) \ + __bs_nonsingle_s(rr,4,(t),(h),(o),(a),(c)) +#define bus_space_read_region_stream_8(t, h, o, a, c) \ + __bs_nonsingle_s(rr,8,(t),(h),(o),(a),(c)) + +/* + * Bus write (single) operations. + */ +__generate_inline_bs_ws(bus_space_write_1, bs_w_1, uint8_t); +__generate_inline_bs_ws(bus_space_write_2, bs_w_2, uint16_t); +__generate_inline_bs_ws(bus_space_write_4, bs_w_4, uint32_t); +__generate_inline_bs_ws(bus_space_write_8, bs_w_8, uint64_t); + +__generate_inline_bs_ws(bus_space_write_stream_1, bs_w_1_s, uint8_t); +__generate_inline_bs_ws(bus_space_write_stream_2, bs_w_2_s, uint16_t); +__generate_inline_bs_ws(bus_space_write_stream_4, bs_w_4_s, uint32_t); +__generate_inline_bs_ws(bus_space_write_stream_8, bs_w_8_s, uint64_t); + +/* + * Bus write multiple operations. + */ +#define bus_space_write_multi_1(t, h, o, a, c) \ + __bs_nonsingle(wm,1,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_2(t, h, o, a, c) \ + __bs_nonsingle(wm,2,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_4(t, h, o, a, c) \ + __bs_nonsingle(wm,4,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_8(t, h, o, a, c) \ + __bs_nonsingle(wm,8,(t),(h),(o),(a),(c)) + +#define bus_space_write_multi_stream_1(t, h, o, a, c) \ + __bs_nonsingle_s(wm,1,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_stream_2(t, h, o, a, c) \ + __bs_nonsingle_s(wm,2,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_stream_4(t, h, o, a, c) \ + __bs_nonsingle_s(wm,4,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_stream_8(t, h, o, a, c) \ + __bs_nonsingle_s(wm,8,(t),(h),(o),(a),(c)) + +/* + * Bus write region operations. + */ +#define bus_space_write_region_1(t, h, o, a, c) \ + __bs_nonsingle(wr,1,(t),(h),(o),(a),(c)) +#define bus_space_write_region_2(t, h, o, a, c) \ + __bs_nonsingle(wr,2,(t),(h),(o),(a),(c)) +#define bus_space_write_region_4(t, h, o, a, c) \ + __bs_nonsingle(wr,4,(t),(h),(o),(a),(c)) +#define bus_space_write_region_8(t, h, o, a, c) \ + __bs_nonsingle(wr,8,(t),(h),(o),(a),(c)) + +#define bus_space_write_region_stream_1(t, h, o, a, c) \ + __bs_nonsingle_s(wr,1,(t),(h),(o),(a),(c)) +#define bus_space_write_region_stream_2(t, h, o, a, c) \ + __bs_nonsingle_s(wr,2,(t),(h),(o),(a),(c)) +#define bus_space_write_region_stream_4(t, h, o, a, c) \ + __bs_nonsingle_s(wr,4,(t),(h),(o),(a),(c)) +#define bus_space_write_region_stream_8(t, h, o, a, c) \ + __bs_nonsingle_s(wr,8,(t),(h),(o),(a),(c)) + +/* + * Set multiple operations. + */ +#define bus_space_set_multi_1(t, h, o, v, c) \ + __bs_set(sm,1,(t),(h),(o),(v),(c)) +#define bus_space_set_multi_2(t, h, o, v, c) \ + __bs_set(sm,2,(t),(h),(o),(v),(c)) +#define bus_space_set_multi_4(t, h, o, v, c) \ + __bs_set(sm,4,(t),(h),(o),(v),(c)) +#define bus_space_set_multi_8(t, h, o, v, c) \ + __bs_set(sm,8,(t),(h),(o),(v),(c)) + +/* + * Set region operations. + */ +#define bus_space_set_region_1(t, h, o, v, c) \ + __bs_set(sr,1,(t),(h),(o),(v),(c)) +#define bus_space_set_region_2(t, h, o, v, c) \ + __bs_set(sr,2,(t),(h),(o),(v),(c)) +#define bus_space_set_region_4(t, h, o, v, c) \ + __bs_set(sr,4,(t),(h),(o),(v),(c)) +#define bus_space_set_region_8(t, h, o, v, c) \ + __bs_set(sr,8,(t),(h),(o),(v),(c)) + +/* + * Copy operations. + */ +#define bus_space_copy_region_1(t, h1, o1, h2, o2, c) \ + __bs_copy(1, t, h1, o1, h2, o2, c) +#define bus_space_copy_region_2(t, h1, o1, h2, o2, c) \ + __bs_copy(2, t, h1, o1, h2, o2, c) +#define bus_space_copy_region_4(t, h1, o1, h2, o2, c) \ + __bs_copy(4, t, h1, o1, h2, o2, c) +#define bus_space_copy_region_8(t, h1, o1, h2, o2, c) \ + __bs_copy(8, t, h1, o1, h2, o2, c) + +/* + * Macros to provide prototypes for all the functions used in the + * bus_space structure + */ + +#define bs_map_proto(f) \ +int __bs_c(f,_bs_map) (bus_space_tag_t t, bus_addr_t addr, \ + bus_size_t size, int cacheable, bus_space_handle_t *bshp); + +#define bs_unmap_proto(f) \ +void __bs_c(f,_bs_unmap) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t size); + +#define bs_subregion_proto(f) \ +int __bs_c(f,_bs_subregion) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, bus_size_t size, \ + bus_space_handle_t *nbshp); + +#define bs_alloc_proto(f) \ +int __bs_c(f,_bs_alloc) (bus_space_tag_t t, bus_addr_t rstart, \ + bus_addr_t rend, bus_size_t size, bus_size_t align, \ + bus_size_t boundary, int cacheable, bus_addr_t *addrp, \ + bus_space_handle_t *bshp); + +#define bs_free_proto(f) \ +void __bs_c(f,_bs_free) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t size); + +#define bs_mmap_proto(f) \ +int __bs_c(f,_bs_mmap) (struct cdev *, vm_offset_t, vm_paddr_t *, int); + +#define bs_barrier_proto(f) \ +void __bs_c(f,_bs_barrier) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, bus_size_t len, int flags); + +#define bs_r_1_proto(f) \ +uint8_t __bs_c(f,_bs_r_1) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset); + +#define bs_r_2_proto(f) \ +uint16_t __bs_c(f,_bs_r_2) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset); + +#define bs_r_4_proto(f) \ +uint32_t __bs_c(f,_bs_r_4) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset); + +#define bs_r_8_proto(f) \ +uint64_t __bs_c(f,_bs_r_8) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset); + +#define bs_r_1_s_proto(f) \ +uint8_t __bs_c(f,_bs_r_1_s) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset); + +#define bs_r_2_s_proto(f) \ +uint16_t __bs_c(f,_bs_r_2_s) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset); + +#define bs_r_4_s_proto(f) \ +uint32_t __bs_c(f,_bs_r_4_s) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset); + +#define bs_w_1_proto(f) \ +void __bs_c(f,_bs_w_1) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint8_t value); + +#define bs_w_2_proto(f) \ +void __bs_c(f,_bs_w_2) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint16_t value); + +#define bs_w_4_proto(f) \ +void __bs_c(f,_bs_w_4) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint32_t value); + +#define bs_w_8_proto(f) \ +void __bs_c(f,_bs_w_8) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint64_t value); + +#define bs_w_1_s_proto(f) \ +void __bs_c(f,_bs_w_1_s) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint8_t value); + +#define bs_w_2_s_proto(f) \ +void __bs_c(f,_bs_w_2_s) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint16_t value); + +#define bs_w_4_s_proto(f) \ +void __bs_c(f,_bs_w_4_s) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint32_t value); + +#define bs_rm_1_proto(f) \ +void __bs_c(f,_bs_rm_1) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint8_t *addr, bus_size_t count); + +#define bs_rm_2_proto(f) \ +void __bs_c(f,_bs_rm_2) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint16_t *addr, bus_size_t count); + +#define bs_rm_4_proto(f) \ +void __bs_c(f,_bs_rm_4) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint32_t *addr, bus_size_t count); + +#define bs_rm_8_proto(f) \ +void __bs_c(f,_bs_rm_8) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint64_t *addr, bus_size_t count); + +#define bs_wm_1_proto(f) \ +void __bs_c(f,_bs_wm_1) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, const uint8_t *addr, bus_size_t count); + +#define bs_wm_2_proto(f) \ +void __bs_c(f,_bs_wm_2) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, const uint16_t *addr, bus_size_t count); + +#define bs_wm_4_proto(f) \ +void __bs_c(f,_bs_wm_4) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, const uint32_t *addr, bus_size_t count); + +#define bs_wm_8_proto(f) \ +void __bs_c(f,_bs_wm_8) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, const uint64_t *addr, bus_size_t count); + +#define bs_rr_1_proto(f) \ +void __bs_c(f, _bs_rr_1) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint8_t *addr, bus_size_t count); + +#define bs_rr_2_proto(f) \ +void __bs_c(f, _bs_rr_2) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint16_t *addr, bus_size_t count); + +#define bs_rr_4_proto(f) \ +void __bs_c(f, _bs_rr_4) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint32_t *addr, bus_size_t count); + +#define bs_rr_8_proto(f) \ +void __bs_c(f, _bs_rr_8) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint64_t *addr, bus_size_t count); + +#define bs_wr_1_proto(f) \ +void __bs_c(f, _bs_wr_1) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, const uint8_t *addr, bus_size_t count); + +#define bs_wr_2_proto(f) \ +void __bs_c(f, _bs_wr_2) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, const uint16_t *addr, bus_size_t count); + +#define bs_wr_4_proto(f) \ +void __bs_c(f, _bs_wr_4) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, const uint32_t *addr, bus_size_t count); + +#define bs_wr_8_proto(f) \ +void __bs_c(f, _bs_wr_8) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, const uint64_t *addr, bus_size_t count); + +#define bs_sm_1_proto(f) \ +void __bs_c(f,_bs_sm_1) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint8_t value, bus_size_t count); + +#define bs_sm_2_proto(f) \ +void __bs_c(f,_bs_sm_2) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint16_t value, bus_size_t count); + +#define bs_sm_4_proto(f) \ +void __bs_c(f,_bs_sm_4) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint32_t value, bus_size_t count); + +#define bs_sm_8_proto(f) \ +void __bs_c(f,_bs_sm_8) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint64_t value, bus_size_t count); + +#define bs_sr_1_proto(f) \ +void __bs_c(f,_bs_sr_1) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint8_t value, bus_size_t count); + +#define bs_sr_2_proto(f) \ +void __bs_c(f,_bs_sr_2) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint16_t value, bus_size_t count); + +#define bs_sr_4_proto(f) \ +void __bs_c(f,_bs_sr_4) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint32_t value, bus_size_t count); + +#define bs_sr_8_proto(f) \ +void __bs_c(f,_bs_sr_8) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint64_t value, bus_size_t count); + +#define bs_c_1_proto(f) \ +void __bs_c(f,_bs_c_1) (bus_space_tag_t t, bus_space_handle_t bsh1, \ + bus_size_t offset1, bus_space_handle_t bsh2, \ + bus_size_t offset2, bus_size_t count); + +#define bs_c_2_proto(f) \ +void __bs_c(f,_bs_c_2) (bus_space_tag_t t, bus_space_handle_t bsh1, \ + bus_size_t offset1, bus_space_handle_t bsh2, \ + bus_size_t offset2, bus_size_t count); + +#define bs_c_4_proto(f) \ +void __bs_c(f,_bs_c_4) (bus_space_tag_t t, bus_space_handle_t bsh1, \ + bus_size_t offset1, bus_space_handle_t bsh2, \ + bus_size_t offset2, bus_size_t count); + +#define bs_c_8_proto(f) \ +void __bs_c(f,_bs_c_8) (bus_space_tag_t t, bus_space_handle_t bsh1, \ + bus_size_t offset1, bus_space_handle_t bsh2, \ + bus_size_t offset2, bus_size_t count); + +#define bs_protos(f) \ +bs_map_proto(f); \ +bs_unmap_proto(f); \ +bs_subregion_proto(f); \ +bs_alloc_proto(f); \ +bs_free_proto(f); \ +bs_mmap_proto(f); \ +bs_barrier_proto(f); \ +bs_r_1_proto(f); \ +bs_r_2_proto(f); \ +bs_r_4_proto(f); \ +bs_r_8_proto(f); \ +bs_r_1_s_proto(f); \ +bs_r_2_s_proto(f); \ +bs_r_4_s_proto(f); \ +bs_w_1_proto(f); \ +bs_w_2_proto(f); \ +bs_w_4_proto(f); \ +bs_w_8_proto(f); \ +bs_w_1_s_proto(f); \ +bs_w_2_s_proto(f); \ +bs_w_4_s_proto(f); \ +bs_rm_1_proto(f); \ +bs_rm_2_proto(f); \ +bs_rm_4_proto(f); \ +bs_rm_8_proto(f); \ +bs_wm_1_proto(f); \ +bs_wm_2_proto(f); \ +bs_wm_4_proto(f); \ +bs_wm_8_proto(f); \ +bs_rr_1_proto(f); \ +bs_rr_2_proto(f); \ +bs_rr_4_proto(f); \ +bs_rr_8_proto(f); \ +bs_wr_1_proto(f); \ +bs_wr_2_proto(f); \ +bs_wr_4_proto(f); \ +bs_wr_8_proto(f); \ +bs_sm_1_proto(f); \ +bs_sm_2_proto(f); \ +bs_sm_4_proto(f); \ +bs_sm_8_proto(f); \ +bs_sr_1_proto(f); \ +bs_sr_2_proto(f); \ +bs_sr_4_proto(f); \ +bs_sr_8_proto(f); \ +bs_c_1_proto(f); \ +bs_c_2_proto(f); \ +bs_c_4_proto(f); \ +bs_c_8_proto(f); + +void generic_bs_unimplemented(void); +#define BS_UNIMPLEMENTED (void *)generic_bs_unimplemented + +#define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) + +#define BUS_SPACE_MAXADDR_24BIT 0xFFFFFF +#define BUS_SPACE_MAXADDR_32BIT 0xFFFFFFFF +#define BUS_SPACE_MAXADDR 0xFFFFFFFF +#define BUS_SPACE_MAXSIZE_24BIT 0xFFFFFF +#define BUS_SPACE_MAXSIZE_32BIT 0xFFFFFFFF +#define BUS_SPACE_MAXSIZE 0xFFFFFFFF + +#define BUS_SPACE_UNRESTRICTED (~0) + +#define BUS_PEEK_FUNC(width, type) \ + static inline int \ + bus_space_peek_##width(bus_space_tag_t tag, \ + bus_space_handle_t hnd, bus_size_t offset, type *value) \ + { \ + type tmp; \ + tmp = bus_space_read_##width(tag, hnd, offset); \ + *value = (type)tmp; \ + return (0); \ + } +BUS_PEEK_FUNC(1, uint8_t) +BUS_PEEK_FUNC(2, uint16_t) +BUS_PEEK_FUNC(4, uint32_t) +BUS_PEEK_FUNC(8, uint64_t) + +#define BUS_POKE_FUNC(width, type) \ + static inline int \ + bus_space_poke_##width(bus_space_tag_t tag, \ + bus_space_handle_t hnd, bus_size_t offset, type value) \ + { \ + bus_space_write_##width(tag, hnd, offset, value); \ + return (0); \ + } +BUS_POKE_FUNC(1, uint8_t) +BUS_POKE_FUNC(2, uint16_t) +BUS_POKE_FUNC(4, uint32_t) +BUS_POKE_FUNC(8, uint64_t) + +#include <machine/bus_dma.h> + +/* + * Get the physical address of a bus space memory-mapped resource. + * Doing this as a macro is a temporary solution until a more robust fix is + * designed. It also serves to mark the locations needing that fix. + */ +#define BUS_SPACE_PHYSADDR(res, offs) \ + ((u_int)(rman_get_start(res)+(offs))) + +#endif /* _MACHINE_BUS_H_ */ diff --git a/sys/arm/include/bus_dma.h b/sys/arm/include/bus_dma.h new file mode 100644 index 000000000000..d716f4f01a17 --- /dev/null +++ b/sys/arm/include/bus_dma.h @@ -0,0 +1,78 @@ +/* $NetBSD: bus.h,v 1.11 2003/07/28 17:35:54 thorpej Exp $ */ + +/*- + * SPDX-License-Identifier: BSD-2-Clause-NetBSD + * + * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, + * NASA Ames Research Center. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/*- + * Copyright (c) 1996 Charles M. Hannum. All rights reserved. + * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Christopher G. Demetriou + * for the NetBSD Project. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _ARM_BUS_DMA_H +#define _ARM_BUS_DMA_H + +#include <sys/bus_dma.h> +#include <sys/bus_dma_internal.h> + +/* Bus Space DMA macros */ + +#define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0) + +#endif /* _ARM_BUS_DMA_H */ diff --git a/sys/arm/include/clock.h b/sys/arm/include/clock.h new file mode 100644 index 000000000000..c9ac2039f836 --- /dev/null +++ b/sys/arm/include/clock.h @@ -0,0 +1,34 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2004 Olivier Houchard + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_CLOCK_H_ +#define _MACHINE_CLOCK_H_ + +#endif /* !_MACHINE_CLOCK_H_ */ diff --git a/sys/arm/include/counter.h b/sys/arm/include/counter.h new file mode 100644 index 000000000000..e3fb03abd352 --- /dev/null +++ b/sys/arm/include/counter.h @@ -0,0 +1,91 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2012 Konstantin Belousov <kib@FreeBSD.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef __MACHINE_COUNTER_H__ +#define __MACHINE_COUNTER_H__ + +#include <sys/pcpu.h> +#include <machine/atomic.h> + +#define EARLY_COUNTER &__pcpu[0].pc_early_dummy_counter + +#define counter_enter() do {} while (0) +#define counter_exit() do {} while (0) + +#ifdef IN_SUBR_COUNTER_C + +static inline uint64_t +counter_u64_read_one(uint64_t *p, int cpu) +{ + + return (atomic_load_64((uint64_t *)((char *)p + UMA_PCPU_ALLOC_SIZE * + cpu))); +} + +static inline uint64_t +counter_u64_fetch_inline(uint64_t *p) +{ + uint64_t r; + int i; + + r = 0; + CPU_FOREACH(i) + r += counter_u64_read_one((uint64_t *)p, i); + + return (r); +} + +static void +counter_u64_zero_one_cpu(void *arg) +{ + + atomic_store_64((uint64_t *)((char *)arg + UMA_PCPU_ALLOC_SIZE * + PCPU_GET(cpuid)), 0); +} + +static inline void +counter_u64_zero_inline(counter_u64_t c) +{ + + smp_rendezvous(smp_no_rendezvous_barrier, counter_u64_zero_one_cpu, + smp_no_rendezvous_barrier, c); +} +#endif + +#define counter_u64_add_protected(c, inc) counter_u64_add(c, inc) + +static inline void +counter_u64_add(counter_u64_t c, int64_t inc) +{ + + atomic_add_64((uint64_t *)zpcpu_get(c), inc); +} + +#endif /* ! __MACHINE_COUNTER_H__ */ diff --git a/sys/arm/include/cpu-v6.h b/sys/arm/include/cpu-v6.h new file mode 100644 index 000000000000..4b301cfd1c4e --- /dev/null +++ b/sys/arm/include/cpu-v6.h @@ -0,0 +1,685 @@ +/*- + * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com> + * Copyright 2014 Michal Meloun <meloun@miracle.cz> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ +#ifndef MACHINE_CPU_V6_H +#define MACHINE_CPU_V6_H + +/* There are no user serviceable parts here, they may change without notice */ +#ifndef _KERNEL +#error Only include this file in the kernel +#endif + +#include <machine/atomic.h> +#include <machine/cpufunc.h> +#include <machine/cpuinfo.h> +#include <machine/sysreg.h> + +/* + * Some kernel modules (dtrace all for example) are compiled + * unconditionally with -DSMP. Although it looks like a bug, + * handle this case here and in #elif condition in ARM_SMP_UP macro. + */ +#if __ARM_ARCH <= 6 && defined(SMP) && !defined(KLD_MODULE) +#error SMP option is not supported on ARMv6 +#endif + +#if __ARM_ARCH <= 6 && defined(SMP_ON_UP) +#error SMP_ON_UP option is only supported on ARMv7+ CPUs +#endif + +#if !defined(SMP) && defined(SMP_ON_UP) +#error SMP option must be defined for SMP_ON_UP option +#endif + +#define CPU_ASID_KERNEL 0 + +#if defined(SMP_ON_UP) +#define ARM_SMP_UP(smp_code, up_code) \ +do { \ + if (cpuinfo.mp_ext != 0) { \ + smp_code; \ + } else { \ + up_code; \ + } \ +} while (0) +#elif defined(SMP) && __ARM_ARCH > 6 +#define ARM_SMP_UP(smp_code, up_code) \ +do { \ + smp_code; \ +} while (0) +#else +#define ARM_SMP_UP(smp_code, up_code) \ +do { \ + up_code; \ +} while (0) +#endif + +void dcache_wbinv_poc_all(void); /* !!! NOT SMP coherent function !!! */ +vm_offset_t dcache_wb_pou_checked(vm_offset_t, vm_size_t); +vm_offset_t icache_inv_pou_checked(vm_offset_t, vm_size_t); + +#ifdef DEV_PMU +#include <sys/pcpu.h> +#define PMU_OVSR_C 0x80000000 /* Cycle Counter */ +extern uint32_t ccnt_hi[MAXCPU]; +extern int pmu_attched; +#endif /* DEV_PMU */ + +#define sev() __asm __volatile("sev" : : : "memory") +#define wfe() __asm __volatile("wfe" : : : "memory") + +/* + * Macros to generate CP15 (system control processor) read/write functions. + */ +#define _FX(s...) #s + +#define _RF0(fname, aname...) \ +static __inline uint32_t \ +fname(void) \ +{ \ + uint32_t reg; \ + __asm __volatile("mrc\t" _FX(aname): "=r" (reg)); \ + return(reg); \ +} + +#define _R64F0(fname, aname) \ +static __inline uint64_t \ +fname(void) \ +{ \ + uint64_t reg; \ + __asm __volatile("mrrc\t" _FX(aname): "=r" (reg)); \ + return(reg); \ +} + +#define _WF0(fname, aname...) \ +static __inline void \ +fname(void) \ +{ \ + __asm __volatile("mcr\t" _FX(aname)); \ +} + +#define _WF1(fname, aname...) \ +static __inline void \ +fname(uint32_t reg) \ +{ \ + __asm __volatile("mcr\t" _FX(aname):: "r" (reg)); \ +} + +#define _W64F1(fname, aname...) \ +static __inline void \ +fname(uint64_t reg) \ +{ \ + __asm __volatile("mcrr\t" _FX(aname):: "r" (reg)); \ +} + +/* + * Raw CP15 maintenance operations + * !!! not for external use !!! + */ + +/* TLB */ + +_WF0(_CP15_TLBIALL, CP15_TLBIALL) /* Invalidate entire unified TLB */ +#if __ARM_ARCH >= 7 && defined(SMP) +_WF0(_CP15_TLBIALLIS, CP15_TLBIALLIS) /* Invalidate entire unified TLB IS */ +#endif +_WF1(_CP15_TLBIASID, CP15_TLBIASID(%0)) /* Invalidate unified TLB by ASID */ +#if __ARM_ARCH >= 7 && defined(SMP) +_WF1(_CP15_TLBIASIDIS, CP15_TLBIASIDIS(%0)) /* Invalidate unified TLB by ASID IS */ +#endif +_WF1(_CP15_TLBIMVAA, CP15_TLBIMVAA(%0)) /* Invalidate unified TLB by MVA, all ASID */ +#if __ARM_ARCH >= 7 && defined(SMP) +_WF1(_CP15_TLBIMVAAIS, CP15_TLBIMVAAIS(%0)) /* Invalidate unified TLB by MVA, all ASID IS */ +#endif +_WF1(_CP15_TLBIMVA, CP15_TLBIMVA(%0)) /* Invalidate unified TLB by MVA */ + +_WF1(_CP15_TTB_SET, CP15_TTBR0(%0)) + +/* Cache and Branch predictor */ + +_WF0(_CP15_BPIALL, CP15_BPIALL) /* Branch predictor invalidate all */ +#if __ARM_ARCH >= 7 && defined(SMP) +_WF0(_CP15_BPIALLIS, CP15_BPIALLIS) /* Branch predictor invalidate all IS */ +#endif +_WF1(_CP15_BPIMVA, CP15_BPIMVA(%0)) /* Branch predictor invalidate by MVA */ +_WF1(_CP15_DCCIMVAC, CP15_DCCIMVAC(%0)) /* Data cache clean and invalidate by MVA PoC */ +_WF1(_CP15_DCCISW, CP15_DCCISW(%0)) /* Data cache clean and invalidate by set/way */ +_WF1(_CP15_DCCMVAC, CP15_DCCMVAC(%0)) /* Data cache clean by MVA PoC */ +#if __ARM_ARCH >= 7 +_WF1(_CP15_DCCMVAU, CP15_DCCMVAU(%0)) /* Data cache clean by MVA PoU */ +#endif +_WF1(_CP15_DCCSW, CP15_DCCSW(%0)) /* Data cache clean by set/way */ +_WF1(_CP15_DCIMVAC, CP15_DCIMVAC(%0)) /* Data cache invalidate by MVA PoC */ +_WF1(_CP15_DCISW, CP15_DCISW(%0)) /* Data cache invalidate by set/way */ +_WF0(_CP15_ICIALLU, CP15_ICIALLU) /* Instruction cache invalidate all PoU */ +#if __ARM_ARCH >= 7 && defined(SMP) +_WF0(_CP15_ICIALLUIS, CP15_ICIALLUIS) /* Instruction cache invalidate all PoU IS */ +#endif +_WF1(_CP15_ICIMVAU, CP15_ICIMVAU(%0)) /* Instruction cache invalidate */ + +/* + * Publicly accessible functions + */ + +/* CP14 Debug Registers */ +_RF0(cp14_dbgdidr_get, CP14_DBGDIDR(%0)) +_RF0(cp14_dbgprsr_get, CP14_DBGPRSR(%0)) +_RF0(cp14_dbgoslsr_get, CP14_DBGOSLSR(%0)) +_RF0(cp14_dbgosdlr_get, CP14_DBGOSDLR(%0)) +_RF0(cp14_dbgdscrint_get, CP14_DBGDSCRint(%0)) + +_WF1(cp14_dbgdscr_v6_set, CP14_DBGDSCRext_V6(%0)) +_WF1(cp14_dbgdscr_v7_set, CP14_DBGDSCRext_V7(%0)) +_WF1(cp14_dbgvcr_set, CP14_DBGVCR(%0)) +_WF1(cp14_dbgoslar_set, CP14_DBGOSLAR(%0)) + +/* Various control registers */ + +_RF0(cp15_cpacr_get, CP15_CPACR(%0)) +_WF1(cp15_cpacr_set, CP15_CPACR(%0)) +_RF0(cp15_dfsr_get, CP15_DFSR(%0)) +_RF0(cp15_ifsr_get, CP15_IFSR(%0)) +_WF1(cp15_prrr_set, CP15_PRRR(%0)) +_WF1(cp15_nmrr_set, CP15_NMRR(%0)) +_RF0(cp15_ttbr_get, CP15_TTBR0(%0)) +_RF0(cp15_dfar_get, CP15_DFAR(%0)) +#if __ARM_ARCH >= 7 +_RF0(cp15_ifar_get, CP15_IFAR(%0)) +_RF0(cp15_l2ctlr_get, CP15_L2CTLR(%0)) +#endif +_RF0(cp15_actlr_get, CP15_ACTLR(%0)) +_WF1(cp15_actlr_set, CP15_ACTLR(%0)) +_WF1(cp15_ats1cpr_set, CP15_ATS1CPR(%0)) +_WF1(cp15_ats1cpw_set, CP15_ATS1CPW(%0)) +_WF1(cp15_ats1cur_set, CP15_ATS1CUR(%0)) +_WF1(cp15_ats1cuw_set, CP15_ATS1CUW(%0)) +_RF0(cp15_par_get, CP15_PAR(%0)) +_RF0(cp15_sctlr_get, CP15_SCTLR(%0)) + +/*CPU id registers */ +_RF0(cp15_midr_get, CP15_MIDR(%0)) +_RF0(cp15_ctr_get, CP15_CTR(%0)) +_RF0(cp15_tcmtr_get, CP15_TCMTR(%0)) +_RF0(cp15_tlbtr_get, CP15_TLBTR(%0)) +_RF0(cp15_mpidr_get, CP15_MPIDR(%0)) +_RF0(cp15_revidr_get, CP15_REVIDR(%0)) +_RF0(cp15_ccsidr_get, CP15_CCSIDR(%0)) +_RF0(cp15_clidr_get, CP15_CLIDR(%0)) +_RF0(cp15_aidr_get, CP15_AIDR(%0)) +_WF1(cp15_csselr_set, CP15_CSSELR(%0)) +_RF0(cp15_id_pfr0_get, CP15_ID_PFR0(%0)) +_RF0(cp15_id_pfr1_get, CP15_ID_PFR1(%0)) +_RF0(cp15_id_dfr0_get, CP15_ID_DFR0(%0)) +_RF0(cp15_id_afr0_get, CP15_ID_AFR0(%0)) +_RF0(cp15_id_mmfr0_get, CP15_ID_MMFR0(%0)) +_RF0(cp15_id_mmfr1_get, CP15_ID_MMFR1(%0)) +_RF0(cp15_id_mmfr2_get, CP15_ID_MMFR2(%0)) +_RF0(cp15_id_mmfr3_get, CP15_ID_MMFR3(%0)) +_RF0(cp15_id_isar0_get, CP15_ID_ISAR0(%0)) +_RF0(cp15_id_isar1_get, CP15_ID_ISAR1(%0)) +_RF0(cp15_id_isar2_get, CP15_ID_ISAR2(%0)) +_RF0(cp15_id_isar3_get, CP15_ID_ISAR3(%0)) +_RF0(cp15_id_isar4_get, CP15_ID_ISAR4(%0)) +_RF0(cp15_id_isar5_get, CP15_ID_ISAR5(%0)) +_RF0(cp15_cbar_get, CP15_CBAR(%0)) + +/* Performance Monitor registers */ + +#if __ARM_ARCH == 6 && defined(CPU_ARM1176) +_RF0(cp15_pmuserenr_get, CP15_PMUSERENR(%0)) +_WF1(cp15_pmuserenr_set, CP15_PMUSERENR(%0)) +_RF0(cp15_pmcr_get, CP15_PMCR(%0)) +_WF1(cp15_pmcr_set, CP15_PMCR(%0)) +_RF0(cp15_pmccntr_get, CP15_PMCCNTR(%0)) +_WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0)) +#elif __ARM_ARCH > 6 +_RF0(cp15_pmcr_get, CP15_PMCR(%0)) +_WF1(cp15_pmcr_set, CP15_PMCR(%0)) +_RF0(cp15_pmcnten_get, CP15_PMCNTENSET(%0)) +_WF1(cp15_pmcnten_set, CP15_PMCNTENSET(%0)) +_WF1(cp15_pmcnten_clr, CP15_PMCNTENCLR(%0)) +_RF0(cp15_pmovsr_get, CP15_PMOVSR(%0)) +_WF1(cp15_pmovsr_set, CP15_PMOVSR(%0)) +_WF1(cp15_pmswinc_set, CP15_PMSWINC(%0)) +_RF0(cp15_pmselr_get, CP15_PMSELR(%0)) +_WF1(cp15_pmselr_set, CP15_PMSELR(%0)) +_RF0(cp15_pmccntr_get, CP15_PMCCNTR(%0)) +_WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0)) +_RF0(cp15_pmxevtyper_get, CP15_PMXEVTYPER(%0)) +_WF1(cp15_pmxevtyper_set, CP15_PMXEVTYPER(%0)) +_RF0(cp15_pmxevcntr_get, CP15_PMXEVCNTRR(%0)) +_WF1(cp15_pmxevcntr_set, CP15_PMXEVCNTRR(%0)) +_RF0(cp15_pmuserenr_get, CP15_PMUSERENR(%0)) +_WF1(cp15_pmuserenr_set, CP15_PMUSERENR(%0)) +_RF0(cp15_pminten_get, CP15_PMINTENSET(%0)) +_WF1(cp15_pminten_set, CP15_PMINTENSET(%0)) +_WF1(cp15_pminten_clr, CP15_PMINTENCLR(%0)) +#endif + +_RF0(cp15_tpidrurw_get, CP15_TPIDRURW(%0)) +_WF1(cp15_tpidrurw_set, CP15_TPIDRURW(%0)) +_RF0(cp15_tpidruro_get, CP15_TPIDRURO(%0)) +_WF1(cp15_tpidruro_set, CP15_TPIDRURO(%0)) +_RF0(cp15_tpidrpwr_get, CP15_TPIDRPRW(%0)) +_WF1(cp15_tpidrpwr_set, CP15_TPIDRPRW(%0)) + +/* Generic Timer registers - only use when you know the hardware is available */ +_RF0(cp15_cntfrq_get, CP15_CNTFRQ(%0)) +_WF1(cp15_cntfrq_set, CP15_CNTFRQ(%0)) +_RF0(cp15_cntkctl_get, CP15_CNTKCTL(%0)) +_WF1(cp15_cntkctl_set, CP15_CNTKCTL(%0)) +_RF0(cp15_cntp_tval_get, CP15_CNTP_TVAL(%0)) +_WF1(cp15_cntp_tval_set, CP15_CNTP_TVAL(%0)) +_RF0(cp15_cntp_ctl_get, CP15_CNTP_CTL(%0)) +_WF1(cp15_cntp_ctl_set, CP15_CNTP_CTL(%0)) +_RF0(cp15_cntv_tval_get, CP15_CNTV_TVAL(%0)) +_WF1(cp15_cntv_tval_set, CP15_CNTV_TVAL(%0)) +_RF0(cp15_cntv_ctl_get, CP15_CNTV_CTL(%0)) +_WF1(cp15_cntv_ctl_set, CP15_CNTV_CTL(%0)) +_RF0(cp15_cnthctl_get, CP15_CNTHCTL(%0)) +_WF1(cp15_cnthctl_set, CP15_CNTHCTL(%0)) +_RF0(cp15_cnthp_tval_get, CP15_CNTHP_TVAL(%0)) +_WF1(cp15_cnthp_tval_set, CP15_CNTHP_TVAL(%0)) +_RF0(cp15_cnthp_ctl_get, CP15_CNTHP_CTL(%0)) +_WF1(cp15_cnthp_ctl_set, CP15_CNTHP_CTL(%0)) + +_R64F0(cp15_cntpct_get, CP15_CNTPCT(%Q0, %R0)) +_R64F0(cp15_cntvct_get, CP15_CNTVCT(%Q0, %R0)) +_R64F0(cp15_cntp_cval_get, CP15_CNTP_CVAL(%Q0, %R0)) +_W64F1(cp15_cntp_cval_set, CP15_CNTP_CVAL(%Q0, %R0)) +_R64F0(cp15_cntv_cval_get, CP15_CNTV_CVAL(%Q0, %R0)) +_W64F1(cp15_cntv_cval_set, CP15_CNTV_CVAL(%Q0, %R0)) +_R64F0(cp15_cntvoff_get, CP15_CNTVOFF(%Q0, %R0)) +_W64F1(cp15_cntvoff_set, CP15_CNTVOFF(%Q0, %R0)) +_R64F0(cp15_cnthp_cval_get, CP15_CNTHP_CVAL(%Q0, %R0)) +_W64F1(cp15_cnthp_cval_set, CP15_CNTHP_CVAL(%Q0, %R0)) + +#undef _FX +#undef _RF0 +#undef _WF0 +#undef _WF1 + +/* + * TLB maintenance operations. + */ + +/* Local (i.e. not broadcasting ) operations. */ + +/* Flush all TLB entries (even global). */ +static __inline void +tlb_flush_all_local(void) +{ + + dsb(); + _CP15_TLBIALL(); + dsb(); +} + +/* Flush all not global TLB entries. */ +static __inline void +tlb_flush_all_ng_local(void) +{ + + dsb(); + _CP15_TLBIASID(CPU_ASID_KERNEL); + dsb(); +} + +/* Flush single TLB entry (even global). */ +static __inline void +tlb_flush_local(vm_offset_t va) +{ + + KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va)); + + dsb(); + _CP15_TLBIMVA(va | CPU_ASID_KERNEL); + dsb(); +} + +/* Flush range of TLB entries (even global). */ +static __inline void +tlb_flush_range_local(vm_offset_t va, vm_size_t size) +{ + vm_offset_t eva = va + size; + + KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va)); + KASSERT((size & PAGE_MASK) == 0, ("%s: size %#x not aligned", __func__, + size)); + + dsb(); + for (; va < eva; va += PAGE_SIZE) + _CP15_TLBIMVA(va | CPU_ASID_KERNEL); + dsb(); +} + +/* Broadcasting operations. */ +#if __ARM_ARCH >= 7 && defined(SMP) + +static __inline void +tlb_flush_all(void) +{ + + dsb(); + ARM_SMP_UP( + _CP15_TLBIALLIS(), + _CP15_TLBIALL() + ); + dsb(); +} + +static __inline void +tlb_flush_all_ng(void) +{ + + dsb(); + ARM_SMP_UP( + _CP15_TLBIASIDIS(CPU_ASID_KERNEL), + _CP15_TLBIASID(CPU_ASID_KERNEL) + ); + dsb(); +} + +static __inline void +tlb_flush(vm_offset_t va) +{ + + KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va)); + + dsb(); + ARM_SMP_UP( + _CP15_TLBIMVAAIS(va), + _CP15_TLBIMVA(va | CPU_ASID_KERNEL) + ); + dsb(); +} + +static __inline void +tlb_flush_range(vm_offset_t va, vm_size_t size) +{ + vm_offset_t eva = va + size; + + KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va)); + KASSERT((size & PAGE_MASK) == 0, ("%s: size %#x not aligned", __func__, + size)); + + dsb(); + ARM_SMP_UP( + { + for (; va < eva; va += PAGE_SIZE) + _CP15_TLBIMVAAIS(va); + }, + { + for (; va < eva; va += PAGE_SIZE) + _CP15_TLBIMVA(va | CPU_ASID_KERNEL); + } + ); + dsb(); +} +#else /* __ARM_ARCH < 7 */ + +#define tlb_flush_all() tlb_flush_all_local() +#define tlb_flush_all_ng() tlb_flush_all_ng_local() +#define tlb_flush(va) tlb_flush_local(va) +#define tlb_flush_range(va, size) tlb_flush_range_local(va, size) + +#endif /* __ARM_ARCH < 7 */ + +/* + * Cache maintenance operations. + */ + +/* Sync I and D caches to PoU */ +static __inline void +icache_sync(vm_offset_t va, vm_size_t size) +{ + vm_offset_t eva = va + size; + + dsb(); + va &= ~cpuinfo.dcache_line_mask; + + for ( ; va < eva; va += cpuinfo.dcache_line_size) { +#if __ARM_ARCH >= 7 + _CP15_DCCMVAU(va); +#else + _CP15_DCCMVAC(va); +#endif + } + dsb(); + ARM_SMP_UP( + _CP15_ICIALLUIS(), + _CP15_ICIALLU() + ); + dsb(); + isb(); +} + +/* Invalidate I cache */ +static __inline void +icache_inv_all(void) +{ + + ARM_SMP_UP( + _CP15_ICIALLUIS(), + _CP15_ICIALLU() + ); + dsb(); + isb(); +} + +/* Invalidate branch predictor buffer */ +static __inline void +bpb_inv_all(void) +{ + + ARM_SMP_UP( + _CP15_BPIALLIS(), + _CP15_BPIALL() + ); + dsb(); + isb(); +} + +/* Write back D-cache to PoU */ +static __inline void +dcache_wb_pou(vm_offset_t va, vm_size_t size) +{ + vm_offset_t eva = va + size; + + dsb(); + va &= ~cpuinfo.dcache_line_mask; + for ( ; va < eva; va += cpuinfo.dcache_line_size) { +#if __ARM_ARCH >= 7 + _CP15_DCCMVAU(va); +#else + _CP15_DCCMVAC(va); +#endif + } + dsb(); +} + +/* + * Invalidate D-cache to PoC + * + * Caches are invalidated from outermost to innermost as fresh cachelines + * flow in this direction. In given range, if there was no dirty cacheline + * in any cache before, no stale cacheline should remain in them after this + * operation finishes. + */ +static __inline void +dcache_inv_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size) +{ + vm_offset_t eva = va + size; + + dsb(); + /* invalidate L2 first */ + cpu_l2cache_inv_range(pa, size); + + /* then L1 */ + va &= ~cpuinfo.dcache_line_mask; + for ( ; va < eva; va += cpuinfo.dcache_line_size) { + _CP15_DCIMVAC(va); + } + dsb(); +} + +/* + * Discard D-cache lines to PoC, prior to overwrite by DMA engine. + * + * Normal invalidation does L2 then L1 to ensure that stale data from L2 doesn't + * flow into L1 while invalidating. This routine is intended to be used only + * when invalidating a buffer before a DMA operation loads new data into memory. + * The concern in this case is that dirty lines are not evicted to main memory, + * overwriting the DMA data. For that reason, the L1 is done first to ensure + * that an evicted L1 line doesn't flow to L2 after the L2 has been cleaned. + */ +static __inline void +dcache_inv_poc_dma(vm_offset_t va, vm_paddr_t pa, vm_size_t size) +{ + vm_offset_t eva = va + size; + + /* invalidate L1 first */ + dsb(); + va &= ~cpuinfo.dcache_line_mask; + for ( ; va < eva; va += cpuinfo.dcache_line_size) { + _CP15_DCIMVAC(va); + } + dsb(); + + /* then L2 */ + cpu_l2cache_inv_range(pa, size); +} + +/* + * Write back D-cache to PoC + * + * Caches are written back from innermost to outermost as dirty cachelines + * flow in this direction. In given range, no dirty cacheline should remain + * in any cache after this operation finishes. + */ +static __inline void +dcache_wb_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size) +{ + vm_offset_t eva = va + size; + + dsb(); + va &= ~cpuinfo.dcache_line_mask; + for ( ; va < eva; va += cpuinfo.dcache_line_size) { + _CP15_DCCMVAC(va); + } + dsb(); + + cpu_l2cache_wb_range(pa, size); +} + +/* Write back and invalidate D-cache to PoC */ +static __inline void +dcache_wbinv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size) +{ + vm_offset_t va; + vm_offset_t eva = sva + size; + + dsb(); + /* write back L1 first */ + va = sva & ~cpuinfo.dcache_line_mask; + for ( ; va < eva; va += cpuinfo.dcache_line_size) { + _CP15_DCCMVAC(va); + } + dsb(); + + /* then write back and invalidate L2 */ + cpu_l2cache_wbinv_range(pa, size); + + /* then invalidate L1 */ + va = sva & ~cpuinfo.dcache_line_mask; + for ( ; va < eva; va += cpuinfo.dcache_line_size) { + _CP15_DCIMVAC(va); + } + dsb(); +} + +/* Set TTB0 register */ +static __inline void +cp15_ttbr_set(uint32_t reg) +{ + dsb(); + _CP15_TTB_SET(reg); + dsb(); + _CP15_BPIALL(); + dsb(); + isb(); + tlb_flush_all_ng_local(); +} + +/* + * Functions for address checking: + * + * cp15_ats1cpr_check() ... check stage 1 privileged (PL1) read access + * cp15_ats1cpw_check() ... check stage 1 privileged (PL1) write access + * cp15_ats1cur_check() ... check stage 1 unprivileged (PL0) read access + * cp15_ats1cuw_check() ... check stage 1 unprivileged (PL0) write access + * + * They must be called while interrupts are disabled to get consistent result. + */ +static __inline int +cp15_ats1cpr_check(vm_offset_t addr) +{ + + cp15_ats1cpr_set(addr); + isb(); + return (cp15_par_get() & 0x01 ? EFAULT : 0); +} + +static __inline int +cp15_ats1cpw_check(vm_offset_t addr) +{ + + cp15_ats1cpw_set(addr); + isb(); + return (cp15_par_get() & 0x01 ? EFAULT : 0); +} + +static __inline int +cp15_ats1cur_check(vm_offset_t addr) +{ + + cp15_ats1cur_set(addr); + isb(); + return (cp15_par_get() & 0x01 ? EFAULT : 0); +} + +static __inline int +cp15_ats1cuw_check(vm_offset_t addr) +{ + + cp15_ats1cuw_set(addr); + isb(); + return (cp15_par_get() & 0x01 ? EFAULT : 0); +} + +#endif /* !MACHINE_CPU_V6_H */ diff --git a/sys/arm/include/cpu.h b/sys/arm/include/cpu.h new file mode 100644 index 000000000000..8937a87aebea --- /dev/null +++ b/sys/arm/include/cpu.h @@ -0,0 +1,90 @@ +/* $NetBSD: cpu.h,v 1.2 2001/02/23 21:23:52 reinoud Exp $ */ +/* $FreeBSD$ */ + +#ifndef MACHINE_CPU_H +#define MACHINE_CPU_H + +#include <machine/armreg.h> +#include <machine/frame.h> + +void cpu_halt(void); +void swi_vm(void *); + +#ifdef _KERNEL +#include <machine/cpu-v6.h> + +static __inline uint64_t +get_cyclecount(void) +{ +#if __ARM_ARCH > 6 || (__ARM_ARCH == 6 && defined(CPU_ARM1176)) +#if (__ARM_ARCH > 6) && defined(DEV_PMU) + if (pmu_attched) { + u_int cpu; + uint64_t h, h2; + uint32_t l, r; + + cpu = PCPU_GET(cpuid); + h = (uint64_t)atomic_load_acq_32(&ccnt_hi[cpu]); + l = cp15_pmccntr_get(); + /* In case interrupts are disabled we need to check for overflow. */ + r = cp15_pmovsr_get(); + if (r & PMU_OVSR_C) { + atomic_add_32(&ccnt_hi[cpu], 1); + /* Clear the event. */ + cp15_pmovsr_set(PMU_OVSR_C); + } + /* Make sure there was no wrap-around while we read the lo half. */ + h2 = (uint64_t)atomic_load_acq_32(&ccnt_hi[cpu]); + if (h != h2) + l = cp15_pmccntr_get(); + return (h2 << 32 | l); + } else +#endif + return cp15_pmccntr_get(); +#else /* No performance counters, so use binuptime(9). This is slooooow */ + struct bintime bt; + + binuptime(&bt); + return ((uint64_t)bt.sec << 56 | bt.frac >> 8); +#endif +} +#endif + +#define TRAPF_USERMODE(frame) ((frame->tf_spsr & PSR_MODE) == PSR_USR32_MODE) + +#define TRAPF_PC(tfp) ((tfp)->tf_pc) + +#define cpu_getstack(td) ((td)->td_frame->tf_usr_sp) +#define cpu_setstack(td, sp) ((td)->td_frame->tf_usr_sp = (sp)) +#define cpu_spinwait() /* nothing */ +#define cpu_lock_delay() DELAY(1) + +#define ARM_NVEC 8 +#define ARM_VEC_ALL 0xffffffff + +extern vm_offset_t vector_page; + +/* + * Params passed into initarm. If you change the size of this you will + * need to update locore.S to allocate more memory on the stack before + * it calls initarm. + */ +struct arm_boot_params { + register_t abp_size; /* Size of this structure */ + register_t abp_r0; /* r0 from the boot loader */ + register_t abp_r1; /* r1 from the boot loader */ + register_t abp_r2; /* r2 from the boot loader */ + register_t abp_r3; /* r3 from the boot loader */ + vm_offset_t abp_physaddr; /* The kernel physical address */ + vm_offset_t abp_pagetable; /* The early page table */ +}; + +void arm_vector_init(vm_offset_t, int); +void fork_trampoline(void); +void identify_arm_cpu(void); +void *initarm(struct arm_boot_params *); + +extern char btext[]; +extern char etext[]; +int badaddr_read(void *, size_t, void *); +#endif /* !MACHINE_CPU_H */ diff --git a/sys/arm/include/cpufunc.h b/sys/arm/include/cpufunc.h new file mode 100644 index 000000000000..a5db3486aff1 --- /dev/null +++ b/sys/arm/include/cpufunc.h @@ -0,0 +1,259 @@ +/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ + +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (c) 1997 Mark Brinicombe. + * Copyright (c) 1997 Causality Limited + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Causality Limited. + * 4. The name of Causality Limited may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * RiscBSD kernel project + * + * cpufunc.h + * + * Prototypes for cpu, mmu and tlb related functions. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_CPUFUNC_H_ +#define _MACHINE_CPUFUNC_H_ + +#ifdef _KERNEL + +#include <sys/types.h> +#include <machine/armreg.h> + +static __inline void +breakpoint(void) +{ + __asm("udf 0xffff"); +} + +struct cpu_functions { + /* CPU functions */ + void (*cf_l2cache_wbinv_all) (void); + void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t); + void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t); + void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t); + void (*cf_l2cache_drain_writebuf) (void); + + /* Other functions */ + + void (*cf_sleep) (int mode); + + void (*cf_setup) (void); +}; + +extern struct cpu_functions cpufuncs; +extern u_int cputype; + +#define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all() +#define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s)) +#define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s)) +#define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s)) +#define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf() + +#define cpu_sleep(m) cpufuncs.cf_sleep(m) + +#define cpu_setup() cpufuncs.cf_setup() + +int set_cpufuncs (void); +#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ + +void cpufunc_nullop (void); +u_int cpufunc_control (u_int clear, u_int bic); + + +#if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT) +void armv7_cpu_sleep (int); +#endif +#if defined(CPU_MV_PJ4B) +void pj4b_config (void); +#endif + +#if defined(CPU_ARM1176) +void arm11x6_sleep (int); /* no ref. for errata */ +#endif + + +/* + * Macros for manipulating CPU interrupts + */ +#define __ARM_INTR_BITS (PSR_I | PSR_F | PSR_A) + +static __inline uint32_t +__set_cpsr(uint32_t bic, uint32_t eor) +{ + uint32_t tmp, ret; + + __asm __volatile( + "mrs %0, cpsr\n" /* Get the CPSR */ + "bic %1, %0, %2\n" /* Clear bits */ + "eor %1, %1, %3\n" /* XOR bits */ + "msr cpsr_xc, %1\n" /* Set the CPSR */ + : "=&r" (ret), "=&r" (tmp) + : "r" (bic), "r" (eor) : "memory"); + + return ret; +} + +static __inline uint32_t +disable_interrupts(uint32_t mask) +{ + + return (__set_cpsr(mask & __ARM_INTR_BITS, mask & __ARM_INTR_BITS)); +} + +static __inline uint32_t +enable_interrupts(uint32_t mask) +{ + + return (__set_cpsr(mask & __ARM_INTR_BITS, 0)); +} + +static __inline uint32_t +restore_interrupts(uint32_t old_cpsr) +{ + + return (__set_cpsr(__ARM_INTR_BITS, old_cpsr & __ARM_INTR_BITS)); +} + +static __inline register_t +intr_disable(void) +{ + + return (disable_interrupts(PSR_I | PSR_F)); +} + +static __inline void +intr_restore(register_t s) +{ + + restore_interrupts(s); +} +#undef __ARM_INTR_BITS + +/* + * Functions to manipulate cpu r13 + * (in arm/arm32/setstack.S) + */ + +void set_stackptr (u_int mode, u_int address); +u_int get_stackptr (u_int mode); + +/* + * CPU functions from locore.S + */ + +void cpu_reset (void) __attribute__((__noreturn__)); + +/* + * Cache info variables. + */ + +/* PRIMARY CACHE VARIABLES */ +extern int arm_dcache_align; +extern int arm_dcache_align_mask; + + +#define HAVE_INLINE_FFS + +static __inline __pure2 int +ffs(int mask) +{ + + return (__builtin_ffs(mask)); +} + +#define HAVE_INLINE_FFSL + +static __inline __pure2 int +ffsl(long mask) +{ + + return (__builtin_ffsl(mask)); +} + +#define HAVE_INLINE_FFSLL + +static __inline __pure2 int +ffsll(long long mask) +{ + + return (__builtin_ffsll(mask)); +} + +#define HAVE_INLINE_FLS + +static __inline __pure2 int +fls(int mask) +{ + + return (mask == 0 ? 0 : + 8 * sizeof(mask) - __builtin_clz((u_int)mask)); +} + +#define HAVE_INLINE_FLSL + +static __inline __pure2 int +flsl(long mask) +{ + + return (mask == 0 ? 0 : + 8 * sizeof(mask) - __builtin_clzl((u_long)mask)); +} + +#define HAVE_INLINE_FLSLL + +static __inline __pure2 int +flsll(long long mask) +{ + + return (mask == 0 ? 0 : + 8 * sizeof(mask) - __builtin_clzll((unsigned long long)mask)); +} +#else /* !_KERNEL */ + +static __inline void +breakpoint(void) +{ + + /* + * This matches the instruction used by GDB for software + * breakpoints. + */ + __asm("udf 0xfdee"); +} + +#endif /* _KERNEL */ +#endif /* _MACHINE_CPUFUNC_H_ */ + +/* End of cpufunc.h */ diff --git a/sys/arm/include/cpuinfo.h b/sys/arm/include/cpuinfo.h new file mode 100644 index 000000000000..97e063d384c2 --- /dev/null +++ b/sys/arm/include/cpuinfo.h @@ -0,0 +1,129 @@ +/*- + * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com> + * Copyright 2014 Michal Meloun <meloun@miracle.cz> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_CPUINFO_H_ +#define _MACHINE_CPUINFO_H_ + +#include <sys/types.h> + +#define CPU_IMPLEMENTER_ARM 0x41 +#define CPU_IMPLEMENTER_QCOM 0x51 +#define CPU_IMPLEMENTER_MRVL 0x56 + +/* ARM */ +#define CPU_ARCH_ARM1176 0xB76 +#define CPU_ARCH_CORTEX_A5 0xC05 +#define CPU_ARCH_CORTEX_A7 0xC07 +#define CPU_ARCH_CORTEX_A8 0xC08 +#define CPU_ARCH_CORTEX_A9 0xC09 +#define CPU_ARCH_CORTEX_A12 0xC0D +#define CPU_ARCH_CORTEX_A15 0xC0F +#define CPU_ARCH_CORTEX_A17 0xC11 +#define CPU_ARCH_CORTEX_A53 0xD03 +#define CPU_ARCH_CORTEX_A57 0xD07 +#define CPU_ARCH_CORTEX_A72 0xD08 +#define CPU_ARCH_CORTEX_A73 0xD09 +#define CPU_ARCH_CORTEX_A75 0xD0A + +/* QCOM */ +#define CPU_ARCH_KRAIT_300 0x06F + +/* MRVL */ +#define CPU_ARCH_SHEEVA_581 0x581 /* PJ4/PJ4B */ +#define CPU_ARCH_SHEEVA_584 0x584 /* PJ4B-MP/PJ4C */ + +struct cpuinfo { + /* raw id registers */ + uint32_t midr; + uint32_t ctr; + uint32_t tcmtr; + uint32_t tlbtr; + uint32_t mpidr; + uint32_t revidr; + uint32_t id_pfr0; + uint32_t id_pfr1; + uint32_t id_dfr0; + uint32_t id_afr0; + uint32_t id_mmfr0; + uint32_t id_mmfr1; + uint32_t id_mmfr2; + uint32_t id_mmfr3; + uint32_t id_isar0; + uint32_t id_isar1; + uint32_t id_isar2; + uint32_t id_isar3; + uint32_t id_isar4; + uint32_t id_isar5; + uint32_t cbar; + uint32_t ccsidr; + uint32_t clidr; + + /* Parsed bits of above registers... */ + + /* midr */ + int implementer; + int revision; + int architecture; + int part_number; + int patch; + + /* id_mmfr0 */ + int outermost_shareability; + int shareability_levels; + int auxiliary_registers; + int innermost_shareability; + + /* id_mmfr1 */ + int mem_barrier; + + /* id_mmfr3 */ + int coherent_walk; + int maintenance_broadcast; + + /* id_pfr1 */ + int generic_timer_ext; + int virtualization_ext; + int security_ext; + + /* L1 cache info */ + int dcache_line_size; + int dcache_line_mask; + int icache_line_size; + int icache_line_mask; + + /* mpidr */ + int mp_ext; +}; + +extern struct cpuinfo cpuinfo; + +void cpuinfo_init(void); +void cpuinfo_init_bp_hardening(void); +void cpuinfo_reinit_mmu(uint32_t ttb); +#endif /* _MACHINE_CPUINFO_H_ */ diff --git a/sys/arm/include/db_machdep.h b/sys/arm/include/db_machdep.h new file mode 100644 index 000000000000..d6d5ade51a86 --- /dev/null +++ b/sys/arm/include/db_machdep.h @@ -0,0 +1,94 @@ +/*- + * Mach Operating System + * Copyright (c) 1991,1990 Carnegie Mellon University + * All Rights Reserved. + * + * Permission to use, copy, modify and distribute this software and its + * documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR + * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie Mellon + * the rights to redistribute these changes. + * + * from: FreeBSD: src/sys/i386/include/db_machdep.h,v 1.16 1999/10/04 + * $FreeBSD$ + */ + +#ifndef _MACHINE_DB_MACHDEP_H_ +#define _MACHINE_DB_MACHDEP_H_ + +#include <machine/frame.h> +#include <machine/trap.h> +#include <machine/armreg.h> + +#define T_BREAKPOINT (1) +#define T_WATCHPOINT (2) +typedef vm_offset_t db_addr_t; +typedef int db_expr_t; + +#define PC_REGS() ((db_addr_t)kdb_thrctx->pcb_regs.sf_pc) + +#define BKPT_INST (KERNEL_BREAKPOINT) +#define BKPT_SIZE (INSN_SIZE) +#define BKPT_SET(inst) (BKPT_INST) + +#define BKPT_SKIP do { \ + kdb_frame->tf_pc += BKPT_SIZE; \ +} while (0) + +#define db_clear_single_step kdb_cpu_clear_singlestep +#define db_set_single_step kdb_cpu_set_singlestep +#define db_pc_is_singlestep kdb_cpu_pc_is_singlestep + +#define IS_BREAKPOINT_TRAP(type, code) (type == T_BREAKPOINT) +#define IS_WATCHPOINT_TRAP(type, code) (type == T_WATCHPOINT) + +#define inst_trap_return(ins) (0) +/* ldmxx reg, {..., pc} + 01800000 stack mode + 000f0000 register + 0000ffff register list */ +/* mov pc, reg + 0000000f register */ +#define inst_return(ins) (((ins) & 0x0e108000) == 0x08108000 || \ + ((ins) & 0x0ff0fff0) == 0x01a0f000 || \ + ((ins) & 0x0ffffff0) == 0x012fff10) /* bx */ +/* bl ... + 00ffffff offset>>2 */ +#define inst_call(ins) (((ins) & 0x0f000000) == 0x0b000000) +/* b ... + 00ffffff offset>>2 */ +/* ldr pc, [pc, reg, lsl #2] + 0000000f register */ + +#define inst_branch(ins) (((ins) & 0x0f000000) == 0x0a000000 || \ + ((ins) & 0x0fdffff0) == 0x079ff100 || \ + ((ins) & 0x0cd0f000) == 0x0490f000 || \ + ((ins) & 0x0ffffff0) == 0x012fff30 || /* blx */ \ + ((ins) & 0x0de0f000) == 0x0080f000) + +#define inst_load(ins) (0) +#define inst_store(ins) (0) + +#define next_instr_address(pc, bd) ((bd) ? (pc) : ((pc) + INSN_SIZE)) + +#define DB_ELFSIZE 32 + +int db_validate_address(vm_offset_t); + +u_int branch_taken (u_int insn, db_addr_t pc); + +#endif /* !_MACHINE_DB_MACHDEP_H_ */ diff --git a/sys/arm/include/debug_monitor.h b/sys/arm/include/debug_monitor.h new file mode 100644 index 000000000000..c160397393ad --- /dev/null +++ b/sys/arm/include/debug_monitor.h @@ -0,0 +1,60 @@ +/*- + * Copyright (c) 2014 The FreeBSD Foundation + * All rights reserved. + * + * This software was developed by Semihalf under + * the sponsorship of the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_DEBUG_MONITOR_H_ +#define _MACHINE_DEBUG_MONITOR_H_ + +#ifdef DDB + +#include <machine/db_machdep.h> + +enum dbg_access_t { + HW_BREAKPOINT_X = 0, + HW_WATCHPOINT_R = 1, + HW_WATCHPOINT_W = 2, + HW_WATCHPOINT_RW = HW_WATCHPOINT_R | HW_WATCHPOINT_W, +}; + +void dbg_monitor_init(void); +void dbg_monitor_init_secondary(void); +void dbg_show_watchpoint(void); +int dbg_setup_watchpoint(db_expr_t, db_expr_t, enum dbg_access_t); +int dbg_remove_watchpoint(db_expr_t, db_expr_t); +void dbg_resume_dbreg(void); + +#else /* DDB */ +static __inline void +dbg_monitor_init(void) +{ +} +#endif + +#endif /* _MACHINE_DEBUG_MONITOR_H_ */ diff --git a/sys/arm/include/disassem.h b/sys/arm/include/disassem.h new file mode 100644 index 000000000000..2ef5cda04c2f --- /dev/null +++ b/sys/arm/include/disassem.h @@ -0,0 +1,56 @@ +/* $NetBSD: disassem.h,v 1.4 2001/03/04 04:15:58 matt Exp $ */ + +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (c) 1997 Mark Brinicombe. + * Copyright (c) 1997 Causality Limited. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Mark Brinicombe. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * Define the interface structure required by the disassembler. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_DISASSEM_H_ +#define _MACHINE_DISASSEM_H_ +typedef struct { + u_int (*di_readword)(u_int); + void (*di_printaddr)(u_int); + int (*di_printf)(const char *, ...) __printflike(1, 2); +} disasm_interface_t; + +/* Prototypes for callable functions */ + +vm_offset_t disasm(const disasm_interface_t *, vm_offset_t, int); +void disassemble(u_int); + +#endif /* !_MACHINE_DISASSEM_H_ */ diff --git a/sys/arm/include/dump.h b/sys/arm/include/dump.h new file mode 100644 index 000000000000..3a7432fd49d3 --- /dev/null +++ b/sys/arm/include/dump.h @@ -0,0 +1,70 @@ +/*- + * Copyright (c) 2014 EMC Corp. + * Author: Conrad Meyer <conrad.meyer@isilon.com> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_DUMP_H_ +#define _MACHINE_DUMP_H_ + +#define KERNELDUMP_ARCH_VERSION KERNELDUMP_ARM_VERSION +#define EM_VALUE EM_ARM +/* XXX: I suppose 20 should be enough. */ +#define DUMPSYS_MD_PA_NPAIRS 20 +#define DUMPSYS_NUM_AUX_HDRS 1 + +void dumpsys_wbinv_all(void); +int dumpsys_write_aux_headers(struct dumperinfo *di); + +static inline void +dumpsys_pa_init(void) +{ + + dumpsys_gen_pa_init(); +} + +static inline struct dump_pa * +dumpsys_pa_next(struct dump_pa *p) +{ + + return (dumpsys_gen_pa_next(p)); +} + +static inline void +dumpsys_unmap_chunk(vm_paddr_t pa, size_t s, void *va) +{ + + dumpsys_gen_unmap_chunk(pa, s, va); +} + +static inline int +dumpsys(struct dumperinfo *di) +{ + + return (dumpsys_generic(di)); +} + +#endif /* !_MACHINE_DUMP_H_ */ diff --git a/sys/arm/include/efi.h b/sys/arm/include/efi.h new file mode 100644 index 000000000000..02e1e7e975ef --- /dev/null +++ b/sys/arm/include/efi.h @@ -0,0 +1,12 @@ +/*- + * This file is in the public domain since it's just boilerplate. + * + * $FreeBSD$ + */ + +#ifndef __ARM_INCLUDE_EFI_H_ +#define __ARM_INCLUDE_EFI_H_ + +#define EFIABI_ATTR + +#endif /* __ARM_INCLUDE_EFI_H_ */ diff --git a/sys/arm/include/elf.h b/sys/arm/include/elf.h new file mode 100644 index 000000000000..affd4b349163 --- /dev/null +++ b/sys/arm/include/elf.h @@ -0,0 +1,115 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2001 David E. O'Brien + * Copyright (c) 1996-1997 John D. Polstra. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_ELF_H_ +#define _MACHINE_ELF_H_ 1 + +/* + * EABI ELF definitions for the StrongARM architecture. + * See "ARM ELF", document no. `SWS ESPC 0003 A-08' for details. + */ + +#include <sys/elf32.h> /* Definitions common to all 32 bit architectures. */ + +#define __ELF_WORD_SIZE 32 /* Used by <sys/elf_generic.h> */ +#include <sys/elf_generic.h> + +typedef struct { /* Auxiliary vector entry on initial stack */ + int a_type; /* Entry type. */ + union { + long a_val; /* Integer value. */ + void *a_ptr; /* Address. */ + void (*a_fcn)(void); /* Function pointer (not used). */ + } a_un; +} Elf32_Auxinfo; + +__ElfType(Auxinfo); + +#define ELF_ARCH EM_ARM + +#define ELF_MACHINE_OK(x) ((x) == EM_ARM) + +/* + * Relocation types. + */ + +#define R_ARM_COUNT 33 /* Count of defined relocation types. */ + +/* Define "machine" characteristics */ +#define ELF_TARG_CLASS ELFCLASS32 +#ifdef __ARMEB__ +#define ELF_TARG_DATA ELFDATA2MSB +#else +#define ELF_TARG_DATA ELFDATA2LSB +#endif +#define ELF_TARG_MACH EM_ARM +#define ELF_TARG_VER 1 + +/* Defines specific for arm headers */ +#define EF_ARM_EABI_VERSION(x) (((x) & EF_ARM_EABIMASK) >> 24) +#define EF_ARM_EABI_VERSION_UNKNOWN 0 +#define EF_ARM_EABI_FREEBSD_MIN 4 + +#define ET_DYN_LOAD_ADDR 0x500000 + +/* Flags passed in AT_HWCAP. */ +#define HWCAP_SWP 0x00000001 /* Unsupported, never set. */ +#define HWCAP_HALF 0x00000002 /* Always set. */ +#define HWCAP_THUMB 0x00000004 +#define HWCAP_26BIT 0x00000008 /* Unsupported, never set. */ +#define HWCAP_FAST_MULT 0x00000010 /* Always set. */ +#define HWCAP_FPA 0x00000020 /* Unsupported, never set. */ +#define HWCAP_VFP 0x00000040 +#define HWCAP_EDSP 0x00000080 /* Always set for ARMv6+. */ +#define HWCAP_JAVA 0x00000100 /* Unsupported, never set. */ +#define HWCAP_IWMMXT 0x00000200 /* Unsupported, never set. */ +#define HWCAP_CRUNCH 0x00000400 /* Unsupported, never set. */ +#define HWCAP_THUMBEE 0x00000800 +#define HWCAP_NEON 0x00001000 +#define HWCAP_VFPv3 0x00002000 +#define HWCAP_VFPv3D16 0x00004000 +#define HWCAP_TLS 0x00008000 /* Always set for ARMv6+. */ +#define HWCAP_VFPv4 0x00010000 +#define HWCAP_IDIVA 0x00020000 +#define HWCAP_IDIVT 0x00040000 +#define HWCAP_VFPD32 0x00080000 +#define HWCAP_IDIV (HWCAP_IDIVA | HWCAP_IDIVT) +#define HWCAP_LPAE 0x00100000 +#define HWCAP_EVTSTRM 0x00200000 /* Not implemented yet. */ + +/* Flags passed in AT_HWCAP2. */ +#define HWCAP2_AES 0x00000001 +#define HWCAP2_PMULL 0x00000002 +#define HWCAP2_SHA1 0x00000004 +#define HWCAP2_SHA2 0x00000008 +#define HWCAP2_CRC32 0x00000010 + +#endif /* !_MACHINE_ELF_H_ */ diff --git a/sys/arm/include/endian.h b/sys/arm/include/endian.h new file mode 100644 index 000000000000..5fb94db3b9b8 --- /dev/null +++ b/sys/arm/include/endian.h @@ -0,0 +1,142 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2001 David E. O'Brien + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)endian.h 8.1 (Berkeley) 6/10/93 + * $NetBSD: endian.h,v 1.7 1999/08/21 05:53:51 simonb Exp $ + * $FreeBSD$ + */ + +#ifndef _ENDIAN_H_ +#define _ENDIAN_H_ + +#include <sys/_types.h> + +/* + * Definitions for byte order, according to byte significance from low + * address to high. + */ +#define _LITTLE_ENDIAN 1234 /* LSB first: i386, vax */ +#define _BIG_ENDIAN 4321 /* MSB first: 68000, ibm, net */ +#define _PDP_ENDIAN 3412 /* LSB first in word, MSW first in long */ + +#ifdef __ARMEB__ +#define _BYTE_ORDER _BIG_ENDIAN +#else +#define _BYTE_ORDER _LITTLE_ENDIAN +#endif /* __ARMEB__ */ + +#if __BSD_VISIBLE +#define LITTLE_ENDIAN _LITTLE_ENDIAN +#define BIG_ENDIAN _BIG_ENDIAN +#define PDP_ENDIAN _PDP_ENDIAN +#define BYTE_ORDER _BYTE_ORDER +#endif + +#ifdef __ARMEB__ +#define _QUAD_HIGHWORD 0 +#define _QUAD_LOWWORD 1 +#define __ntohl(x) ((__uint32_t)(x)) +#define __ntohs(x) ((__uint16_t)(x)) +#define __htonl(x) ((__uint32_t)(x)) +#define __htons(x) ((__uint16_t)(x)) +#else +#define _QUAD_HIGHWORD 1 +#define _QUAD_LOWWORD 0 +#define __ntohl(x) (__bswap32(x)) +#define __ntohs(x) (__bswap16(x)) +#define __htonl(x) (__bswap32(x)) +#define __htons(x) (__bswap16(x)) +#endif /* __ARMEB__ */ + +static __inline __uint64_t +__bswap64(__uint64_t _x) +{ + + return ((_x >> 56) | ((_x >> 40) & 0xff00) | ((_x >> 24) & 0xff0000) | + ((_x >> 8) & 0xff000000) | ((_x << 8) & ((__uint64_t)0xff << 32)) | + ((_x << 24) & ((__uint64_t)0xff << 40)) | + ((_x << 40) & ((__uint64_t)0xff << 48)) | ((_x << 56))); +} + +static __inline __uint32_t +__bswap32_var(__uint32_t v) +{ + __uint32_t t1; + + __asm __volatile("eor %1, %0, %0, ror #16\n" + "bic %1, %1, #0x00ff0000\n" + "mov %0, %0, ror #8\n" + "eor %0, %0, %1, lsr #8\n" + : "+r" (v), "=r" (t1)); + + return (v); +} + +static __inline __uint16_t +__bswap16_var(__uint16_t v) +{ + __uint32_t ret = v & 0xffff; + + __asm __volatile( + "mov %0, %0, ror #8\n" + "orr %0, %0, %0, lsr #16\n" + "bic %0, %0, %0, lsl #16" + : "+r" (ret)); + + return ((__uint16_t)ret); +} + +#ifdef __OPTIMIZE__ + +#define __bswap32_constant(x) \ + ((((x) & 0xff000000U) >> 24) | \ + (((x) & 0x00ff0000U) >> 8) | \ + (((x) & 0x0000ff00U) << 8) | \ + (((x) & 0x000000ffU) << 24)) + +#define __bswap16_constant(x) \ + ((((x) & 0xff00) >> 8) | \ + (((x) & 0x00ff) << 8)) + +#define __bswap16(x) \ + ((__uint16_t)(__builtin_constant_p(x) ? \ + __bswap16_constant(x) : \ + __bswap16_var(x))) + +#define __bswap32(x) \ + ((__uint32_t)(__builtin_constant_p(x) ? \ + __bswap32_constant(x) : \ + __bswap32_var(x))) + +#else +#define __bswap16(x) __bswap16_var(x) +#define __bswap32(x) __bswap32_var(x) + +#endif /* __OPTIMIZE__ */ +#endif /* !_ENDIAN_H_ */ diff --git a/sys/arm/include/exec.h b/sys/arm/include/exec.h new file mode 100644 index 000000000000..be6bc6f8677b --- /dev/null +++ b/sys/arm/include/exec.h @@ -0,0 +1,39 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2001 David E. O'Brien + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY JOHN BIRRELL AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_EXEC_H_ +#define _MACHINE_EXEC_H_ + +#define __LDPGSZ 4096 + +#endif /* !_MACHINE_EXEC_H_ */ diff --git a/sys/arm/include/fdt.h b/sys/arm/include/fdt.h new file mode 100644 index 000000000000..e8af11c8c4b0 --- /dev/null +++ b/sys/arm/include/fdt.h @@ -0,0 +1,44 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2010 The FreeBSD Foundation + * All rights reserved. + * + * This software was developed by Semihalf under sponsorship from + * the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_FDT_H_ +#define _MACHINE_FDT_H_ + +#include <machine/bus.h> + +/* + * Bus space tag. XXX endianess info needs to be derived from the blob. + */ +extern bus_space_tag_t fdtbus_bs_tag; + +#endif /* _MACHINE_FDT_H_ */ diff --git a/sys/arm/include/fiq.h b/sys/arm/include/fiq.h new file mode 100644 index 000000000000..a075c99e7d9b --- /dev/null +++ b/sys/arm/include/fiq.h @@ -0,0 +1,73 @@ +/* $NetBSD: fiq.h,v 1.1 2001/12/20 01:20:23 thorpej Exp $ */ + +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (c) 2001 Wasabi Systems, Inc. + * All rights reserved. + * + * Written by Jason R. Thorpe for Wasabi Systems, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Wasabi Systems, Inc. + * 4. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + * + */ + +#ifndef _MACHINE_FIQ_H_ +#define _MACHINE_FIQ_H_ + +#include <sys/queue.h> + +struct fiqregs { + u_int fr_r8; /* FIQ mode r8 */ + u_int fr_r9; /* FIQ mode r9 */ + u_int fr_r10; /* FIQ mode r10 */ + u_int fr_r11; /* FIQ mode r11 */ + u_int fr_r12; /* FIQ mode r12 */ + u_int fr_r13; /* FIQ mode r13 */ +}; + +struct fiqhandler { + TAILQ_ENTRY(fiqhandler) fh_list;/* link in the FIQ handler stack */ + void *fh_func; /* FIQ handler routine */ + size_t fh_size; /* size of FIQ handler */ + int fh_flags; /* flags; see below */ + struct fiqregs *fh_regs; /* pointer to regs structure */ +}; + +#define FH_CANPUSH 0x01 /* can push this handler out of the way */ + +int fiq_claim(struct fiqhandler *); +void fiq_release(struct fiqhandler *); + +void fiq_getregs(struct fiqregs *); +void fiq_setregs(struct fiqregs *); + +#endif /* _MACHINE_FIQ_H_ */ diff --git a/sys/arm/include/float.h b/sys/arm/include/float.h new file mode 100644 index 000000000000..857d76ea57e7 --- /dev/null +++ b/sys/arm/include/float.h @@ -0,0 +1,100 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 1989 Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: @(#)float.h 7.1 (Berkeley) 5/8/90 + * $FreeBSD$ + */ + +#ifndef _MACHINE_FLOAT_H_ +#define _MACHINE_FLOAT_H_ 1 + +#include <sys/cdefs.h> + +__BEGIN_DECLS +extern int __flt_rounds(void); +__END_DECLS + +#define FLT_RADIX 2 /* b */ +#ifndef _ARM_HARD_FLOAT +#define FLT_ROUNDS __flt_rounds() +#else +#define FLT_ROUNDS (-1) +#endif +#if __ISO_C_VISIBLE >= 1999 +#define FLT_EVAL_METHOD 0 +#define DECIMAL_DIG 17 /* max precision in decimal digits */ +#endif + +#define FLT_MANT_DIG 24 /* p */ +#define FLT_EPSILON 1.19209290E-07F /* b**(1-p) */ +#define FLT_DIG 6 /* floor((p-1)*log10(b))+(b == 10) */ +#define FLT_MIN_EXP (-125) /* emin */ +#define FLT_MIN 1.17549435E-38F /* b**(emin-1) */ +#define FLT_MIN_10_EXP (-37) /* ceil(log10(b**(emin-1))) */ +#define FLT_MAX_EXP 128 /* emax */ +#define FLT_MAX 3.40282347E+38F /* (1-b**(-p))*b**emax */ +#define FLT_MAX_10_EXP 38 /* floor(log10((1-b**(-p))*b**emax)) */ +#if __ISO_C_VISIBLE >= 2011 +#define FLT_TRUE_MIN 1.40129846E-45F /* b**(emin-p) */ +#define FLT_DECIMAL_DIG 9 /* ceil(1+p*log10(b)) */ +#define FLT_HAS_SUBNORM 1 +#endif /* __ISO_C_VISIBLE >= 2011 */ + +#define DBL_MANT_DIG 53 +#define DBL_EPSILON 2.2204460492503131E-16 +#define DBL_DIG 15 +#define DBL_MIN_EXP (-1021) +#define DBL_MIN 2.2250738585072014E-308 +#define DBL_MIN_10_EXP (-307) +#define DBL_MAX_EXP 1024 +#define DBL_MAX 1.7976931348623157E+308 +#define DBL_MAX_10_EXP 308 +#if __ISO_C_VISIBLE >= 2011 +#define DBL_TRUE_MIN 4.9406564584124654E-324 +#define DBL_DECIMAL_DIG 17 +#define DBL_HAS_SUBNORM 1 +#endif /* __ISO_C_VISIBLE >= 2011 */ + +#define LDBL_MANT_DIG DBL_MANT_DIG +#define LDBL_EPSILON ((long double)DBL_EPSILON) +#define LDBL_DIG DBL_DIG +#define LDBL_MIN_EXP DBL_MIN_EXP +#define LDBL_MIN ((long double)DBL_MIN) +#define LDBL_MIN_10_EXP DBL_MIN_10_EXP +#define LDBL_MAX_EXP DBL_MAX_EXP +#define LDBL_MAX ((long double)DBL_MAX) +#define LDBL_MAX_10_EXP DBL_MAX_10_EXP +#if __ISO_C_VISIBLE >= 2011 +#define LDBL_TRUE_MIN ((long double)DBL_TRUE_MIN) +#define LDBL_DECIMAL_DIG DBL_DECIMAL_DIG +#define LDBL_HAS_SUBNORM DBL_HAS_SUBNORM +#endif /* __ISO_C_VISIBLE >= 2011 */ + +#endif /* _MACHINE_FLOAT_H_ */ diff --git a/sys/arm/include/floatingpoint.h b/sys/arm/include/floatingpoint.h new file mode 100644 index 000000000000..b1c28e91d79e --- /dev/null +++ b/sys/arm/include/floatingpoint.h @@ -0,0 +1,44 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (c) 1993 Andrew Moore, Talke Studio + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: @(#) floatingpoint.h 1.0 (Berkeley) 9/23/93 + * $FreeBSD$ + */ + +#ifndef _FLOATINGPOINT_H_ +#define _FLOATINGPOINT_H_ + +#include <machine/ieeefp.h> + +#endif /* !_FLOATINGPOINT_H_ */ diff --git a/sys/arm/include/frame.h b/sys/arm/include/frame.h new file mode 100644 index 000000000000..8866e8ab0a33 --- /dev/null +++ b/sys/arm/include/frame.h @@ -0,0 +1,137 @@ +/* $NetBSD: frame.h,v 1.5 2002/10/19 00:10:54 bjh21 Exp $ */ + +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (c) 1994-1997 Mark Brinicombe. + * Copyright (c) 1994 Brini. + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Brini. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * RiscBSD kernel project + * + * frame.h + * + * Stack frames structures + * + * Created : 30/09/94 + * + * $FreeBSD$ + * + */ + +#ifndef _MACHINE_FRAME_H_ +#define _MACHINE_FRAME_H_ + +#ifndef _LOCORE + +#include <sys/signal.h> +#include <sys/ucontext.h> + +/* + * Trap frame. Pushed onto the kernel stack on a trap (synchronous exception). + */ + +struct trapframe { + register_t tf_spsr; /* Zero on arm26 */ + register_t tf_r0; + register_t tf_r1; + register_t tf_r2; + register_t tf_r3; + register_t tf_r4; + register_t tf_r5; + register_t tf_r6; + register_t tf_r7; + register_t tf_r8; + register_t tf_r9; + register_t tf_r10; + register_t tf_r11; + register_t tf_r12; + register_t tf_usr_sp; + register_t tf_usr_lr; + register_t tf_svc_sp; /* Not used on arm26 */ + register_t tf_svc_lr; /* Not used on arm26 */ + register_t tf_pc; + register_t tf_pad; +}; + +/* Register numbers */ +#define tf_r13 tf_usr_sp +#define tf_r14 tf_usr_lr +#define tf_r15 tf_pc + +/* + * Signal frame. Pushed onto user stack before calling sigcode. + * The pointers are used in the trampoline code to locate the ucontext. + */ +struct sigframe { + siginfo_t sf_si; /* actual saved siginfo */ + ucontext_t sf_uc; /* actual saved ucontext */ + mcontext_vfp_t sf_vfp; /* actual saved VFP context */ +}; + +/* + * Switch frame. + * + * It is important this is a multiple of 8 bytes so the stack is correctly + * aligned when we create new threads. + */ +struct switchframe +{ + register_t sf_r4; + register_t sf_r5; + register_t sf_r6; + register_t sf_r7; + register_t sf_r8; + register_t sf_r9; + register_t sf_r10; + register_t sf_r11; + register_t sf_r12; + register_t sf_sp; + register_t sf_lr; + register_t sf_pc; + register_t sf_tpidrurw; + register_t sf_spare0; +}; + +/* + * Stack frame. Used during stack traces (db_trace.c) + */ +struct frame { + u_int fr_fp; + u_int fr_sp; + u_int fr_lr; + u_int fr_pc; +}; + +#endif /* !_LOCORE */ + +#endif /* _MACHINE_FRAME_H_ */ diff --git a/sys/arm/include/gdb_machdep.h b/sys/arm/include/gdb_machdep.h new file mode 100644 index 000000000000..017025253bd5 --- /dev/null +++ b/sys/arm/include/gdb_machdep.h @@ -0,0 +1,73 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2006 Olivier Houchard + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_GDB_MACHDEP_H_ +#define _MACHINE_GDB_MACHDEP_H_ + +#define GDB_BUFSZ 400 +#define GDB_NREGS 26 +#define GDB_REG_SP 13 +#define GDB_REG_LR 14 +#define GDB_REG_PC 15 + +static __inline size_t +gdb_cpu_regsz(int regnum) +{ + /* + * GDB expects the FPA registers f0-f7, each 96 bits wide, to be placed + * in between the PC and CSPR in response to a "g" packet. + */ + return (regnum >= 16 && regnum <= 23 ? 12 : sizeof(int)); +} + +static __inline int +gdb_cpu_query(void) +{ + return (0); +} + +static __inline void * +gdb_begin_write(void) +{ + + return (NULL); +} + +static __inline void +gdb_end_write(void *arg __unused) +{ + +} + +void *gdb_cpu_getreg(int, size_t *); +void gdb_cpu_setreg(int, void *); +int gdb_cpu_signal(int, int); + +#endif /* !_MACHINE_GDB_MACHDEP_H_ */ diff --git a/sys/arm/include/ieee.h b/sys/arm/include/ieee.h new file mode 100644 index 000000000000..0942eac8eadf --- /dev/null +++ b/sys/arm/include/ieee.h @@ -0,0 +1,167 @@ +/* $NetBSD: ieee754.h,v 1.4 2003/10/27 02:30:26 simonb Exp $ */ + +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This software was developed by the Computer Systems Engineering group + * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and + * contributed to Berkeley. + * + * All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Lawrence Berkeley Laboratory. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)ieee.h 8.1 (Berkeley) 6/11/93 + * + * $FreeBSD$ + * + */ + +/* + * NOTICE: This is not a standalone file. To use it, #include it in + * your port's ieee.h header. + */ + +#include <machine/endian.h> + +/* + * <sys/ieee754.h> defines the layout of IEEE 754 floating point types. + * Only single-precision and double-precision types are defined here; + * extended types, if available, are defined in the machine-dependent + * header. + */ + +/* + * Define the number of bits in each fraction and exponent. + * + * k k+1 + * Note that 1.0 x 2 == 0.1 x 2 and that denorms are represented + * + * (-exp_bias+1) + * as fractions that look like 0.fffff x 2 . This means that + * + * -126 + * the number 0.10000 x 2 , for instance, is the same as the normalized + * + * -127 -128 + * float 1.0 x 2 . Thus, to represent 2 , we need one leading zero + * + * -129 + * in the fraction; to represent 2 , we need two, and so on. This + * + * (-exp_bias-fracbits+1) + * implies that the smallest denormalized number is 2 + * + * for whichever format we are talking about: for single precision, for + * + * -126 -149 + * instance, we get .00000000000000000000001 x 2 , or 1.0 x 2 , and + * + * -149 == -127 - 23 + 1. + */ +#define SNG_EXPBITS 8 +#define SNG_FRACBITS 23 + +#define DBL_EXPBITS 11 +#define DBL_FRACBITS 52 + +#if defined(__VFP_FP__) || defined(__ARM_EABI__) +#define _IEEE_WORD_ORDER _BYTE_ORDER +#else +#define _IEEE_WORD_ORDER _BIG_ENDIAN +#endif + +struct ieee_single { +#if _BYTE_ORDER == _BIG_ENDIAN + u_int sng_sign:1; + u_int sng_exp:8; + u_int sng_frac:23; +#else + u_int sng_frac:23; + u_int sng_exp:8; + u_int sng_sign:1; +#endif +}; + +struct ieee_double { +#if _BYTE_ORDER == _BIG_ENDIAN + u_int dbl_sign:1; + u_int dbl_exp:11; + u_int dbl_frach:20; + u_int dbl_fracl; +#else +#if _IEEE_WORD_ORDER == _LITTLE_ENDIAN + u_int dbl_fracl; +#endif + u_int dbl_frach:20; + u_int dbl_exp:11; + u_int dbl_sign:1; +#if _IEEE_WORD_ORDER == _BIG_ENDIAN + u_int dbl_fracl; +#endif +#endif +}; + +/* + * Floats whose exponent is in [1..INFNAN) (of whatever type) are + * `normal'. Floats whose exponent is INFNAN are either Inf or NaN. + * Floats whose exponent is zero are either zero (iff all fraction + * bits are zero) or subnormal values. + * + * A NaN is a `signalling NaN' if its QUIETNAN bit is clear in its + * high fraction; if the bit is set, it is a `quiet NaN'. + */ +#define SNG_EXP_INFNAN 255 +#define DBL_EXP_INFNAN 2047 + +#if 0 +#define SNG_QUIETNAN (1 << 22) +#define DBL_QUIETNAN (1 << 19) +#endif + +/* + * Exponent biases. + */ +#define SNG_EXP_BIAS 127 +#define DBL_EXP_BIAS 1023 + +/* + * Convenience data structures. + */ +union ieee_single_u { + float sngu_f; + struct ieee_single sngu_sng; +}; + +union ieee_double_u { + double dblu_d; + struct ieee_double dblu_dbl; +}; diff --git a/sys/arm/include/ieeefp.h b/sys/arm/include/ieeefp.h new file mode 100644 index 000000000000..0b61744b450b --- /dev/null +++ b/sys/arm/include/ieeefp.h @@ -0,0 +1,53 @@ +/* $NetBSD: ieeefp.h,v 1.1 2001/01/10 19:02:06 bjh21 Exp $ */ +/* $FreeBSD$ */ +/*- + * Based on ieeefp.h written by J.T. Conklin, Apr 28, 1995 + * Public domain. + */ + +#ifndef _MACHINE_IEEEFP_H_ +#define _MACHINE_IEEEFP_H_ + +/* Deprecated historical FPU control interface */ + +/* FP exception codes */ +#define FP_EXCEPT_INV 0 +#define FP_EXCEPT_DZ 1 +#define FP_EXCEPT_OFL 2 +#define FP_EXCEPT_UFL 3 +#define FP_EXCEPT_IMP 4 + +/* Exception type (used by fpsetmask() et al.) */ + +typedef int fp_except; + +/* Bit defines for fp_except */ + +#define FP_X_INV (1 << FP_EXCEPT_INV) /* invalid operation exception */ +#define FP_X_DZ (1 << FP_EXCEPT_DZ) /* divide-by-zero exception */ +#define FP_X_OFL (1 << FP_EXCEPT_OFL) /* overflow exception */ +#define FP_X_UFL (1 << FP_EXCEPT_UFL) /* underflow exception */ +#define FP_X_IMP (1 << FP_EXCEPT_IMP) /* imprecise (loss of precision; "inexact") */ + +/* Rounding modes */ + +typedef enum { + FP_RN=0, /* round to nearest representable number */ + FP_RP=1, /* round toward positive infinity */ + FP_RM=2, /* round toward negative infinity */ + FP_RZ=3 /* round to zero (truncate) */ +} fp_rnd_t; + +/* + * FP precision modes + */ +typedef enum { + FP_PS=0, /* 24 bit (single-precision) */ + FP_PRS, /* reserved */ + FP_PD, /* 53 bit (double-precision) */ + FP_PE /* 64 bit (extended-precision) */ +} fp_prec_t; + +#define fp_except_t int + +#endif /* _MACHINE_IEEEFP_H_ */ diff --git a/sys/arm/include/in_cksum.h b/sys/arm/include/in_cksum.h new file mode 100644 index 000000000000..a75433830d73 --- /dev/null +++ b/sys/arm/include/in_cksum.h @@ -0,0 +1,66 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from tahoe: in_cksum.c 1.2 86/01/05 + * from: @(#)in_cksum.c 1.3 (Berkeley) 1/19/91 + * from: Id: in_cksum.c,v 1.8 1995/12/03 18:35:19 bde Exp + * $FreeBSD$ + */ + +#ifndef _MACHINE_IN_CKSUM_H_ +#define _MACHINE_IN_CKSUM_H_ 1 + +#include <sys/cdefs.h> + +#ifdef _KERNEL +u_short in_cksum(struct mbuf *m, int len); +u_short in_addword(u_short sum, u_short b); +u_short in_cksum_skip(struct mbuf *m, int len, int skip); +u_int do_cksum(const void *, int); +#if defined(IPVERSION) && (IPVERSION == 4) +u_int in_cksum_hdr(const struct ip *); +#endif + +static __inline u_short +in_pseudo(u_int sum, u_int b, u_int c) +{ + __asm __volatile("adds %0, %0, %1\n" + "adcs %0, %0, %2\n" + "adc %0, %0, #0\n" + : "+r" (sum) + : "r" (b), "r" (c)); + sum = (sum & 0xffff) + (sum >> 16); + if (sum > 0xffff) + sum -= 0xffff; + return (sum); +} + +#endif /* _KERNEL */ +#endif /* _MACHINE_IN_CKSUM_H_ */ diff --git a/sys/arm/include/intr.h b/sys/arm/include/intr.h new file mode 100644 index 000000000000..c783c41fd35d --- /dev/null +++ b/sys/arm/include/intr.h @@ -0,0 +1,69 @@ +/* $NetBSD: intr.h,v 1.7 2003/06/16 20:01:00 thorpej Exp $ */ + +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (c) 1997 Mark Brinicombe. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Mark Brinicombe + * for the NetBSD Project. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + * + */ + +#ifndef _MACHINE_INTR_H_ +#define _MACHINE_INTR_H_ + +#ifdef FDT +#include <dev/ofw/openfirm.h> +#endif + +#ifndef NIRQ +#define NIRQ 1024 /* XXX - It should be an option. */ +#endif + +#include <sys/intr.h> + +#ifdef SMP +typedef void intr_ipi_send_t(void *, cpuset_t, u_int); +typedef void intr_ipi_handler_t(void *); + +void intr_ipi_dispatch(u_int, struct trapframe *); +void intr_ipi_send(cpuset_t, u_int); + +void intr_ipi_setup(u_int, const char *, intr_ipi_handler_t *, void *, + intr_ipi_send_t *, void *); + +int intr_pic_ipi_setup(u_int, const char *, intr_ipi_handler_t *, void *); +#endif + +void arm_irq_memory_barrier(uintptr_t); + +#endif /* _MACHINE_INTR_H */ diff --git a/sys/arm/include/kdb.h b/sys/arm/include/kdb.h new file mode 100644 index 000000000000..42677499ed78 --- /dev/null +++ b/sys/arm/include/kdb.h @@ -0,0 +1,57 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2004 Marcel Moolenaar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_KDB_H_ +#define _MACHINE_KDB_H_ + +#include <machine/cpu.h> +#include <machine/db_machdep.h> +#include <machine/frame.h> +#include <machine/psl.h> + +#define KDB_STOPPEDPCB(pc) &stoppcbs[pc->pc_cpuid] + +extern void kdb_cpu_clear_singlestep(void); +extern void kdb_cpu_set_singlestep(void); +boolean_t kdb_cpu_pc_is_singlestep(db_addr_t); + +static __inline void +kdb_cpu_sync_icache(unsigned char *addr, size_t size) +{ + + icache_sync((vm_offset_t)addr, size); +} + +static __inline void +kdb_cpu_trap(int type, int code) +{ +} + +#endif /* _MACHINE_KDB_H_ */ diff --git a/sys/arm/include/limits.h b/sys/arm/include/limits.h new file mode 100644 index 000000000000..5a7b831b3089 --- /dev/null +++ b/sys/arm/include/limits.h @@ -0,0 +1,46 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 1988, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)limits.h 8.3 (Berkeley) 1/4/94 + * $FreeBSD$ + */ + +#ifndef _MACHINE_LIMITS_H_ +#define _MACHINE_LIMITS_H_ + +#include <sys/cdefs.h> + +#ifdef __CC_SUPPORTS_WARNING +#warning "machine/limits.h is deprecated. Include sys/limits.h instead." +#endif + +#include <sys/limits.h> + +#endif /* !_MACHINE_LIMITS_H_ */ diff --git a/sys/arm/include/machdep.h b/sys/arm/include/machdep.h new file mode 100644 index 000000000000..3efad39753d3 --- /dev/null +++ b/sys/arm/include/machdep.h @@ -0,0 +1,75 @@ +/* $NetBSD: machdep.h,v 1.7 2002/02/21 02:52:21 thorpej Exp $ */ +/* $FreeBSD$ */ + +#ifndef _MACHDEP_BOOT_MACHDEP_H_ +#define _MACHDEP_BOOT_MACHDEP_H_ + +/* Structs that need to be initialised by initarm */ +extern vm_offset_t irqstack; +extern vm_offset_t undstack; +extern vm_offset_t abtstack; + +/* Define various stack sizes in pages */ +#define IRQ_STACK_SIZE 1 +#define ABT_STACK_SIZE 1 +#define UND_STACK_SIZE 1 + +/* misc prototypes used by the many arm machdeps */ +struct trapframe; +void init_proc0(vm_offset_t kstack); +void halt(void); +void abort_handler(struct trapframe *, int ); +void set_stackptrs(int cpu); +void undefinedinstruction_bounce(struct trapframe *); + +/* Early boot related helper functions */ +struct arm_boot_params; +vm_offset_t default_parse_boot_param(struct arm_boot_params *abp); +vm_offset_t fake_preload_metadata(struct arm_boot_params *abp, + void *dtb_ptr, size_t dtb_size); +vm_offset_t parse_boot_param(struct arm_boot_params *abp); +void arm_parse_fdt_bootargs(void); +void arm_print_kenv(void); + +int arm_get_vfpstate(struct thread *td, void *args); + +/* Board-specific attributes */ +void board_set_serial(uint64_t); +void board_set_revision(uint32_t); + +int arm_predict_branch(void *, u_int, register_t, register_t *, + u_int (*)(void*, int), u_int (*)(void*, vm_offset_t, u_int*)); + +#ifdef PLATFORM +typedef void delay_func(int, void *); +void arm_set_delay(delay_func *, void *); +#endif + +#ifdef EFI +struct efi_map_header; +struct mem_region; +void arm_add_efi_map_entries(struct efi_map_header *efihdr, + struct mem_region *mr, int *mrcnt); +#endif + +/* + * Symbols created by ldscript.arm which are accessible in the kernel as global + * symbols. They have uint8 type because they mark the byte location where the + * corresponding data starts or ends (in the end case, it's the next byte + * following the data, so the data size is end-start). These are listed below + * in the order they occur within the kernel (i.e., the address of each variable + * should be greater than any of the ones before it). + */ +extern uint8_t _start; /* Kernel entry point in locore.S */ +extern uint8_t _etext; /* text segment end */ +extern uint8_t _extab_start; /* unwind table start */ +extern uint8_t _exidx_start; /* unwind index start */ +extern uint8_t _exidx_end; /* unwind index end */ +extern uint8_t _start_ctors; /* ctors data start */ +extern uint8_t _stop_ctors; /* ctors data end */ +extern uint8_t _edata; /* data segment end */ +extern uint8_t __bss_start; /* bss segment start */ +extern uint8_t _ebss; /* bss segment end */ +extern uint8_t _end; /* End of kernel (text+ctors+unwind+data+bss) */ + +#endif /* !_MACHINE_MACHDEP_H_ */ diff --git a/sys/arm/include/md_var.h b/sys/arm/include/md_var.h new file mode 100644 index 000000000000..d60992f104e1 --- /dev/null +++ b/sys/arm/include/md_var.h @@ -0,0 +1,71 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 1995 Bruce D. Evans. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the author nor the names of contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: FreeBSD: src/sys/i386/include/md_var.h,v 1.40 2001/07/12 + * $FreeBSD$ + */ + +#ifndef _MACHINE_MD_VAR_H_ +#define _MACHINE_MD_VAR_H_ + +extern long Maxmem; +extern char sigcode[]; +extern int szsigcode; +extern u_long elf_hwcap; +extern u_long elf_hwcap2; +extern vm_paddr_t arm_physmem_kernaddr; + +extern int (*_arm_memcpy)(void *, void *, int, int); +extern int (*_arm_bzero)(void *, int, int); + +extern int _min_memcpy_size; +extern int _min_bzero_size; + +#define DST_IS_USER 0x1 +#define SRC_IS_USER 0x2 +#define IS_PHYSICAL 0x4 + +enum cpu_class { + CPU_CLASS_NONE, + CPU_CLASS_CORTEXA, + CPU_CLASS_KRAIT, + CPU_CLASS_ARM11J, + CPU_CLASS_MARVELL +}; +extern enum cpu_class cpu_class; + +struct dumperinfo; +extern int busdma_swi_pending; +void busdma_swi(void); +int minidumpsys(struct dumperinfo *); + +extern uint32_t initial_fpscr; + +#endif /* !_MACHINE_MD_VAR_H_ */ diff --git a/sys/arm/include/memdev.h b/sys/arm/include/memdev.h new file mode 100644 index 000000000000..b9b2172d4647 --- /dev/null +++ b/sys/arm/include/memdev.h @@ -0,0 +1,42 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2004 Mark R V Murray + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer + * in this position and unchanged. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_MEMDEV_H_ +#define _MACHINE_MEMDEV_H_ + +#define CDEV_MINOR_MEM 0 +#define CDEV_MINOR_KMEM 1 + +d_open_t memopen; +d_read_t memrw; +d_mmap_t memmmap; +d_ioctl_t memioctl_md; + +#endif /* _MACHINE_MEMDEV_H_ */ diff --git a/sys/arm/include/metadata.h b/sys/arm/include/metadata.h new file mode 100644 index 000000000000..587fd901b379 --- /dev/null +++ b/sys/arm/include/metadata.h @@ -0,0 +1,59 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2003 Peter Wemm <peter@FreeBSD.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_METADATA_H_ +#define _MACHINE_METADATA_H_ + +#define MODINFOMD_BOOTINFO 0x1001 +#define MODINFOMD_DTBP 0x1002 +#define MODINFOMD_EFI_MAP 0x1003 + +struct efi_map_header { + uint64_t memory_size; + uint64_t descriptor_size; + uint32_t descriptor_version; +}; + +/* + * Placeholder for now + */ +struct efi_fb { + uint64_t fb_addr; + uint64_t fb_size; + uint32_t fb_height; + uint32_t fb_width; + uint32_t fb_stride; + uint32_t fb_mask_red; + uint32_t fb_mask_green; + uint32_t fb_mask_blue; + uint32_t fb_mask_reserved; +}; + +#endif /* !_MACHINE_METADATA_H_ */ diff --git a/sys/arm/include/minidump.h b/sys/arm/include/minidump.h new file mode 100644 index 000000000000..d11e997d94dc --- /dev/null +++ b/sys/arm/include/minidump.h @@ -0,0 +1,62 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2006 Peter Wemm + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * From: FreeBSD: src/sys/i386/include/minidump.h,v 1.1 2006/04/21 04:28:43 + * $FreeBSD$ + */ + +#ifndef _MACHINE_MINIDUMP_H_ +#define _MACHINE_MINIDUMP_H_ + +#define MINIDUMP_MAGIC "minidump FreeBSD/arm" +#define MINIDUMP_VERSION 2 + +/* + * The first page of vmcore is dedicated to the following header. + * As the rest of the page is zeroed, any header extension can be + * done without version bumping. It should be taken into account + * only that new entries will be zero in old vmcores. + */ + +struct minidumphdr { + char magic[24]; + uint32_t version; + uint32_t msgbufsize; + uint32_t bitmapsize; + uint32_t ptesize; + uint32_t kernbase; + uint32_t arch; + uint32_t mmuformat; + uint32_t dumpavailsize; +}; + +#define MINIDUMP_MMU_FORMAT_UNKNOWN 0 +#define MINIDUMP_MMU_FORMAT_V4 1 +#define MINIDUMP_MMU_FORMAT_V6 2 +#define MINIDUMP_MMU_FORMAT_V6_LPAE 3 + +#endif /* _MACHINE_MINIDUMP_H_ */ diff --git a/sys/arm/include/ofw_machdep.h b/sys/arm/include/ofw_machdep.h new file mode 100644 index 000000000000..76ab31c963cf --- /dev/null +++ b/sys/arm/include/ofw_machdep.h @@ -0,0 +1,49 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2009 The FreeBSD Foundation + * All rights reserved. + * + * This software was developed by Semihalf under sponsorship from + * the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_OFW_MACHDEP_H_ +#define _MACHINE_OFW_MACHDEP_H_ + +#include <sys/types.h> +#include <sys/bus.h> +#include <sys/rman.h> +#include <vm/vm.h> + +typedef uint32_t cell_t; + +struct mem_region { + uint64_t mr_start; + uint64_t mr_size; +}; + +#endif /* _MACHINE_OFW_MACHDEP_H_ */ diff --git a/sys/arm/include/param.h b/sys/arm/include/param.h new file mode 100644 index 000000000000..807b492324fa --- /dev/null +++ b/sys/arm/include/param.h @@ -0,0 +1,146 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (c) 2001 David E. O'Brien + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * William Jolitz. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: @(#)param.h 5.8 (Berkeley) 6/28/91 + * $FreeBSD$ + */ + +#ifndef _ARM_INCLUDE_PARAM_H_ +#define _ARM_INCLUDE_PARAM_H_ + +/* + * Machine dependent constants for StrongARM + */ + +#include <machine/_align.h> + +#define STACKALIGNBYTES (8 - 1) +#define STACKALIGN(p) ((u_int)(p) & ~STACKALIGNBYTES) + +#define __PCI_REROUTE_INTERRUPT + +#ifndef MACHINE +#define MACHINE "arm" +#endif +#ifndef MACHINE_ARCH +#if __ARM_ARCH >= 7 +#define MACHINE_ARCH "armv7" +#else +#define MACHINE_ARCH "armv6" +#endif +#endif + +#ifdef SMP +#ifndef MAXCPU +#define MAXCPU 4 +#endif +#else +#define MAXCPU 1 +#endif + +#ifndef MAXMEMDOM +#define MAXMEMDOM 1 +#endif + +#define ALIGNBYTES _ALIGNBYTES +#define ALIGN(p) _ALIGN(p) +/* + * ALIGNED_POINTER is a boolean macro that checks whether an address + * is valid to fetch data elements of type t from on this architecture. + * This does not reflect the optimal alignment, just the possibility + * (within reasonable limits). + * + * armv4 and v5 require alignment to the type's size. armv6 requires 8-byte + * alignment for the ldrd/strd instructions, but otherwise follows armv7 rules. + * armv7 requires that an 8-byte type be aligned to at least a 4-byte boundary; + * access to smaller types can be unaligned, except that the compiler may + * optimize access to adjacent uint32_t values into a single load/store-multiple + * instruction which requires 4-byte alignment, so we must provide the most- + * pessimistic answer possible even on armv7. + */ +#define ALIGNED_POINTER(p, t) ((((unsigned)(p)) & (sizeof(t)-1)) == 0) + +/* + * CACHE_LINE_SIZE is the compile-time maximum cache line size for an + * architecture. It should be used with appropriate caution. + */ +#define CACHE_LINE_SHIFT 6 +#define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT) + +#define PAGE_SHIFT 12 +#define PAGE_SIZE (1 << PAGE_SHIFT) /* Page size */ +#define PAGE_MASK (PAGE_SIZE - 1) + +#define PDR_SHIFT 20 /* log2(NBPDR) */ +#define NBPDR (1 << PDR_SHIFT) +#define PDRMASK (NBPDR - 1) +#define NPDEPG (1 << (32 - PDR_SHIFT)) + +#define MAXPAGESIZES 2 /* maximum number of supported page sizes */ + +#ifndef KSTACK_PAGES +#define KSTACK_PAGES 2 +#endif /* !KSTACK_PAGES */ + +#ifndef FPCONTEXTSIZE +#define FPCONTEXTSIZE (0x100) +#endif + +#ifndef KSTACK_GUARD_PAGES +#define KSTACK_GUARD_PAGES 1 +#endif /* !KSTACK_GUARD_PAGES */ + +#define USPACE_SVC_STACK_TOP (kstack_pages * PAGE_SIZE) + +/* + * Mach derived conversion macros + */ +#define trunc_page(x) ((x) & ~PAGE_MASK) +#define round_page(x) (((x) + PAGE_MASK) & ~PAGE_MASK) +#define trunc_1mpage(x) ((unsigned)(x) & ~PDRMASK) +#define round_1mpage(x) ((((unsigned)(x)) + PDRMASK) & ~PDRMASK) + +#define atop(x) ((unsigned)(x) >> PAGE_SHIFT) +#define ptoa(x) ((unsigned)(x) << PAGE_SHIFT) + +#define arm32_btop(x) ((unsigned)(x) >> PAGE_SHIFT) +#define arm32_ptob(x) ((unsigned)(x) << PAGE_SHIFT) + +#define pgtok(x) ((x) * (PAGE_SIZE / 1024)) + +#endif /* !_ARM_INCLUDE_PARAM_H_ */ diff --git a/sys/arm/include/pcb.h b/sys/arm/include/pcb.h new file mode 100644 index 000000000000..078a13c13796 --- /dev/null +++ b/sys/arm/include/pcb.h @@ -0,0 +1,89 @@ +/* $NetBSD: pcb.h,v 1.10 2003/10/13 21:46:39 scw Exp $ */ + +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (c) 2001 Matt Thomas <matt@3am-software.com>. + * Copyright (c) 1994 Mark Brinicombe. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the RiscBSD team. + * 4. The name "RiscBSD" nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY RISCBSD ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL RISCBSD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_PCB_H_ +#define _MACHINE_PCB_H_ + +#include <machine/frame.h> +#include <machine/vfp.h> + +/* + * WARNING! + * Keep pcb_regs first for faster access in switch.S + */ +struct pcb { + struct switchframe pcb_regs; /* CPU state */ + u_int pcb_flags; +#define PCB_OWNFPU 0x00000001 +#define PCB_NOALIGNFLT 0x00000002 + caddr_t pcb_onfault; /* On fault handler */ + vm_offset_t pcb_pagedir; /* TTB0 value */ + /* + * XXX: + * Variables pcb_pl1vec, pcb_l1vec, pcb_dacr are used solely + * by old PMAP. Keep them here for PCB binary compatibility + * between old and new PMAP. + */ + uint32_t *pcb_pl1vec; /* PTR to vector_base L1 entry*/ + uint32_t pcb_l1vec; /* Value to stuff on ctx sw */ + u_int pcb_dacr; /* Domain Access Control Reg */ + + struct vfp_state pcb_vfpstate; /* VP/NEON state */ + u_int pcb_vfpcpu; /* VP/NEON last cpu */ +} __aligned(8); /* + * We need the PCB to be aligned on 8 bytes, as we may + * access it using ldrd/strd, and ARM ABI require it + * to by aligned on 8 bytes. + */ + +/* + * No additional data for core dumps. + */ +struct md_coredump { + int md_empty; +}; + +void makectx(struct trapframe *tf, struct pcb *pcb); + +#ifdef _KERNEL + +void savectx(struct pcb *) __returns_twice; +#endif /* _KERNEL */ + +#endif /* !_MACHINE_PCB_H_ */ diff --git a/sys/arm/include/pcpu.h b/sys/arm/include/pcpu.h new file mode 100644 index 000000000000..4d609b10bf73 --- /dev/null +++ b/sys/arm/include/pcpu.h @@ -0,0 +1,146 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 1999 Luoqi Chen <luoqi@freebsd.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: FreeBSD: src/sys/i386/include/globaldata.h,v 1.27 2001/04/27 + * $FreeBSD$ + */ + +#ifndef _MACHINE_PCPU_H_ +#define _MACHINE_PCPU_H_ + +#ifdef _KERNEL + +#include <sys/_lock.h> +#include <sys/_mutex.h> + +#define ALT_STACK_SIZE 128 + +struct vmspace; + +#endif /* _KERNEL */ + +/* Branch predictor hardening method */ +#define PCPU_BP_HARDEN_KIND_NONE 0 +#define PCPU_BP_HARDEN_KIND_BPIALL 1 +#define PCPU_BP_HARDEN_KIND_ICIALLU 2 + +#define PCPU_MD_FIELDS \ + unsigned int pc_vfpsid; \ + unsigned int pc_vfpmvfr0; \ + unsigned int pc_vfpmvfr1; \ + struct pmap *pc_curpmap; \ + struct mtx pc_cmap_lock; \ + void *pc_cmap1_pte2p; \ + void *pc_cmap2_pte2p; \ + caddr_t pc_cmap1_addr; \ + caddr_t pc_cmap2_addr; \ + vm_offset_t pc_qmap_addr; \ + void *pc_qmap_pte2p; \ + unsigned int pc_dbreg[32]; \ + int pc_dbreg_cmd; \ + int pc_bp_harden_kind; \ + uint32_t pc_original_actlr; \ + uint64_t pc_clock; \ + uint32_t pc_mpidr; \ + char __pad[135] + +#ifdef _KERNEL + +#define PC_DBREG_CMD_NONE 0 +#define PC_DBREG_CMD_LOAD 1 + +struct pcb; +struct pcpu; + +extern struct pcpu *pcpup; + +#define CPU_MASK (0xf) + +#ifndef SMP +#define get_pcpu() (pcpup) +#else +#define get_pcpu() __extension__ ({ \ + int id; \ + __asm __volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (id)); \ + (pcpup + (id & CPU_MASK)); \ + }) +#endif + +static inline struct thread * +get_curthread(void) +{ + void *ret; + + __asm __volatile("mrc p15, 0, %0, c13, c0, 4" : "=r" (ret)); + return (ret); +} + +static inline void +set_curthread(struct thread *td) +{ + + __asm __volatile("mcr p15, 0, %0, c13, c0, 4" : : "r" (td)); +} + +static inline void * +get_tls(void) +{ + void *tls; + + /* TPIDRURW contains the authoritative value. */ + __asm __volatile("mrc p15, 0, %0, c13, c0, 2" : "=r" (tls)); + return (tls); +} + +static inline void +set_tls(void *tls) +{ + + /* + * Update both TPIDRURW and TPIDRURO. TPIDRURW needs to be written + * first to ensure that a context switch between the two writes will + * still give the desired result of updating both. + */ + __asm __volatile( + "mcr p15, 0, %0, c13, c0, 2\n" + "mcr p15, 0, %0, c13, c0, 3\n" + : : "r" (tls)); +} + +#define curthread get_curthread() + + +#define PCPU_GET(member) (get_pcpu()->pc_ ## member) +#define PCPU_ADD(member, value) (get_pcpu()->pc_ ## member += (value)) +#define PCPU_INC(member) PCPU_ADD(member, 1) +#define PCPU_PTR(member) (&get_pcpu()->pc_ ## member) +#define PCPU_SET(member,value) (get_pcpu()->pc_ ## member = (value)) + +void pcpu0_init(void); +#endif /* _KERNEL */ + +#endif /* !_MACHINE_PCPU_H_ */ diff --git a/sys/arm/include/pcpu_aux.h b/sys/arm/include/pcpu_aux.h new file mode 100644 index 000000000000..3d4c70c491d6 --- /dev/null +++ b/sys/arm/include/pcpu_aux.h @@ -0,0 +1,52 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2019 The FreeBSD Foundation + * + * This software was developed by Konstantin Belousov <kib@FreeBSD.org> + * under sponsorship from the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_PCPU_AUX_H_ +#define _MACHINE_PCPU_AUX_H_ + +#ifndef _KERNEL +#error "Not for userspace" +#endif + +#ifndef _SYS_PCPU_H_ +#error "Do not include machine/pcpu_aux.h directly" +#endif + +/* + * To minimize memory waste in per-cpu UMA zones, the page size should + * be a multiple of the size of struct pcpu. + */ +_Static_assert(PAGE_SIZE % sizeof(struct pcpu) == 0, "fix pcpu size"); + +extern struct pcpu __pcpu[]; + +#endif /* _MACHINE_PCPU_AUX_H_ */ diff --git a/sys/arm/include/pl310.h b/sys/arm/include/pl310.h new file mode 100644 index 000000000000..39e8434097a7 --- /dev/null +++ b/sys/arm/include/pl310.h @@ -0,0 +1,191 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2012 Olivier Houchard. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * $FreeBSD$ + */ + +#ifndef PL310_H_ +#define PL310_H_ + +/** + * PL310 - L2 Cache Controller register offsets. + * + */ +#define PL310_CACHE_ID 0x000 +#define CACHE_ID_RELEASE_SHIFT 0 +#define CACHE_ID_RELEASE_MASK 0x3f +#define CACHE_ID_RELEASE_r0p0 0x00 +#define CACHE_ID_RELEASE_r1p0 0x02 +#define CACHE_ID_RELEASE_r2p0 0x04 +#define CACHE_ID_RELEASE_r3p0 0x05 +#define CACHE_ID_RELEASE_r3p1 0x06 +#define CACHE_ID_RELEASE_r3p2 0x08 +#define CACHE_ID_RELEASE_r3p3 0x09 +#define CACHE_ID_PARTNUM_SHIFT 6 +#define CACHE_ID_PARTNUM_MASK 0xf +#define CACHE_ID_PARTNUM_VALUE 0x3 +#define PL310_CACHE_TYPE 0x004 +#define PL310_CTRL 0x100 +#define CTRL_ENABLED 0x01 +#define CTRL_DISABLED 0x00 +#define PL310_AUX_CTRL 0x104 +#define AUX_CTRL_MASK 0xc0000fff +#define AUX_CTRL_ASSOCIATIVITY_SHIFT 16 +#define AUX_CTRL_WAY_SIZE_SHIFT 17 +#define AUX_CTRL_WAY_SIZE_MASK (0x7 << 17) +#define AUX_CTRL_SHARE_OVERRIDE (1 << 22) +#define AUX_CTRL_NS_LOCKDOWN (1 << 26) +#define AUX_CTRL_NS_INT_CTRL (1 << 27) +#define AUX_CTRL_DATA_PREFETCH (1 << 28) +#define AUX_CTRL_INSTR_PREFETCH (1 << 29) +#define AUX_CTRL_EARLY_BRESP (1 << 30) +#define PL310_TAG_RAM_CTRL 0x108 +#define PL310_DATA_RAM_CTRL 0x10C +#define RAM_CTRL_WRITE_SHIFT 8 +#define RAM_CTRL_WRITE_MASK (0x7 << 8) +#define RAM_CTRL_READ_SHIFT 4 +#define RAM_CTRL_READ_MASK (0x7 << 4) +#define RAM_CTRL_SETUP_SHIFT 0 +#define RAM_CTRL_SETUP_MASK (0x7 << 0) +#define PL310_EVENT_COUNTER_CTRL 0x200 +#define EVENT_COUNTER_CTRL_ENABLED (1 << 0) +#define EVENT_COUNTER_CTRL_C0_RESET (1 << 1) +#define EVENT_COUNTER_CTRL_C1_RESET (1 << 2) +#define PL310_EVENT_COUNTER1_CONF 0x204 +#define PL310_EVENT_COUNTER0_CONF 0x208 +#define EVENT_COUNTER_CONF_NOINTR 0 +#define EVENT_COUNTER_CONF_INCR 1 +#define EVENT_COUNTER_CONF_OVFW 2 +#define EVENT_COUNTER_CONF_NOEV (0 << 2) +#define EVENT_COUNTER_CONF_CO (1 << 2) +#define EVENT_COUNTER_CONF_DRHIT (2 << 2) +#define EVENT_COUNTER_CONF_DRREQ (3 << 2) +#define EVENT_COUNTER_CONF_DWHIT (4 << 2) +#define EVENT_COUNTER_CONF_DWREQ (5 << 2) +#define EVENT_COUNTER_CONF_DWTREQ (6 << 2) +#define EVENT_COUNTER_CONF_DIRHIT (7 << 2) +#define EVENT_COUNTER_CONF_DIRREQ (8 << 2) +#define EVENT_COUNTER_CONF_WA (9 << 2) +#define PL310_EVENT_COUNTER1_VAL 0x20C +#define PL310_EVENT_COUNTER0_VAL 0x210 +#define PL310_INTR_MASK 0x214 +#define PL310_MASKED_INTR_STAT 0x218 +#define PL310_RAW_INTR_STAT 0x21C +#define PL310_INTR_CLEAR 0x220 +#define INTR_MASK_ALL ((1 << 9) - 1) +#define INTR_MASK_ECNTR (1 << 0) +#define INTR_MASK_PARRT (1 << 1) +#define INTR_MASK_PARRD (1 << 2) +#define INTR_MASK_ERRWT (1 << 3) +#define INTR_MASK_ERRWD (1 << 4) +#define INTR_MASK_ERRRT (1 << 5) +#define INTR_MASK_ERRRD (1 << 6) +#define INTR_MASK_SLVERR (1 << 7) +#define INTR_MASK_DECERR (1 << 8) +#define PL310_CACHE_SYNC 0x730 +#define PL310_INV_LINE_PA 0x770 +#define PL310_INV_WAY 0x77C +#define PL310_CLEAN_LINE_PA 0x7B0 +#define PL310_CLEAN_LINE_IDX 0x7B8 +#define PL310_CLEAN_WAY 0x7BC +#define PL310_CLEAN_INV_LINE_PA 0x7F0 +#define PL310_CLEAN_INV_LINE_IDX 0x7F8 +#define PL310_CLEAN_INV_WAY 0x7FC +#define PL310_LOCKDOWN_D_WAY(x) (0x900 + ((x) * 8)) +#define PL310_LOCKDOWN_I_WAY(x) (0x904 + ((x) * 8)) +#define PL310_LOCKDOWN_LINE_ENABLE 0x950 +#define PL310_UNLOCK_ALL_LINES_WAY 0x954 +#define PL310_ADDR_FILTER_STAR 0xC00 +#define PL310_ADDR_FILTER_END 0xC04 +#define PL310_DEBUG_CTRL 0xF40 +#define DEBUG_CTRL_DISABLE_LINEFILL (1 << 0) +#define DEBUG_CTRL_DISABLE_WRITEBACK (1 << 1) +#define DEBUG_CTRL_SPNIDEN (1 << 2) +#define PL310_PREFETCH_CTRL 0xF60 +#define PREFETCH_CTRL_OFFSET_MASK (0x1f) +#define PREFETCH_CTRL_NOTSAMEID (1 << 21) +#define PREFETCH_CTRL_INCR_DL (1 << 23) +#define PREFETCH_CTRL_PREFETCH_DROP (1 << 24) +#define PREFETCH_CTRL_DL_ON_WRAP (1 << 27) +#define PREFETCH_CTRL_DATA_PREFETCH (1 << 28) +#define PREFETCH_CTRL_INSTR_PREFETCH (1 << 29) +#define PREFETCH_CTRL_DL (1 << 30) +#define PL310_POWER_CTRL 0xF80 +#define POWER_CTRL_ENABLE_GATING (1 << 1) +#define POWER_CTRL_ENABLE_STANDBY (1 << 0) + +struct intr_config_hook; + +struct pl310_softc { + device_t sc_dev; + struct resource *sc_mem_res; + struct resource *sc_irq_res; + void* sc_irq_h; + int sc_enabled; + struct mtx sc_mtx; + u_int sc_rtl_revision; + struct intr_config_hook *sc_ich; + boolean_t sc_io_coherent; +}; + +/** + * pl310_read4 - read a 32-bit value from the PL310 registers + * pl310_write4 - write a 32-bit value from the PL310 registers + * @off: byte offset within the register set to read from + * @val: the value to write into the register + * + * + * LOCKING: + * None + * + * RETURNS: + * nothing in case of write function, if read function returns the value read. + */ +static __inline uint32_t +pl310_read4(struct pl310_softc *sc, bus_size_t off) +{ + + return bus_read_4(sc->sc_mem_res, off); +} + +static __inline void +pl310_write4(struct pl310_softc *sc, bus_size_t off, uint32_t val) +{ + + bus_write_4(sc->sc_mem_res, off, val); +} + +void pl310_set_ram_latency(struct pl310_softc *sc, uint32_t which_reg, + uint32_t read, uint32_t write, uint32_t setup); + +#ifndef PLATFORM +void platform_pl310_init(struct pl310_softc *); +void platform_pl310_write_ctrl(struct pl310_softc *, uint32_t); +void platform_pl310_write_debug(struct pl310_softc *, uint32_t); +#endif + +#endif /* PL310_H_ */ diff --git a/sys/arm/include/platform.h b/sys/arm/include/platform.h new file mode 100644 index 000000000000..5632003bcc27 --- /dev/null +++ b/sys/arm/include/platform.h @@ -0,0 +1,66 @@ +/*- + * Copyright (c) 2014 Andrew Turner + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_PLATFORM_H_ +#define _MACHINE_PLATFORM_H_ + +/* + * Initialization functions called by the common initarm() function in + * arm/machdep.c (but not necessarily from the custom initarm() functions of + * older code). + * + * - platform_probe_and_attach() is called very early, after parsing the boot + * params and after physical memory has been located and sized. + * + * - platform_devmap_init() is called as one of the last steps of early virtual + * memory initialization, shortly before the new page tables are installed. + * + * - platform_lastaddr() is called after platform_devmap_init(), and must return + * the address of the first byte of unusable KVA space. This allows a + * platform to carve out of the top of the KVA space whatever reserves it + * needs for things like static device mapping, and this is called to get the + * value before calling pmap_bootstrap() which uses the value to size the + * available KVA. + * + * - platform_gpio_init() is called after the static device mappings are + * established and just before cninit(). The intention is that the routine + * can do any hardware setup (such as gpio or pinmux) necessary to make the + * console functional. + * + * - platform_late_init() is called just after cninit(). This is the first of + * the init routines that can use printf() and expect the output to appear on + * a standard console. + * + */ +void platform_probe_and_attach(void); +int platform_devmap_init(void); +vm_offset_t platform_lastaddr(void); +void platform_gpio_init(void); +void platform_late_init(void); + +#endif /* _MACHINE_PLATFORM_H_ */ diff --git a/sys/arm/include/platformvar.h b/sys/arm/include/platformvar.h new file mode 100644 index 000000000000..4fbe658d69ae --- /dev/null +++ b/sys/arm/include/platformvar.h @@ -0,0 +1,124 @@ +/*- + * Copyright (c) 2005 Peter Grehan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_PLATFORMVAR_H_ +#define _MACHINE_PLATFORMVAR_H_ + +/* + * An ARM platform implementation is declared with a kernel object and + * an associated method table, similar to a device driver. + * + * e.g. + * + * static platform_method_t bcm2835_methods[] = { + * PLATFORMMETHOD(platform_probe, bcm2835_probe), + * ... + * PLATFORMMETHOD_END + * }; + * + * static platform_def_t bcm3835_platform = { + * "bcm2835", + * bcm2835_methods, + * sizeof(bcm2835_platform_softc), // or 0 if no softc + * }; + * + * PLATFORM_DEF(bcm2835_platform); + */ + +#include <sys/kobj.h> +#include <sys/linker_set.h> + +struct platform_class { + KOBJ_CLASS_FIELDS; + + /* How many times to loop to delay approximately 1us */ + int delay_count; +}; + +struct platform_kobj { + /* + * A platform instance is a kernel object + */ + KOBJ_FIELDS; + + /* Platform class, for access to class specific data */ + struct platform_class *cls; +}; + +typedef struct platform_kobj *platform_t; +typedef struct platform_class platform_def_t; +#define platform_method_t kobj_method_t + +#define PLATFORMMETHOD KOBJMETHOD +#define PLATFORMMETHOD_END KOBJMETHOD_END + +#define PLATFORM_DEF(name) DATA_SET(platform_set, name) + +#ifdef FDT +struct fdt_platform_class { + KOBJ_CLASS_FIELDS; + + const char *fdt_compatible; +}; + +typedef struct fdt_platform_class fdt_platform_def_t; + +extern platform_method_t fdt_platform_methods[]; + +#define FDT_PLATFORM_DEF2(NAME, VAR_NAME, NAME_STR, _size, _compatible, \ + _delay) \ +CTASSERT(_delay > 0); \ +static fdt_platform_def_t VAR_NAME ## _fdt_platform = { \ + .name = NAME_STR, \ + .methods = fdt_platform_methods, \ + .fdt_compatible = _compatible, \ +}; \ +static kobj_class_t VAR_NAME ## _baseclasses[] = \ + { (kobj_class_t)&VAR_NAME ## _fdt_platform, NULL }; \ +static platform_def_t VAR_NAME ## _platform = { \ + .name = NAME_STR, \ + .methods = NAME ## _methods, \ + .size = _size, \ + .baseclasses = VAR_NAME ## _baseclasses, \ + .delay_count = _delay, \ +}; \ +DATA_SET(platform_set, VAR_NAME ## _platform) + +#define FDT_PLATFORM_DEF(NAME, NAME_STR, size, compatible, delay) \ + FDT_PLATFORM_DEF2(NAME, NAME, NAME_STR, size, compatible, delay) + +#endif + +/* + * Helper to get the platform object + */ +platform_t platform_obj(void); + +bool arm_tmr_timed_wait(platform_t, int); + +#endif /* _MACHINE_PLATFORMVAR_H_ */ diff --git a/sys/arm/include/pmap-v6.h b/sys/arm/include/pmap-v6.h new file mode 100644 index 000000000000..aa596aa699c6 --- /dev/null +++ b/sys/arm/include/pmap-v6.h @@ -0,0 +1,194 @@ +/*- + * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com> + * Copyright 2014 Michal Meloun <meloun@miracle.cz> + * Copyright (c) 1991 Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * the Systems Programming Group of the University of Utah Computer + * Science Department and William Jolitz of UUNET Technologies Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * The ARM version of this file was more or less based on the i386 version, + * which has the following provenance... + * + * Derived from hp300 version by Mike Hibler, this version by William + * Jolitz uses a recursive map [a pde points to the page directory] to + * map the page tables using the pagetables themselves. This is done to + * reduce the impact on kernel virtual memory for lots of sparse address + * space, and to reduce the cost of memory to each process. + * + * from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90 + * from: @(#)pmap.h 7.4 (Berkeley) 5/12/91 + * from: FreeBSD: src/sys/i386/include/pmap.h,v 1.70 2000/11/30 + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_PMAP_V6_H_ +#define _MACHINE_PMAP_V6_H_ + +#include <sys/queue.h> +#include <sys/_cpuset.h> +#include <sys/_lock.h> +#include <sys/_mutex.h> + +typedef uint32_t pt1_entry_t; /* L1 table entry */ +typedef uint32_t pt2_entry_t; /* L2 table entry */ +typedef uint32_t ttb_entry_t; /* TTB entry */ + +#ifdef _KERNEL + +#if 0 +#define PMAP_PTE_NOCACHE // Use uncached page tables +#endif + +/* + * (1) During pmap bootstrap, physical pages for L2 page tables are + * allocated in advance which are used for KVA continuous mapping + * starting from KERNBASE. This makes things more simple. + * (2) During vm subsystem initialization, only vm subsystem itself can + * allocate physical memory safely. As pmap_map() is called during + * this initialization, we must be prepared for that and have some + * preallocated physical pages for L2 page tables. + * + * Note that some more pages for L2 page tables are preallocated too + * for mappings laying above VM_MAX_KERNEL_ADDRESS. + */ +#ifndef NKPT2PG +/* + * The optimal way is to define this in board configuration as + * definition here must be safe enough. It means really big. + * + * 1 GB KVA <=> 256 kernel L2 page table pages + * + * From real platforms: + * 1 GB physical memory <=> 10 pages is enough + * 2 GB physical memory <=> 21 pages is enough + */ +#define NKPT2PG 32 +#endif +#endif /* _KERNEL */ + +/* + * Pmap stuff + */ +struct pv_entry; +struct pv_chunk; + +struct md_page { + TAILQ_HEAD(,pv_entry) pv_list; + uint16_t pt2_wirecount[4]; + vm_memattr_t pat_mode; +}; + +struct pmap { + struct mtx pm_mtx; + pt1_entry_t *pm_pt1; /* KVA of pt1 */ + pt2_entry_t *pm_pt2tab; /* KVA of pt2 pages table */ + TAILQ_HEAD(,pv_chunk) pm_pvchunk; /* list of mappings in pmap */ + cpuset_t pm_active; /* active on cpus */ + struct pmap_statistics pm_stats; /* pmap statictics */ + LIST_ENTRY(pmap) pm_list; /* List of all pmaps */ +}; + +typedef struct pmap *pmap_t; + +#ifdef _KERNEL +extern struct pmap kernel_pmap_store; +#define kernel_pmap (&kernel_pmap_store) + +#define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx) +#define PMAP_LOCK_ASSERT(pmap, type) \ + mtx_assert(&(pmap)->pm_mtx, (type)) +#define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx) +#define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \ + NULL, MTX_DEF | MTX_DUPOK) +#define PMAP_LOCKED(pmap) mtx_owned(&(pmap)->pm_mtx) +#define PMAP_MTX(pmap) (&(pmap)->pm_mtx) +#define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx) +#define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx) +#endif + +/* + * For each vm_page_t, there is a list of all currently valid virtual + * mappings of that page. An entry is a pv_entry_t, the list is pv_list. + */ +typedef struct pv_entry { + vm_offset_t pv_va; /* virtual address for mapping */ + TAILQ_ENTRY(pv_entry) pv_next; +} *pv_entry_t; + +/* + * pv_entries are allocated in chunks per-process. This avoids the + * need to track per-pmap assignments. + */ +#define _NPCM 11 +#define _NPCPV 336 +struct pv_chunk { + pmap_t pc_pmap; + TAILQ_ENTRY(pv_chunk) pc_list; + uint32_t pc_map[_NPCM]; /* bitmap; 1 = free */ + TAILQ_ENTRY(pv_chunk) pc_lru; + struct pv_entry pc_pventry[_NPCPV]; +}; + +#ifdef _KERNEL +extern ttb_entry_t pmap_kern_ttb; /* TTB for kernel pmap */ + +#define pmap_page_get_memattr(m) ((m)->md.pat_mode) + +/* + * Only the following functions or macros may be used before pmap_bootstrap() + * is called: pmap_kenter(), pmap_kextract(), pmap_kremove(), vtophys(), and + * vtopte2(). + */ +void pmap_bootstrap(vm_offset_t); +void pmap_kenter(vm_offset_t, vm_paddr_t); +void pmap_kremove(vm_offset_t); +boolean_t pmap_page_is_mapped(vm_page_t); +bool pmap_ps_enabled(pmap_t pmap); + +void pmap_tlb_flush(pmap_t, vm_offset_t); +void pmap_tlb_flush_range(pmap_t, vm_offset_t, vm_size_t); + +vm_paddr_t pmap_dump_kextract(vm_offset_t, pt2_entry_t *); + +int pmap_fault(pmap_t, vm_offset_t, uint32_t, int, bool); + +void pmap_set_tex(void); + +/* + * Pre-bootstrap epoch functions set. + */ +void pmap_bootstrap_prepare(vm_paddr_t); +vm_paddr_t pmap_preboot_get_pages(u_int); +void pmap_preboot_map_pages(vm_paddr_t, vm_offset_t, u_int); +vm_offset_t pmap_preboot_reserve_pages(u_int); +vm_offset_t pmap_preboot_get_vpages(u_int); +void pmap_preboot_map_attr(vm_paddr_t, vm_offset_t, vm_size_t, vm_prot_t, + vm_memattr_t); +void pmap_remap_vm_attr(vm_memattr_t old_attr, vm_memattr_t new_attr); + +#endif /* _KERNEL */ +#endif /* !_MACHINE_PMAP_V6_H_ */ diff --git a/sys/arm/include/pmap.h b/sys/arm/include/pmap.h new file mode 100644 index 000000000000..2f407a9c8760 --- /dev/null +++ b/sys/arm/include/pmap.h @@ -0,0 +1,77 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2016 Svatopluk Kraus + * Copyright (c) 2016 Michal Meloun + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_PMAP_H_ +#define _MACHINE_PMAP_H_ + +#include <machine/pmap-v6.h> + +#ifdef _KERNEL +#include <sys/systm.h> + +extern char *_tmppt; /* poor name! */ + +extern vm_offset_t virtual_avail; +extern vm_offset_t virtual_end; + +void *pmap_kenter_temporary(vm_paddr_t, int); +#define pmap_page_is_write_mapped(m) (((m)->a.flags & PGA_WRITEABLE) != 0) +void pmap_page_set_memattr(vm_page_t, vm_memattr_t); + +void *pmap_mapdev(vm_paddr_t, vm_size_t); +void pmap_unmapdev(vm_offset_t, vm_size_t); + +static inline void * +pmap_mapdev_attr(vm_paddr_t addr, vm_size_t size, int attr) +{ + panic("%s is not implemented yet!\n", __func__); +} + +struct pcb; +void pmap_set_pcb_pagedir(pmap_t, struct pcb *); + +void pmap_kenter_device(vm_offset_t, vm_size_t, vm_paddr_t); +void pmap_kremove_device(vm_offset_t, vm_size_t); + +vm_paddr_t pmap_kextract(vm_offset_t); +#define vtophys(va) pmap_kextract((vm_offset_t)(va)) + +static inline int +pmap_vmspace_copy(pmap_t dst_pmap __unused, pmap_t src_pmap __unused) +{ + + return (0); +} + +#define PMAP_ENTER_QUICK_LOCKED 0x10000000 + +#endif /* _KERNEL */ +#endif /* !_MACHINE_PMAP_H_ */ diff --git a/sys/arm/include/pmap_var.h b/sys/arm/include/pmap_var.h new file mode 100644 index 000000000000..34c101df5c4d --- /dev/null +++ b/sys/arm/include/pmap_var.h @@ -0,0 +1,494 @@ +/*- + * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com> + * Copyright 2014 Michal Meloun <meloun@miracle.cz> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_PMAP_VAR_H_ +#define _MACHINE_PMAP_VAR_H_ + +#include <machine/cpu-v6.h> +#include <machine/pte-v6.h> +/* + * Various PMAP defines, exports, and inline functions + * definitions also usable in other MD code. + */ + +/* A number of pages in L1 page table. */ +#define NPG_IN_PT1 (NB_IN_PT1 / PAGE_SIZE) + +/* A number of L2 page tables in a page. */ +#define NPT2_IN_PG (PAGE_SIZE / NB_IN_PT2) + +/* A number of L2 page table entries in a page. */ +#define NPTE2_IN_PG (NPT2_IN_PG * NPTE2_IN_PT2) + +#ifdef _KERNEL + +/* + * A L2 page tables page contains NPT2_IN_PG L2 page tables. Masking of + * pte1_idx by PT2PG_MASK gives us an index to associated L2 page table + * in a page. The PT2PG_SHIFT definition depends on NPT2_IN_PG strictly. + * I.e., (1 << PT2PG_SHIFT) == NPT2_IN_PG must be fulfilled. + */ +#define PT2PG_SHIFT 2 +#define PT2PG_MASK ((1 << PT2PG_SHIFT) - 1) + +/* + * A PT2TAB holds all allocated L2 page table pages in a pmap. + * Right shifting of virtual address by PT2TAB_SHIFT gives us an index + * to L2 page table page in PT2TAB which holds the address mapping. + */ +#define PT2TAB_ENTRIES (NPTE1_IN_PT1 / NPT2_IN_PG) +#define PT2TAB_SHIFT (PTE1_SHIFT + PT2PG_SHIFT) + +/* + * All allocated L2 page table pages in a pmap are mapped into PT2MAP space. + * An virtual address right shifting by PT2MAP_SHIFT gives us an index to PTE2 + * which maps the address. + */ +#define PT2MAP_SIZE (NPTE1_IN_PT1 * NB_IN_PT2) +#define PT2MAP_SHIFT PTE2_SHIFT + +extern pt1_entry_t *kern_pt1; +extern pt2_entry_t *kern_pt2tab; +extern pt2_entry_t *PT2MAP; + +/* + * Virtual interface for L1 page table management. + */ + +static __inline u_int +pte1_index(vm_offset_t va) +{ + + return (va >> PTE1_SHIFT); +} + +static __inline pt1_entry_t * +pte1_ptr(pt1_entry_t *pt1, vm_offset_t va) +{ + + return (pt1 + pte1_index(va)); +} + +static __inline vm_offset_t +pte1_trunc(vm_offset_t va) +{ + + return (va & PTE1_FRAME); +} + +static __inline vm_offset_t +pte1_roundup(vm_offset_t va) +{ + + return ((va + PTE1_OFFSET) & PTE1_FRAME); +} + +/* + * Virtual interface for L1 page table entries management. + * + * XXX: Some of the following functions now with a synchronization barrier + * are called in a loop, so it could be useful to have two versions of them. + * One with the barrier and one without the barrier. In this case, pure + * barrier pte1_sync() should be implemented as well. + */ +static __inline void +pte1_sync(pt1_entry_t *pte1p) +{ + + dsb(); +#ifndef PMAP_PTE_NOCACHE + if (!cpuinfo.coherent_walk) + dcache_wb_pou((vm_offset_t)pte1p, sizeof(*pte1p)); +#endif +} + +static __inline void +pte1_sync_range(pt1_entry_t *pte1p, vm_size_t size) +{ + + dsb(); +#ifndef PMAP_PTE_NOCACHE + if (!cpuinfo.coherent_walk) + dcache_wb_pou((vm_offset_t)pte1p, size); +#endif +} + +static __inline void +pte1_store(pt1_entry_t *pte1p, pt1_entry_t pte1) +{ + + dmb(); + *pte1p = pte1; + pte1_sync(pte1p); +} + +static __inline void +pte1_clear(pt1_entry_t *pte1p) +{ + + pte1_store(pte1p, 0); +} + +static __inline void +pte1_clear_bit(pt1_entry_t *pte1p, uint32_t bit) +{ + + *pte1p &= ~bit; + pte1_sync(pte1p); +} + +static __inline boolean_t +pte1_is_link(pt1_entry_t pte1) +{ + + return ((pte1 & L1_TYPE_MASK) == L1_TYPE_C); +} + +static __inline int +pte1_is_section(pt1_entry_t pte1) +{ + + return ((pte1 & L1_TYPE_MASK) == L1_TYPE_S); +} + +static __inline boolean_t +pte1_is_dirty(pt1_entry_t pte1) +{ + + return ((pte1 & (PTE1_NM | PTE1_RO)) == 0); +} + +static __inline boolean_t +pte1_is_global(pt1_entry_t pte1) +{ + + return ((pte1 & PTE1_NG) == 0); +} + +static __inline boolean_t +pte1_is_valid(pt1_entry_t pte1) +{ + int l1_type; + + l1_type = pte1 & L1_TYPE_MASK; + return ((l1_type == L1_TYPE_C) || (l1_type == L1_TYPE_S)); +} + +static __inline boolean_t +pte1_is_wired(pt1_entry_t pte1) +{ + + return (pte1 & PTE1_W); +} + +static __inline pt1_entry_t +pte1_load(pt1_entry_t *pte1p) +{ + pt1_entry_t pte1; + + pte1 = *pte1p; + return (pte1); +} + +static __inline pt1_entry_t +pte1_load_clear(pt1_entry_t *pte1p) +{ + pt1_entry_t opte1; + + opte1 = *pte1p; + *pte1p = 0; + pte1_sync(pte1p); + return (opte1); +} + +static __inline void +pte1_set_bit(pt1_entry_t *pte1p, uint32_t bit) +{ + + *pte1p |= bit; + pte1_sync(pte1p); +} + +static __inline vm_paddr_t +pte1_pa(pt1_entry_t pte1) +{ + + return ((vm_paddr_t)(pte1 & PTE1_FRAME)); +} + +static __inline vm_paddr_t +pte1_link_pa(pt1_entry_t pte1) +{ + + return ((vm_paddr_t)(pte1 & L1_C_ADDR_MASK)); +} + +/* + * Virtual interface for L2 page table entries management. + * + * XXX: Some of the following functions now with a synchronization barrier + * are called in a loop, so it could be useful to have two versions of them. + * One with the barrier and one without the barrier. + */ + +static __inline void +pte2_sync(pt2_entry_t *pte2p) +{ + + dsb(); +#ifndef PMAP_PTE_NOCACHE + if (!cpuinfo.coherent_walk) + dcache_wb_pou((vm_offset_t)pte2p, sizeof(*pte2p)); +#endif +} + +static __inline void +pte2_sync_range(pt2_entry_t *pte2p, vm_size_t size) +{ + + dsb(); +#ifndef PMAP_PTE_NOCACHE + if (!cpuinfo.coherent_walk) + dcache_wb_pou((vm_offset_t)pte2p, size); +#endif +} + +static __inline void +pte2_store(pt2_entry_t *pte2p, pt2_entry_t pte2) +{ + + dmb(); + *pte2p = pte2; + pte2_sync(pte2p); +} + +static __inline void +pte2_clear(pt2_entry_t *pte2p) +{ + + pte2_store(pte2p, 0); +} + +static __inline void +pte2_clear_bit(pt2_entry_t *pte2p, uint32_t bit) +{ + + *pte2p &= ~bit; + pte2_sync(pte2p); +} + +static __inline boolean_t +pte2_is_dirty(pt2_entry_t pte2) +{ + + return ((pte2 & (PTE2_NM | PTE2_RO)) == 0); +} + +static __inline boolean_t +pte2_is_global(pt2_entry_t pte2) +{ + + return ((pte2 & PTE2_NG) == 0); +} + +static __inline boolean_t +pte2_is_valid(pt2_entry_t pte2) +{ + + return (pte2 & PTE2_V); +} + +static __inline boolean_t +pte2_is_wired(pt2_entry_t pte2) +{ + + return (pte2 & PTE2_W); +} + +static __inline pt2_entry_t +pte2_load(pt2_entry_t *pte2p) +{ + pt2_entry_t pte2; + + pte2 = *pte2p; + return (pte2); +} + +static __inline pt2_entry_t +pte2_load_clear(pt2_entry_t *pte2p) +{ + pt2_entry_t opte2; + + opte2 = *pte2p; + *pte2p = 0; + pte2_sync(pte2p); + return (opte2); +} + +static __inline void +pte2_set_bit(pt2_entry_t *pte2p, uint32_t bit) +{ + + *pte2p |= bit; + pte2_sync(pte2p); +} + +static __inline void +pte2_set_wired(pt2_entry_t *pte2p, boolean_t wired) +{ + + /* + * Wired bit is transparent for page table walk, + * so pte2_sync() is not needed. + */ + if (wired) + *pte2p |= PTE2_W; + else + *pte2p &= ~PTE2_W; +} + +static __inline vm_paddr_t +pte2_pa(pt2_entry_t pte2) +{ + + return ((vm_paddr_t)(pte2 & PTE2_FRAME)); +} + +static __inline u_int +pte2_attr(pt2_entry_t pte2) +{ + + return ((u_int)(pte2 & PTE2_ATTR_MASK)); +} + +/* + * Virtual interface for L2 page tables mapping management. + */ + +static __inline u_int +pt2tab_index(vm_offset_t va) +{ + + return (va >> PT2TAB_SHIFT); +} + +static __inline pt2_entry_t * +pt2tab_entry(pt2_entry_t *pt2tab, vm_offset_t va) +{ + + return (pt2tab + pt2tab_index(va)); +} + +static __inline void +pt2tab_store(pt2_entry_t *pte2p, pt2_entry_t pte2) +{ + + pte2_store(pte2p,pte2); +} + +static __inline pt2_entry_t +pt2tab_load(pt2_entry_t *pte2p) +{ + + return (pte2_load(pte2p)); +} + +static __inline pt2_entry_t +pt2tab_load_clear(pt2_entry_t *pte2p) +{ + + return (pte2_load_clear(pte2p)); +} + +static __inline u_int +pt2map_index(vm_offset_t va) +{ + + return (va >> PT2MAP_SHIFT); +} + +static __inline pt2_entry_t * +pt2map_entry(vm_offset_t va) +{ + + return (PT2MAP + pt2map_index(va)); +} + +/* + * Virtual interface for pmap structure & kernel shortcuts. + */ + +static __inline pt1_entry_t * +pmap_pte1(pmap_t pmap, vm_offset_t va) +{ + + return (pte1_ptr(pmap->pm_pt1, va)); +} + +static __inline pt1_entry_t * +kern_pte1(vm_offset_t va) +{ + + return (pte1_ptr(kern_pt1, va)); +} + +static __inline pt2_entry_t * +pmap_pt2tab_entry(pmap_t pmap, vm_offset_t va) +{ + + return (pt2tab_entry(pmap->pm_pt2tab, va)); +} + +static __inline pt2_entry_t * +kern_pt2tab_entry(vm_offset_t va) +{ + + return (pt2tab_entry(kern_pt2tab, va)); +} + +static __inline vm_page_t +pmap_pt2_page(pmap_t pmap, vm_offset_t va) +{ + pt2_entry_t pte2; + + pte2 = pte2_load(pmap_pt2tab_entry(pmap, va)); + return (PHYS_TO_VM_PAGE(pte2 & PTE2_FRAME)); +} + +static __inline vm_page_t +kern_pt2_page(vm_offset_t va) +{ + pt2_entry_t pte2; + + pte2 = pte2_load(kern_pt2tab_entry(va)); + return (PHYS_TO_VM_PAGE(pte2 & PTE2_FRAME)); +} + +#endif /* _KERNEL */ +#endif /* !_MACHINE_PMAP_VAR_H_ */ diff --git a/sys/arm/include/pmc_mdep.h b/sys/arm/include/pmc_mdep.h new file mode 100644 index 000000000000..69cb0c84deca --- /dev/null +++ b/sys/arm/include/pmc_mdep.h @@ -0,0 +1,83 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2009 Rui Paulo <rpaulo@FreeBSD.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_PMC_MDEP_H_ +#define _MACHINE_PMC_MDEP_H_ + +#define PMC_MDEP_CLASS_INDEX_ARMV7 1 +/* + * On the ARM platform we support the following PMCs. + * + * ARMV7 ARM Cortex-A processors + */ +#include <dev/hwpmc/hwpmc_armv7.h> + +union pmc_md_op_pmcallocate { + uint64_t __pad[4]; +}; + +/* Logging */ +#define PMCLOG_READADDR PMCLOG_READ32 +#define PMCLOG_EMITADDR PMCLOG_EMIT32 + +#ifdef _KERNEL +union pmc_md_pmc { + struct pmc_md_armv7_pmc pm_armv7; +}; + +#define PMC_IN_KERNEL_STACK(S,START,END) \ + ((S) >= (START) && (S) < (END)) +#define PMC_IN_KERNEL(va) INKERNEL((va)) + +#define PMC_IN_USERSPACE(va) ((va) <= VM_MAXUSER_ADDRESS) + +#define PMC_TRAPFRAME_TO_PC(TF) ((TF)->tf_pc) +#define PMC_TRAPFRAME_TO_FP(TF) ((TF)->tf_r11) +#define PMC_TRAPFRAME_TO_SVC_SP(TF) ((TF)->tf_svc_sp) +#define PMC_TRAPFRAME_TO_USR_SP(TF) ((TF)->tf_usr_sp) +#define PMC_TRAPFRAME_TO_SVC_LR(TF) ((TF)->tf_svc_lr) +#define PMC_TRAPFRAME_TO_USR_LR(TF) ((TF)->tf_usr_lr) + +/* Build a fake kernel trapframe from current instruction pointer. */ +#define PMC_FAKE_TRAPFRAME(TF) \ + do { \ + (TF)->tf_spsr = PSR_SVC32_MODE; \ + __asm __volatile("mov %0, pc" : "=r" ((TF)->tf_pc)); \ + __asm __volatile("mov %0, r11" : "=r" ((TF)->tf_r11)); \ + } while (0) + +/* + * Prototypes + */ +struct pmc_mdep *pmc_armv7_initialize(void); +void pmc_armv7_finalize(struct pmc_mdep *_md); +#endif /* _KERNEL */ + +#endif /* !_MACHINE_PMC_MDEP_H_ */ diff --git a/sys/arm/include/proc.h b/sys/arm/include/proc.h new file mode 100644 index 000000000000..a37ccd8f621c --- /dev/null +++ b/sys/arm/include/proc.h @@ -0,0 +1,82 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (c) 1991 Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: @(#)proc.h 7.1 (Berkeley) 5/15/91 + * from: FreeBSD: src/sys/i386/include/proc.h,v 1.11 2001/06/29 + * $FreeBSD$ + */ + +#ifndef _MACHINE_PROC_H_ +#define _MACHINE_PROC_H_ + +#include <machine/utrap.h> + +struct md_utrap { + utrap_entry_t *ut_precise[UT_MAX]; /* must be first */ + int ut_refcnt; +}; + +struct mdthread { + int md_spinlock_count; /* (k) */ + register_t md_saved_cspr; /* (k) */ + register_t md_spurflt_addr; /* (k) Spurious page fault address. */ + int md_ptrace_instr; + int md_ptrace_addr; + int md_ptrace_instr_alt; + int md_ptrace_addr_alt; +}; + +struct mdproc { + struct md_utrap *md_utrap; + void *md_sigtramp; +}; + +#define KINFO_PROC_SIZE 816 + +#define MAXARGS 8 +/* + * This holds the syscall state for a single system call. + * As some syscall arguments may be 64-bit aligned we need to ensure the + * args value is 64-bit aligned. The ABI will then ensure any 64-bit + * arguments are already correctly aligned, even if they were passed in + * via registers, we just need to make sure we copy them to an aligned + * buffer. + */ +struct syscall_args { + u_int code; + struct sysent *callp; + register_t args[MAXARGS]; +} __aligned(8); + +#endif /* !_MACHINE_PROC_H_ */ diff --git a/sys/arm/include/procctl.h b/sys/arm/include/procctl.h new file mode 100644 index 000000000000..5221cfcd7be1 --- /dev/null +++ b/sys/arm/include/procctl.h @@ -0,0 +1,4 @@ +/*- + * This file is in the public domain. + */ +/* $FreeBSD$ */ diff --git a/sys/arm/include/profile.h b/sys/arm/include/profile.h new file mode 100644 index 000000000000..cab8f89ddadf --- /dev/null +++ b/sys/arm/include/profile.h @@ -0,0 +1,124 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)profile.h 8.1 (Berkeley) 6/11/93 + * $FreeBSD$ + */ + +#ifndef _MACHINE_PROFILE_H_ +#define _MACHINE_PROFILE_H_ + +/* + * Config generates something to tell the compiler to align functions on 32 + * byte boundaries. A strict alignment is good for keeping the tables small. + */ +#define FUNCTION_ALIGNMENT 16 + +#define _MCOUNT_DECL void mcount + +typedef u_long fptrdiff_t; + +/* + * Cannot implement mcount in C as GCC will trash the ip register when it + * pushes a trapframe. Pity we cannot insert assembly before the function + * prologue. + */ + +#ifndef PLTSYM +#define PLTSYM +#endif + +#define MCOUNT \ + __asm__(".text"); \ + __asm__(".align 2"); \ + __asm__(".type __mcount ,%function"); \ + __asm__(".global __mcount"); \ + __asm__("__mcount:"); \ + /* \ + * Preserve registers that are trashed during mcount \ + */ \ + __asm__("stmfd sp!, {r0-r3, ip, lr}"); \ + /* \ + * find the return address for mcount, \ + * and the return address for mcount's caller. \ + * \ + * frompcindex = pc pushed by call into self. \ + */ \ + __asm__("mov r0, ip"); \ + /* \ + * selfpc = pc pushed by mcount call \ + */ \ + __asm__("mov r1, lr"); \ + /* \ + * Call the real mcount code \ + */ \ + __asm__("bl mcount"); \ + /* \ + * Restore registers that were trashed during mcount \ + */ \ + __asm__("ldmfd sp!, {r0-r3, lr}"); \ + /* \ + * Return to the caller. Loading lr and pc in one instruction \ + * is deprecated on ARMv7 so we need this on its own. \ + */ \ + __asm__("ldmfd sp!, {pc}"); +void bintr(void); +void btrap(void); +void eintr(void); +void user(void); + +#define MCOUNT_FROMPC_USER(pc) \ + ((pc < (uintfptr_t)VM_MAXUSER_ADDRESS) ? (uintfptr_t)user : pc) + +#define MCOUNT_FROMPC_INTR(pc) \ + ((pc >= (uintfptr_t)btrap && pc < (uintfptr_t)eintr) ? \ + ((pc >= (uintfptr_t)bintr) ? (uintfptr_t)bintr : \ + (uintfptr_t)btrap) : ~0U) + +#ifdef _KERNEL + +#define MCOUNT_DECL(s) register_t s; + +#include <machine/asm.h> +#include <machine/cpufunc.h> +#define MCOUNT_ENTER(s) {s = intr_disable(); } /* kill IRQ */ +#define MCOUNT_EXIT(s) {intr_restore(s); } /* restore old value */ + +void mcount(uintfptr_t frompc, uintfptr_t selfpc); + +#else +typedef u_int uintfptr_t; +#endif /* _KERNEL */ + +#endif /* !_MACHINE_PROFILE_H_ */ diff --git a/sys/arm/include/psl.h b/sys/arm/include/psl.h new file mode 100644 index 000000000000..000e93dd64a6 --- /dev/null +++ b/sys/arm/include/psl.h @@ -0,0 +1,84 @@ +/* $NetBSD: psl.h,v 1.6 2003/06/16 20:00:58 thorpej Exp $ */ + +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (c) 1995 Mark Brinicombe. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Mark Brinicombe + * for the NetBSD Project. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * RiscBSD kernel project + * + * psl.h + * + * spl prototypes. + * Eventually this will become a set of defines. + * + * Created : 21/07/95 + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_PSL_H_ +#define _MACHINE_PSL_H_ + +/* + * These are the different SPL states + * + * Each state has an interrupt mask associated with it which + * indicate which interrupts are allowed. + */ + +#define _SPL_0 0 +#define _SPL_SOFTCLOCK 1 +#define _SPL_SOFTNET 2 +#define _SPL_BIO 3 +#define _SPL_NET 4 +#define _SPL_SOFTSERIAL 5 +#define _SPL_TTY 6 +#define _SPL_VM 7 +#define _SPL_AUDIO 8 +#define _SPL_CLOCK 9 +#define _SPL_STATCLOCK 10 +#define _SPL_HIGH 11 +#define _SPL_SERIAL 12 +#define _SPL_LEVELS 13 + +#ifdef _KERNEL +#ifndef _LOCORE +extern int current_spl_level; + +extern u_int spl_masks[_SPL_LEVELS + 1]; +extern u_int spl_smasks[_SPL_LEVELS]; +#endif /* _LOCORE */ +#endif /* _KERNEL */ + +#endif /* _ARM_PSL_H_ */ +/* End of psl.h */ diff --git a/sys/arm/include/pte-v6.h b/sys/arm/include/pte-v6.h new file mode 100644 index 000000000000..d9aaaea6ef56 --- /dev/null +++ b/sys/arm/include/pte-v6.h @@ -0,0 +1,297 @@ +/*- + * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com> + * Copyright 2014 Michal Meloun <meloun@miracle.cz> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_PTE_V6_H_ +#define _MACHINE_PTE_V6_H_ + +/* + * Domain Types for the Domain Access Control Register. + */ +#define DOMAIN_FAULT 0x00 /* no access */ +#define DOMAIN_CLIENT 0x01 /* client */ +#define DOMAIN_RESERVED 0x02 /* reserved */ +#define DOMAIN_MANAGER 0x03 /* manager */ + +/* + * TEX remap registers attributes + */ +#define PRRR_SO 0 /* Strongly ordered memory */ +#define PRRR_DEV 1 /* Device memory */ +#define PRRR_MEM 2 /* Normal memory */ +#define PRRR_DS0 (1 << 16) /* Shared bit for Device, S = 0 */ +#define PRRR_DS1 (1 << 17) /* Shared bit for Device, S = 1 */ +#define PRRR_NS0 (1 << 18) /* Shared bit for Normal, S = 0 */ +#define PRRR_NS1 (1 << 19) /* Shared bit for Normal, S = 1 */ +#define PRRR_NOS_SHIFT 24 /* base shif for Not Outer Shared bits */ + +#define NMRR_NC 0 /* Noncachable*/ +#define NMRR_WB_WA 1 /* Write Back, Write Allocate */ +#define NMRR_WT 2 /* Write Through, Non-Write Allocate */ +#define NMRR_WB 3 /* Write Back, Non-Write Allocate */ + +/* + * + * The ARM MMU is capable of mapping memory in the following chunks: + * + * 16M Supersections (L1 table) + * + * 1M Sections (L1 table) + * + * 64K Large Pages (L2 table) + * + * 4K Small Pages (L2 table) + * + * + * Coarse Tables can map Large and Small Pages. + * Coarse Tables are 1K in length. + * + * The Translation Table Base register holds the pointer to the + * L1 Table. The L1 Table is a 16K contiguous chunk of memory + * aligned to a 16K boundary. Each entry in the L1 Table maps + * 1M of virtual address space, either via a Section mapping or + * via an L2 Table. + * + */ +#define L1_TABLE_SIZE 0x4000 /* 16K */ +#define L1_ENTRIES 0x1000 /* 4K */ +#define L2_TABLE_SIZE 0x0400 /* 1K */ +#define L2_ENTRIES 0x0100 /* 256 */ + +/* ARMv6 super-sections. */ +#define L1_SUP_SIZE 0x01000000 /* 16M */ +#define L1_SUP_OFFSET (L1_SUP_SIZE - 1) +#define L1_SUP_FRAME (~L1_SUP_OFFSET) +#define L1_SUP_SHIFT 24 + +#define L1_S_SIZE 0x00100000 /* 1M */ +#define L1_S_OFFSET (L1_S_SIZE - 1) +#define L1_S_FRAME (~L1_S_OFFSET) +#define L1_S_SHIFT 20 + +#define L2_L_SIZE 0x00010000 /* 64K */ +#define L2_L_OFFSET (L2_L_SIZE - 1) +#define L2_L_FRAME (~L2_L_OFFSET) +#define L2_L_SHIFT 16 + +#define L2_S_SIZE 0x00001000 /* 4K */ +#define L2_S_OFFSET (L2_S_SIZE - 1) +#define L2_S_FRAME (~L2_S_OFFSET) +#define L2_S_SHIFT 12 + +/* + * ARM MMU L1 Descriptors + */ +#define L1_TYPE_INV 0x00 /* Invalid (fault) */ +#define L1_TYPE_C 0x01 /* Coarse L2 */ +#define L1_TYPE_S 0x02 /* Section */ +#define L1_TYPE_MASK 0x03 /* Mask of type bits */ + +/* L1 Section Descriptor */ +#define L1_S_B 0x00000004 /* bufferable Section */ +#define L1_S_C 0x00000008 /* cacheable Section */ +#define L1_S_NX 0x00000010 /* not executeable */ +#define L1_S_DOM(x) ((x) << 5) /* domain */ +#define L1_S_DOM_MASK L1_S_DOM(0xf) +#define L1_S_P 0x00000200 /* ECC enable for this section */ +#define L1_S_AP(x) ((x) << 10) /* access permissions */ +#define L1_S_AP0 0x00000400 /* access permissions bit 0 */ +#define L1_S_AP1 0x00000800 /* access permissions bit 1 */ +#define L1_S_TEX(x) ((x) << 12) /* type extension */ +#define L1_S_TEX0 0x00001000 /* type extension bit 0 */ +#define L1_S_TEX1 0x00002000 /* type extension bit 1 */ +#define L1_S_TEX2 0x00004000 /* type extension bit 2 */ +#define L1_S_AP2 0x00008000 /* access permissions bit 2 */ +#define L1_S_SHARED 0x00010000 /* shared */ +#define L1_S_NG 0x00020000 /* not global */ +#define L1_S_SUPERSEC 0x00040000 /* Section is a super-section. */ +#define L1_S_ADDR_MASK 0xfff00000 /* phys address of section */ + +/* L1 Coarse Descriptor */ +#define L1_C_DOM(x) ((x) << 5) /* domain */ +#define L1_C_DOM_MASK L1_C_DOM(0xf) +#define L1_C_P 0x00000200 /* ECC enable for this section */ +#define L1_C_ADDR_MASK 0xfffffc00 /* phys address of L2 Table */ + +/* + * ARM MMU L2 Descriptors + */ +#define L2_TYPE_INV 0x00 /* Invalid (fault) */ +#define L2_TYPE_L 0x01 /* Large Page - 64k - not used yet*/ +#define L2_TYPE_S 0x02 /* Small Page - 4 */ +#define L2_TYPE_MASK 0x03 + +#define L2_NX 0x00000001 /* Not executable */ +#define L2_B 0x00000004 /* Bufferable page */ +#define L2_C 0x00000008 /* Cacheable page */ +#define L2_CB_SHIFT 2 /* C,B bit field shift */ +#define L2_AP(x) ((x) << 4) +#define L2_AP0 0x00000010 /* access permissions bit 0*/ +#define L2_AP1 0x00000020 /* access permissions bit 1*/ +#define L2_TEX_SHIFT 6 /* type extension field shift */ +#define L2_TEX(x) ((x) << L2_TEX_SHIFT) /* type extension */ +#define L2_TEX0 0x00000040 /* type extension bit 0 */ +#define L2_TEX1 0x00000080 /* type extension bit 1 */ +#define L2_TEX2 0x00000100 /* type extension bit 2 */ +#define L2_AP2 0x00000200 /* access permissions bit 2*/ +#define L2_SHARED 0x00000400 /* shared */ +#define L2_NG 0x00000800 /* not global */ + +/* + * TEX classes encoding + */ +#define TEX1_CLASS_0 ( 0) +#define TEX1_CLASS_1 ( L1_S_B) +#define TEX1_CLASS_2 ( L1_S_C ) +#define TEX1_CLASS_3 ( L1_S_C | L1_S_B) +#define TEX1_CLASS_4 (L1_S_TEX0 ) +#define TEX1_CLASS_5 (L1_S_TEX0 | L1_S_B) +#define TEX1_CLASS_6 (L1_S_TEX0 | L1_S_C ) /* Reserved for ARM11 */ +#define TEX1_CLASS_7 (L1_S_TEX0 | L1_S_C | L1_S_B) + +#define TEX2_CLASS_0 ( 0) +#define TEX2_CLASS_1 ( L2_B) +#define TEX2_CLASS_2 ( L2_C ) +#define TEX2_CLASS_3 ( L2_C | L2_B) +#define TEX2_CLASS_4 (L2_TEX0 ) +#define TEX2_CLASS_5 (L2_TEX0 | L2_B) +#define TEX2_CLASS_6 (L2_TEX0 | L2_C ) /* Reserved for ARM11 */ +#define TEX2_CLASS_7 (L2_TEX0 | L2_C | L2_B) + +/* L1 table definitions. */ +#define NB_IN_PT1 L1_TABLE_SIZE +#define NPTE1_IN_PT1 L1_ENTRIES + +/* L2 table definitions. */ +#define NB_IN_PT2 L2_TABLE_SIZE +#define NPTE2_IN_PT2 L2_ENTRIES + +/* + * Map memory attributes to TEX classes + */ +#define PTE2_ATTR_WB_WA TEX2_CLASS_0 +#define PTE2_ATTR_NOCACHE TEX2_CLASS_1 +#define PTE2_ATTR_DEVICE TEX2_CLASS_2 +#define PTE2_ATTR_SO TEX2_CLASS_3 +#define PTE2_ATTR_WT TEX2_CLASS_4 +/* + * Software defined bits for L1 descriptors + * - L1_AP0 is used as page accessed bit + * - L1_AP2 (RO / not RW) is used as page not modified bit + * - L1_TEX0 is used as software emulated RO bit + */ +#define PTE1_V L1_TYPE_S /* Valid bit */ +#define PTE1_A L1_S_AP0 /* Accessed - software emulated */ +#define PTE1_NM L1_S_AP2 /* not modified bit - software emulated + * used as real write enable bit */ +#define PTE1_M 0 /* Modified (dummy) */ +#define PTE1_S L1_S_SHARED /* Shared */ +#define PTE1_NG L1_S_NG /* Not global */ +#define PTE1_G 0 /* Global (dummy) */ +#define PTE1_NX L1_S_NX /* Not executable */ +#define PTE1_X 0 /* Executable (dummy) */ +#define PTE1_RO L1_S_TEX1 /* Read Only */ +#define PTE1_RW 0 /* Read-Write (dummy) */ +#define PTE1_U L1_S_AP1 /* User */ +#define PTE1_NU 0 /* Not user (kernel only) (dummy) */ +#define PTE1_W L1_S_TEX2 /* Wired */ + +#define PTE1_SHIFT L1_S_SHIFT +#define PTE1_SIZE L1_S_SIZE +#define PTE1_OFFSET L1_S_OFFSET +#define PTE1_FRAME L1_S_FRAME + +#define PTE1_ATTR_MASK (L1_S_TEX0 | L1_S_C | L1_S_B) + +#define PTE1_AP_KR (PTE1_RO | PTE1_NM) +#define PTE1_AP_KRW 0 +#define PTE1_AP_KRUR (PTE1_RO | PTE1_NM | PTE1_U) +#define PTE1_AP_KRWURW PTE1_U + +/* + * PTE1 descriptors creation macros. + */ +#define PTE1_PA(pa) ((pa) & PTE1_FRAME) +#define PTE1_AP_COMMON (PTE1_V | PTE1_S) + +#define PTE1(pa, ap, attr) (PTE1_PA(pa) | (ap) | (attr) | PTE1_AP_COMMON) + +#define PTE1_KERN(pa, ap, attr) PTE1(pa, (ap) | PTE1_A | PTE1_G, attr) +#define PTE1_KERN_NG(pa, ap, attr) PTE1(pa, (ap) | PTE1_A | PTE1_NG, attr) + +#define PTE1_LINK(pa) (((pa) & L1_C_ADDR_MASK) | L1_TYPE_C) + +/* + * Software defined bits for L2 descriptors + * - L2_AP0 is used as page accessed bit + * - L2_AP2 (RO / not RW) is used as page not modified bit + * - L2_TEX0 is used as software emulated RO bit + */ +#define PTE2_V L2_TYPE_S /* Valid bit */ +#define PTE2_A L2_AP0 /* Accessed - software emulated */ +#define PTE2_NM L2_AP2 /* not modified bit - software emulated + * used as real write enable bit */ +#define PTE2_M 0 /* Modified (dummy) */ +#define PTE2_S L2_SHARED /* Shared */ +#define PTE2_NG L2_NG /* Not global */ +#define PTE2_G 0 /* Global (dummy) */ +#define PTE2_NX L2_NX /* Not executable */ +#define PTE2_X 0 /* Not executable (dummy) */ +#define PTE2_RO L2_TEX1 /* Read Only */ +#define PTE2_U L2_AP1 /* User */ +#define PTE2_NU 0 /* Not user (kernel only) (dummy) */ +#define PTE2_W L2_TEX2 /* Wired */ + +#define PTE2_SHIFT L2_S_SHIFT +#define PTE2_SIZE L2_S_SIZE +#define PTE2_OFFSET L2_S_OFFSET +#define PTE2_FRAME L2_S_FRAME + +#define PTE2_ATTR_MASK (L2_TEX0 | L2_C | L2_B) +/* PTE2 attributes to TEX class index: (TEX0 C B) */ +#define PTE2_ATTR2IDX(attr) \ + ((((attr) & (L2_C | L2_B)) >> L2_CB_SHIFT) | \ + (((attr) & L2_TEX0) >> (L2_TEX_SHIFT - L2_CB_SHIFT))) + +#define PTE2_AP_KR (PTE2_RO | PTE2_NM) +#define PTE2_AP_KRW 0 +#define PTE2_AP_KRUR (PTE2_RO | PTE2_NM | PTE2_U) +#define PTE2_AP_KRWURW PTE2_U + +/* + * PTE2 descriptors creation macros. + */ +#define PTE2_PA(pa) ((pa) & PTE2_FRAME) +#define PTE2_AP_COMMON (PTE2_V | PTE2_S) + +#define PTE2(pa, ap, attr) (PTE2_PA(pa) | (ap) | (attr) | PTE2_AP_COMMON) + +#define PTE2_KERN(pa, ap, attr) PTE2(pa, (ap) | PTE2_A | PTE2_G, attr) +#define PTE2_KERN_NG(pa, ap, attr) PTE2(pa, (ap) | PTE2_A | PTE2_NG, attr) + +#endif /* !_MACHINE_PTE_V6_H_ */ diff --git a/sys/arm/include/ptrace.h b/sys/arm/include/ptrace.h new file mode 100644 index 000000000000..44085a3b7079 --- /dev/null +++ b/sys/arm/include/ptrace.h @@ -0,0 +1,22 @@ +/* $NetBSD: ptrace.h,v 1.2 2001/02/23 21:23:52 reinoud Exp $ */ +/* $FreeBSD$ */ + +#ifndef _MACHINE_PTRACE_H_ +#define _MACHINE_PTRACE_H_ + +#define __HAVE_PTRACE_MACHDEP + +/* + * Must match mcontext_vfp_t. Note that mcontext_vfp_t does not + * include explicit padding. + */ +struct vfpreg { + __uint64_t vfp_reg[32]; + __uint32_t vfp_scr; + __uint32_t vfp_pad0; +}; + +#define PT_GETVFPREGS (PT_FIRSTMACH + 0) +#define PT_SETVFPREGS (PT_FIRSTMACH + 1) + +#endif /* !_MACHINE_PTRACE_H */ diff --git a/sys/arm/include/reg.h b/sys/arm/include/reg.h new file mode 100644 index 000000000000..ab70ae128d39 --- /dev/null +++ b/sys/arm/include/reg.h @@ -0,0 +1,42 @@ +/* $NetBSD: reg.h,v 1.2 2001/02/23 21:23:52 reinoud Exp $ */ +/* $FreeBSD$ */ +#ifndef MACHINE_REG_H +#define MACHINE_REG_H + +struct reg { + unsigned int r[13]; + unsigned int r_sp; + unsigned int r_lr; + unsigned int r_pc; + unsigned int r_cpsr; +}; + +struct fp_extended_precision { + u_int32_t fp_exponent; + u_int32_t fp_mantissa_hi; + u_int32_t fp_mantissa_lo; +}; + +typedef struct fp_extended_precision fp_reg_t; + +struct fpreg { + unsigned int fpr_fpsr; + fp_reg_t fpr[8]; +}; + +struct dbreg { +#define ARM_WR_MAX 16 /* Maximum number of watchpoint registers */ + unsigned int dbg_wcr[ARM_WR_MAX]; /* Watchpoint Control Registers */ + unsigned int dbg_wvr[ARM_WR_MAX]; /* Watchpoint Value Registers */ +}; + +#ifdef _KERNEL +int fill_regs(struct thread *, struct reg *); +int set_regs(struct thread *, struct reg *); +int fill_fpregs(struct thread *, struct fpreg *); +int set_fpregs(struct thread *, struct fpreg *); +int fill_dbregs(struct thread *, struct dbreg *); +int set_dbregs(struct thread *, struct dbreg *); +#endif + +#endif /* !MACHINE_REG_H */ diff --git a/sys/arm/include/reloc.h b/sys/arm/include/reloc.h new file mode 100644 index 000000000000..688475703225 --- /dev/null +++ b/sys/arm/include/reloc.h @@ -0,0 +1,55 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)reloc.h 8.1 (Berkeley) 6/10/93 + * $FreeBSD$ + */ + +#ifndef _MACHINE_RELOC_H_ +#define _MACHINE_RELOC_H_ + +/* Relocation format. */ +struct relocation_info { + int r_address; /* offset in text or data segment */ + unsigned int r_symbolnum : 24, /* ordinal number of add symbol */ + r_pcrel : 1, /* 1 if value should be pc-relative */ + r_length : 2, /* log base 2 of value's width */ + r_extern : 1, /* 1 if need to add symbol to value */ + r_baserel : 1, /* linkage table relative */ + r_jmptable : 1, /* relocate to jump table */ + r_relative : 1, /* load address relative */ + r_copy : 1; /* run time copy */ +}; + +#endif diff --git a/sys/arm/include/resource.h b/sys/arm/include/resource.h new file mode 100644 index 000000000000..bfa5b3f98790 --- /dev/null +++ b/sys/arm/include/resource.h @@ -0,0 +1,49 @@ +/*- + * Copyright 1998 Massachusetts Institute of Technology + * + * Permission to use, copy, modify, and distribute this software and + * its documentation for any purpose and without fee is hereby + * granted, provided that both the above copyright notice and this + * permission notice appear in all copies, that both the above + * copyright notice and this permission notice appear in all + * supporting documentation, and that the name of M.I.T. not be used + * in advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. M.I.T. makes + * no representations about the suitability of this software for any + * purpose. It is provided "as is" without express or implied + * warranty. + * + * THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS + * ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT + * SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_RESOURCE_H_ +#define _MACHINE_RESOURCE_H_ 1 + +/* + * Definitions of resource types for Intel Architecture machines + * with support for legacy ISA devices and drivers. + */ + +#define SYS_RES_IRQ 1 /* interrupt lines */ +#define SYS_RES_DRQ 2 /* isa dma lines */ +#define SYS_RES_MEMORY 3 /* i/o memory */ +#define SYS_RES_IOPORT 4 /* i/o ports */ +#define SYS_RES_GPIO 5 /* general purpose i/o */ +#ifdef NEW_PCIB +#define PCI_RES_BUS 6 /* PCI bus numbers */ +#endif + +#endif /* !_MACHINE_RESOURCE_H_ */ diff --git a/sys/arm/include/runq.h b/sys/arm/include/runq.h new file mode 100644 index 000000000000..ba21b9ab4316 --- /dev/null +++ b/sys/arm/include/runq.h @@ -0,0 +1,48 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2001 Jake Burkholder <jake@FreeBSD.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_RUNQ_H_ +#define _MACHINE_RUNQ_H_ + +#define RQB_LEN (2) /* Number of priority status words. */ +#define RQB_L2BPW (5) /* Log2(sizeof(rqb_word_t) * NBBY)). */ +#define RQB_BPW (1<<RQB_L2BPW) /* Bits in an rqb_word_t. */ + +#define RQB_BIT(pri) (1 << ((pri) & (RQB_BPW - 1))) +#define RQB_WORD(pri) ((pri) >> RQB_L2BPW) + +#define RQB_FFS(word) (ffs(word) - 1) + +/* + * Type of run queue status word. + */ +typedef u_int32_t rqb_word_t; + +#endif diff --git a/sys/arm/include/sc_machdep.h b/sys/arm/include/sc_machdep.h new file mode 100644 index 000000000000..61a2a86f702d --- /dev/null +++ b/sys/arm/include/sc_machdep.h @@ -0,0 +1,73 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2003 Jake Burkholder. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_SC_MACHDEP_H_ +#define _MACHINE_SC_MACHDEP_H_ + +/* Color attributes for foreground text */ + +#define FG_BLACK 0x0 +#define FG_BLUE 0x1 +#define FG_GREEN 0x2 +#define FG_CYAN 0x3 +#define FG_RED 0x4 +#define FG_MAGENTA 0x5 +#define FG_BROWN 0x6 +#define FG_LIGHTGREY 0x7 /* aka white */ +#define FG_DARKGREY 0x8 +#define FG_LIGHTBLUE 0x9 +#define FG_LIGHTGREEN 0xa +#define FG_LIGHTCYAN 0xb +#define FG_LIGHTRED 0xc +#define FG_LIGHTMAGENTA 0xd +#define FG_YELLOW 0xe +#define FG_WHITE 0xf /* aka bright white */ +#define FG_BLINK 0x80 + +/* Color attributes for text background */ + +#define BG_BLACK 0x00 +#define BG_BLUE 0x10 +#define BG_GREEN 0x20 +#define BG_CYAN 0x30 +#define BG_RED 0x40 +#define BG_MAGENTA 0x50 +#define BG_BROWN 0x60 +#define BG_LIGHTGREY 0x70 +#define BG_DARKGREY 0x80 +#define BG_LIGHTBLUE 0x90 +#define BG_LIGHTGREEN 0xa0 +#define BG_LIGHTCYAN 0xb0 +#define BG_LIGHTRED 0xc0 +#define BG_LIGHTMAGENTA 0xd0 +#define BG_YELLOW 0xe0 +#define BG_WHITE 0xf0 + +#endif /* !_MACHINE_SC_MACHDEP_H_ */ diff --git a/sys/arm/include/setjmp.h b/sys/arm/include/setjmp.h new file mode 100644 index 000000000000..2090c5d15f40 --- /dev/null +++ b/sys/arm/include/setjmp.h @@ -0,0 +1,107 @@ +/* $NetBSD: setjmp.h,v 1.5 2013/01/11 13:56:32 matt Exp $ */ +/* $FreeBSD$ */ + +/* + * machine/setjmp.h: machine dependent setjmp-related information. + */ + +#ifndef _MACHINE_SETJMP_H_ +#define _MACHINE_SETJMP_H_ + +#define _JBLEN 64 /* size, in longs, of a jmp_buf */ + +/* + * NOTE: The internal structure of a jmp_buf is *PRIVATE* + * This information is provided as there is software + * that fiddles with this with obtain the stack pointer + * (yes really ! and its commercial !). + * + * Description of the setjmp buffer + * + * word 0 magic number (dependent on creator) + * 13 fpscr vfp status control register + * 14 r4 register 4 + * 15 r5 register 5 + * 16 r6 register 6 + * 17 r7 register 7 + * 18 r8 register 8 + * 19 r9 register 9 + * 20 r10 register 10 (sl) + * 21 r11 register 11 (fp) + * 22 r12 register 12 (ip) + * 23 r13 register 13 (sp) + * 24 r14 register 14 (lr) + * 25 signal mask (dependent on magic) + * 26 (con't) + * 27 (con't) + * 28 (con't) + * 32-33 d8 (vfp register d8) + * 34-35 d9 (vfp register d9) + * 36-37 d10 (vfp register d10) + * 38-39 d11 (vfp register d11) + * 40-41 d12 (vfp register d12) + * 42-43 d13 (vfp register d13) + * 44-45 d14 (vfp register d14) + * 46-47 d15 (vfp register d15) + * + * The magic number number identifies the jmp_buf and + * how the buffer was created as well as providing + * a sanity check + * + * A side note I should mention - Please do not tamper + * with the floating point fields. While they are + * always saved and restored at the moment this cannot + * be garenteed especially if the compiler happens + * to be generating soft-float code so no fp + * registers will be used. + * + * Whilst this can be seen an encouraging people to + * use the setjmp buffer in this way I think that it + * is for the best then if changes occur compiles will + * break rather than just having new builds falling over + * mysteriously. + */ + +#define _JB_MAGIC__SETJMP 0x4278f500 +#define _JB_MAGIC_SETJMP 0x4278f501 +#define _JB_MAGIC__SETJMP_VFP 0x4278f502 +#define _JB_MAGIC_SETJMP_VFP 0x4278f503 + +/* Valid for all jmp_buf's */ + +#define _JB_MAGIC 0 +#define _JB_REG_FPSCR 13 +#define _JB_REG_R4 14 +#define _JB_REG_R5 15 +#define _JB_REG_R6 16 +#define _JB_REG_R7 17 +#define _JB_REG_R8 18 +#define _JB_REG_R9 19 +#define _JB_REG_R10 20 +#define _JB_REG_R11 21 +#define _JB_REG_R12 22 +#define _JB_REG_R13 23 +#define _JB_REG_R14 24 + +/* Only valid with the _JB_MAGIC_SETJMP magic */ + +#define _JB_SIGMASK 25 + +#define _JB_REG_D8 32 +#define _JB_REG_D9 34 +#define _JB_REG_D10 36 +#define _JB_REG_D11 38 +#define _JB_REG_D12 40 +#define _JB_REG_D13 42 +#define _JB_REG_D14 44 +#define _JB_REG_D15 46 + +#ifndef __ASSEMBLER__ +#if __BSD_VISIBLE || __POSIX_VISIBLE || __XSI_VISIBLE +typedef struct _sigjmp_buf { int _sjb[_JBLEN + 1]; } sigjmp_buf[1]; +#endif + +typedef struct _jmp_buf { int _jb[_JBLEN + 1]; } jmp_buf[1]; +#endif + +#endif /* !_MACHINE_SETJMP_H_ */ diff --git a/sys/arm/include/sf_buf.h b/sys/arm/include/sf_buf.h new file mode 100644 index 000000000000..65ef6f99b7a1 --- /dev/null +++ b/sys/arm/include/sf_buf.h @@ -0,0 +1,48 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2003 Alan L. Cox <alc@cs.rice.edu> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_SF_BUF_H_ +#define _MACHINE_SF_BUF_H_ + +static inline void +sf_buf_map(struct sf_buf *sf, int flags) +{ + + pmap_qenter(sf->kva, &(sf->m), 1); +} + +static inline int +sf_buf_unmap(struct sf_buf *sf) +{ + + pmap_qremove(sf->kva, 1); + return (1); +} +#endif /* !_MACHINE_SF_BUF_H_ */ diff --git a/sys/arm/include/sigframe.h b/sys/arm/include/sigframe.h new file mode 100644 index 000000000000..9787f579d563 --- /dev/null +++ b/sys/arm/include/sigframe.h @@ -0,0 +1,2 @@ +/* $FreeBSD$ */ +#include <machine/frame.h> diff --git a/sys/arm/include/signal.h b/sys/arm/include/signal.h new file mode 100644 index 000000000000..2286bcea2d2d --- /dev/null +++ b/sys/arm/include/signal.h @@ -0,0 +1,52 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 1986, 1989, 1991, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)signal.h 8.1 (Berkeley) 6/11/93 + * from: FreeBSD: src/sys/i386/include/signal.h,v 1.13 2000/11/09 + * from: FreeBSD: src/sys/sparc64/include/signal.h,v 1.6 2001/09/30 18:52:17 + * $FreeBSD$ + */ + +#ifndef _MACHINE_SIGNAL_H_ +#define _MACHINE_SIGNAL_H_ + +#include <sys/cdefs.h> + +typedef long sig_atomic_t; + +#if __BSD_VISIBLE + +struct sigcontext { + int _dummy; +}; + +#endif + +#endif /* !_MACHINE_SIGNAL_H_ */ diff --git a/sys/arm/include/smp.h b/sys/arm/include/smp.h new file mode 100644 index 000000000000..4f1545872a4e --- /dev/null +++ b/sys/arm/include/smp.h @@ -0,0 +1,35 @@ +/* $FreeBSD$ */ + +#ifndef _MACHINE_SMP_H_ +#define _MACHINE_SMP_H_ + +#include <sys/_cpuset.h> +#include <machine/pcb.h> + +enum { + IPI_AST, + IPI_PREEMPT, + IPI_RENDEZVOUS, + IPI_STOP, + IPI_STOP_HARD = IPI_STOP, /* These are synonyms on arm. */ + IPI_HARDCLOCK, + IPI_TLB, /* Not used now, but keep it reserved. */ + IPI_CACHE, /* Not used now, but keep it reserved. */ + INTR_IPI_COUNT +}; + +void init_secondary(int cpu); +void mpentry(void); + +void ipi_all_but_self(u_int ipi); +void ipi_cpu(int cpu, u_int ipi); +void ipi_selected(cpuset_t cpus, u_int ipi); + +/* Platform interface */ +void platform_mp_setmaxid(void); +void platform_mp_start_ap(void); + +/* global data in mp_machdep.c */ +extern struct pcb stoppcbs[]; + +#endif /* !_MACHINE_SMP_H_ */ diff --git a/sys/arm/include/stack.h b/sys/arm/include/stack.h new file mode 100644 index 000000000000..4bc384f775bc --- /dev/null +++ b/sys/arm/include/stack.h @@ -0,0 +1,68 @@ +/*- + * Copyright (c) 2000, 2001 Ben Harris + * Copyright (c) 1996 Scott K. Stevens + * + * Mach Operating System + * Copyright (c) 1991,1990 Carnegie Mellon University + * All Rights Reserved. + * + * Permission to use, copy, modify and distribute this software and its + * documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR + * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_STACK_H_ +#define _MACHINE_STACK_H_ + +#define INKERNEL(va) (((vm_offset_t)(va)) >= VM_MIN_KERNEL_ADDRESS) + +#define FR_SCP (0) +#define FR_RLV (-1) +#define FR_RSP (-2) +#define FR_RFP (-3) + +/* The state of the unwind process */ +struct unwind_state { + uint32_t registers[16]; + uint32_t start_pc; + uint32_t *insn; + u_int entries; + u_int byte; + uint16_t update_mask; +}; + +/* The register names */ +#define FP 11 +#define SP 13 +#define LR 14 +#define PC 15 + +#ifdef _KERNEL + +int unwind_stack_one(struct unwind_state *, int); + +struct linker_file; +void unwind_module_loaded(struct linker_file *); +void unwind_module_unloaded(struct linker_file *); + +#endif + +#endif /* !_MACHINE_STACK_H_ */ diff --git a/sys/arm/include/stdarg.h b/sys/arm/include/stdarg.h new file mode 100644 index 000000000000..acb526429ac2 --- /dev/null +++ b/sys/arm/include/stdarg.h @@ -0,0 +1,39 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2017 Poul-Henning Kamp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_STDARG_H_ +#define _MACHINE_STDARG_H_ + +#include <sys/_stdarg.h> + +#ifndef va_start + #error this file needs to be ported to your compiler +#endif + +#endif /* !_MACHINE_STDARG_H_ */ diff --git a/sys/arm/include/swi.h b/sys/arm/include/swi.h new file mode 100644 index 000000000000..b2caf5ee1c31 --- /dev/null +++ b/sys/arm/include/swi.h @@ -0,0 +1,22 @@ +/* $NetBSD: swi.h,v 1.1 2002/01/13 15:03:06 bjh21 Exp $ */ +/* $FreeBSD$ */ + +/*- + * This file is in the Public Domain. + * Ben Harris, 2002. + */ + +#ifndef _MACHINE_SWI_H_ +#define _MACHINE_SWI_H_ + +#define SWI_OS_MASK 0xf00000 +#define SWI_OS_RISCOS 0x000000 +#define SWI_OS_RISCIX 0x800000 +#define SWI_OS_LINUX 0x900000 +#define SWI_OS_NETBSD 0xa00000 +#define SWI_OS_ARM 0xf00000 + +#define SWI_IMB 0xf00000 +#define SWI_IMBrange 0xf00001 + +#endif /* !_MACHINE_SWI_H_ */ diff --git a/sys/arm/include/sysarch.h b/sys/arm/include/sysarch.h new file mode 100644 index 000000000000..603d8c5a852c --- /dev/null +++ b/sys/arm/include/sysarch.h @@ -0,0 +1,83 @@ +/* $NetBSD: sysarch.h,v 1.5 2003/09/11 09:40:12 kleink Exp $ */ + +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (c) 1996-1997 Mark Brinicombe. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Mark Brinicombe. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* $FreeBSD$ */ + +#ifndef _ARM_SYSARCH_H_ +#define _ARM_SYSARCH_H_ + +#include <machine/armreg.h> + +#ifndef LOCORE +#ifndef __ASSEMBLER__ + +/* + * Pickup definition of various __types. + */ +#include <sys/_types.h> + +/* + * Architecture specific syscalls (arm) + */ + +#define ARM_SYNC_ICACHE 0 +#define ARM_DRAIN_WRITEBUF 1 +#define ARM_SET_TP 2 +#define ARM_GET_TP 3 +#define ARM_GET_VFPSTATE 4 + +struct arm_sync_icache_args { + __uintptr_t addr; /* Virtual start address */ + __size_t len; /* Region size */ +}; + +struct arm_get_vfpstate_args { + __size_t mc_vfp_size; + void *mc_vfp; +}; + +#ifndef _KERNEL +__BEGIN_DECLS +int arm_sync_icache(unsigned int, int); +int arm_drain_writebuf(void); +int sysarch(int, void *); +__END_DECLS +#endif + +#endif /* __ASSEMBLER__ */ +#endif /* LOCORE */ + +#endif /* !_ARM_SYSARCH_H_ */ diff --git a/sys/arm/include/sysreg.h b/sys/arm/include/sysreg.h new file mode 100644 index 000000000000..ca8a1abdea3f --- /dev/null +++ b/sys/arm/include/sysreg.h @@ -0,0 +1,325 @@ +/*- + * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com> + * Copyright 2014 Michal Meloun <meloun@miracle.cz> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Macros to make working with the System Control Registers simpler. + * + * Note that when register r0 is hard-coded in these definitions it means the + * cp15 operation neither reads nor writes the register, and r0 is used only + * because some syntatically-valid register name has to appear at that point to + * keep the asm parser happy. + */ + +#ifndef MACHINE_SYSREG_H +#define MACHINE_SYSREG_H + +/* + * CP14 registers + */ +#define CP14_DBGDIDR(rr) p14, 0, rr, c0, c0, 0 /* Debug ID Register */ +#define CP14_DBGDSCRext_V6(rr) p14, 0, rr, c0, c1, 0 /* Debug Status and Ctrl Register v6 */ +#define CP14_DBGDSCRext_V7(rr) p14, 0, rr, c0, c2, 2 /* Debug Status and Ctrl Register v7 */ +#define CP14_DBGVCR(rr) p14, 0, rr, c0, c7, 0 /* Vector Catch Register */ +#define CP14_DBGOSLAR(rr) p14, 0, rr, c1, c0, 4 /* OS Lock Access Register */ +#define CP14_DBGOSLSR(rr) p14, 0, rr, c1, c1, 4 /* OS Lock Status Register */ +#define CP14_DBGOSDLR(rr) p14, 0, rr, c1, c3, 4 /* OS Double Lock Register */ +#define CP14_DBGPRSR(rr) p14, 0, rr, c1, c5, 4 /* Device Powerdown and Reset Status */ + +#define CP14_DBGDSCRint(rr) CP14_DBGDSCRext_V6(rr) /* Debug Status and Ctrl internal view */ + +/* + * CP15 C0 registers + */ +#define CP15_MIDR(rr) p15, 0, rr, c0, c0, 0 /* Main ID Register */ +#define CP15_CTR(rr) p15, 0, rr, c0, c0, 1 /* Cache Type Register */ +#define CP15_TCMTR(rr) p15, 0, rr, c0, c0, 2 /* TCM Type Register */ +#define CP15_TLBTR(rr) p15, 0, rr, c0, c0, 3 /* TLB Type Register */ +#define CP15_MPIDR(rr) p15, 0, rr, c0, c0, 5 /* Multiprocessor Affinity Register */ +#define CP15_REVIDR(rr) p15, 0, rr, c0, c0, 6 /* Revision ID Register */ + +#define CP15_ID_PFR0(rr) p15, 0, rr, c0, c1, 0 /* Processor Feature Register 0 */ +#define CP15_ID_PFR1(rr) p15, 0, rr, c0, c1, 1 /* Processor Feature Register 1 */ +#define CP15_ID_DFR0(rr) p15, 0, rr, c0, c1, 2 /* Debug Feature Register 0 */ +#define CP15_ID_AFR0(rr) p15, 0, rr, c0, c1, 3 /* Auxiliary Feature Register 0 */ +#define CP15_ID_MMFR0(rr) p15, 0, rr, c0, c1, 4 /* Memory Model Feature Register 0 */ +#define CP15_ID_MMFR1(rr) p15, 0, rr, c0, c1, 5 /* Memory Model Feature Register 1 */ +#define CP15_ID_MMFR2(rr) p15, 0, rr, c0, c1, 6 /* Memory Model Feature Register 2 */ +#define CP15_ID_MMFR3(rr) p15, 0, rr, c0, c1, 7 /* Memory Model Feature Register 3 */ + +#define CP15_ID_ISAR0(rr) p15, 0, rr, c0, c2, 0 /* Instruction Set Attribute Register 0 */ +#define CP15_ID_ISAR1(rr) p15, 0, rr, c0, c2, 1 /* Instruction Set Attribute Register 1 */ +#define CP15_ID_ISAR2(rr) p15, 0, rr, c0, c2, 2 /* Instruction Set Attribute Register 2 */ +#define CP15_ID_ISAR3(rr) p15, 0, rr, c0, c2, 3 /* Instruction Set Attribute Register 3 */ +#define CP15_ID_ISAR4(rr) p15, 0, rr, c0, c2, 4 /* Instruction Set Attribute Register 4 */ +#define CP15_ID_ISAR5(rr) p15, 0, rr, c0, c2, 5 /* Instruction Set Attribute Register 5 */ + +#define CP15_CCSIDR(rr) p15, 1, rr, c0, c0, 0 /* Cache Size ID Registers */ +#define CP15_CLIDR(rr) p15, 1, rr, c0, c0, 1 /* Cache Level ID Register */ +#define CP15_AIDR(rr) p15, 1, rr, c0, c0, 7 /* Auxiliary ID Register */ + +#define CP15_CSSELR(rr) p15, 2, rr, c0, c0, 0 /* Cache Size Selection Register */ + +#define CP15_VPIDR(rr) p15, 4, rr, c0, c0, 0 /* Virtualization Processor ID Register */ +#define CP15_VMPIDR(rr) p15, 4, rr, c0, c0, 5 /* Virtualization Multiprocessor ID Register */ + +/* + * CP15 C1 registers + */ +#define CP15_SCTLR(rr) p15, 0, rr, c1, c0, 0 /* System Control Register */ +#define CP15_ACTLR(rr) p15, 0, rr, c1, c0, 1 /* IMPLEMENTATION DEFINED Auxiliary Control Register */ +#define CP15_CPACR(rr) p15, 0, rr, c1, c0, 2 /* Coprocessor Access Control Register */ + +#define CP15_SCR(rr) p15, 0, rr, c1, c1, 0 /* Secure Configuration Register */ +#define CP15_SDER(rr) p15, 0, rr, c1, c1, 1 /* Secure Debug Enable Register */ +#define CP15_NSACR(rr) p15, 0, rr, c1, c1, 2 /* Non-Secure Access Control Register */ + +#define CP15_HSCTLR(rr) p15, 4, rr, c1, c0, 0 /* Hyp System Control Register */ + +#define CP15_HCR(rr) p15, 4, rr, c1, c1, 0 /* Hyp Configuration Register */ +#define CP15_HDCR(rr) p15, 4, rr, c1, c1, 1 /* Hyp Debug Configuration Register */ +#define CP15_HCPTR(rr) p15, 4, rr, c1, c1, 2 /* Hyp Coprocessor Trap Register */ +#define CP15_HSTR(rr) p15, 4, rr, c1, c1, 3 /* Hyp System Trap Register */ + +/* + * CP15 C2 registers + */ +#define CP15_TTBR0(rr) p15, 0, rr, c2, c0, 0 /* Translation Table Base Register 0 */ +#define CP15_TTBR1(rr) p15, 0, rr, c2, c0, 1 /* Translation Table Base Register 1 */ +#define CP15_TTBCR(rr) p15, 0, rr, c2, c0, 2 /* Translation Table Base Control Register */ + +#define CP15_HTCR(rr) p15, 4, rr, c2, c0, 2 /* Hyp Translation Control Register */ +#define CP15_VTCR(rr) p15, 4, rr, c2, c1, 2 /* Virtualization Translation Control Register */ + +/* + * CP15 C3 registers + */ +#define CP15_DACR(rr) p15, 0, rr, c3, c0, 0 /* Domain Access Control Register */ + +/* + * CP15 C5 registers + */ +#define CP15_DFSR(rr) p15, 0, rr, c5, c0, 0 /* Data Fault Status Register */ +#define CP15_HSR(rr) p15, 4, rr, c5, c2, 0 /* Hyp Syndrome Register */ + +/* From ARMv6: */ +#define CP15_IFSR(rr) p15, 0, rr, c5, c0, 1 /* Instruction Fault Status Register */ +#if __ARM_ARCH >= 7 +/* From ARMv7: */ +#define CP15_ADFSR(rr) p15, 0, rr, c5, c1, 0 /* Auxiliary Data Fault Status Register */ +#define CP15_AIFSR(rr) p15, 0, rr, c5, c1, 1 /* Auxiliary Instruction Fault Status Register */ +#endif + +/* + * CP15 C6 registers + */ +#define CP15_DFAR(rr) p15, 0, rr, c6, c0, 0 /* Data Fault Address Register */ +#define CP15_HDFAR(rr) p15, 4, rr, c6, c0, 0 /* Hyp Data Fault Address Register */ +#define CP15_HIFAR(rr) p15, 4, rr, c6, c0, 2 /* Hyp Instruction Fault Address Register */ +#define CP15_HPFAR(rr) p15, 4, rr, c6, c0, 4 /* Hyp IPA Fault Address Register */ + +/* From ARMv6k: */ +#define CP15_IFAR(rr) p15, 0, rr, c6, c0, 2 /* Instruction Fault Address Register */ + +/* + * CP15 C7 registers + */ +#if __ARM_ARCH >= 7 && defined(SMP) +/* From ARMv7: */ +#define CP15_ICIALLUIS p15, 0, r0, c7, c1, 0 /* Instruction cache invalidate all PoU, IS */ +#define CP15_BPIALLIS p15, 0, r0, c7, c1, 6 /* Branch predictor invalidate all IS */ +#endif + +#define CP15_PAR(rr) p15, 0, rr, c7, c4, 0 /* Physical Address Register */ + +#define CP15_ICIALLU p15, 0, r0, c7, c5, 0 /* Instruction cache invalidate all PoU */ +#define CP15_ICIMVAU(rr) p15, 0, rr, c7, c5, 1 /* Instruction cache invalidate */ +#if __ARM_ARCH == 6 +/* Deprecated in ARMv7 */ +#define CP15_CP15ISB p15, 0, r0, c7, c5, 4 /* ISB */ +#endif +#define CP15_BPIALL p15, 0, r0, c7, c5, 6 /* Branch predictor invalidate all */ +#define CP15_BPIMVA p15, 0, rr, c7, c5, 7 /* Branch predictor invalidate by MVA */ + +#if __ARM_ARCH == 6 +/* Only ARMv6: */ +#define CP15_DCIALL p15, 0, r0, c7, c6, 0 /* Data cache invalidate all */ +#endif +#define CP15_DCIMVAC(rr) p15, 0, rr, c7, c6, 1 /* Data cache invalidate by MVA PoC */ +#define CP15_DCISW(rr) p15, 0, rr, c7, c6, 2 /* Data cache invalidate by set/way */ + +#define CP15_ATS1CPR(rr) p15, 0, rr, c7, c8, 0 /* Stage 1 Current state PL1 read */ +#define CP15_ATS1CPW(rr) p15, 0, rr, c7, c8, 1 /* Stage 1 Current state PL1 write */ +#define CP15_ATS1CUR(rr) p15, 0, rr, c7, c8, 2 /* Stage 1 Current state unprivileged read */ +#define CP15_ATS1CUW(rr) p15, 0, rr, c7, c8, 3 /* Stage 1 Current state unprivileged write */ + +#if __ARM_ARCH >= 7 +/* From ARMv7: */ +#define CP15_ATS12NSOPR(rr) p15, 0, rr, c7, c8, 4 /* Stages 1 and 2 Non-secure only PL1 read */ +#define CP15_ATS12NSOPW(rr) p15, 0, rr, c7, c8, 5 /* Stages 1 and 2 Non-secure only PL1 write */ +#define CP15_ATS12NSOUR(rr) p15, 0, rr, c7, c8, 6 /* Stages 1 and 2 Non-secure only unprivileged read */ +#define CP15_ATS12NSOUW(rr) p15, 0, rr, c7, c8, 7 /* Stages 1 and 2 Non-secure only unprivileged write */ +#endif + +#if __ARM_ARCH == 6 +/* Only ARMv6: */ +#define CP15_DCCALL p15, 0, r0, c7, c10, 0 /* Data cache clean all */ +#endif +#define CP15_DCCMVAC(rr) p15, 0, rr, c7, c10, 1 /* Data cache clean by MVA PoC */ +#define CP15_DCCSW(rr) p15, 0, rr, c7, c10, 2 /* Data cache clean by set/way */ +#if __ARM_ARCH == 6 +/* Only ARMv6: */ +#define CP15_CP15DSB p15, 0, r0, c7, c10, 4 /* DSB */ +#define CP15_CP15DMB p15, 0, r0, c7, c10, 5 /* DMB */ +#define CP15_CP15WFI p15, 0, r0, c7, c0, 4 /* WFI */ +#endif + +#if __ARM_ARCH >= 7 +/* From ARMv7: */ +#define CP15_DCCMVAU(rr) p15, 0, rr, c7, c11, 1 /* Data cache clean by MVA PoU */ +#endif + +#if __ARM_ARCH == 6 +/* Only ARMv6: */ +#define CP15_DCCIALL p15, 0, r0, c7, c14, 0 /* Data cache clean and invalidate all */ +#endif +#define CP15_DCCIMVAC(rr) p15, 0, rr, c7, c14, 1 /* Data cache clean and invalidate by MVA PoC */ +#define CP15_DCCISW(rr) p15, 0, rr, c7, c14, 2 /* Data cache clean and invalidate by set/way */ + +/* + * CP15 C8 registers + */ +#if __ARM_ARCH >= 7 && defined(SMP) +/* From ARMv7: */ +#define CP15_TLBIALLIS p15, 0, r0, c8, c3, 0 /* Invalidate entire unified TLB IS */ +#define CP15_TLBIMVAIS(rr) p15, 0, rr, c8, c3, 1 /* Invalidate unified TLB by MVA IS */ +#define CP15_TLBIASIDIS(rr) p15, 0, rr, c8, c3, 2 /* Invalidate unified TLB by ASID IS */ +#define CP15_TLBIMVAAIS(rr) p15, 0, rr, c8, c3, 3 /* Invalidate unified TLB by MVA, all ASID IS */ +#endif + +#define CP15_TLBIALL p15, 0, r0, c8, c7, 0 /* Invalidate entire unified TLB */ +#define CP15_TLBIMVA(rr) p15, 0, rr, c8, c7, 1 /* Invalidate unified TLB by MVA */ +#define CP15_TLBIASID(rr) p15, 0, rr, c8, c7, 2 /* Invalidate unified TLB by ASID */ + +#define CP15_TLBIALLH(rr) p15, 4, rr, c8, c7, 0 /* Invalidate Entire Hyp Unified TLB */ + +/* From ARMv6: */ +#define CP15_TLBIMVAA(rr) p15, 0, rr, c8, c7, 3 /* Invalidate unified TLB by MVA, all ASID */ + +/* + * CP15 C9 registers + */ +#if __ARM_ARCH == 6 && defined(CPU_ARM1176) +#define CP15_PMUSERENR(rr) p15, 0, rr, c15, c9, 0 /* Access Validation Control Register */ +#define CP15_PMCR(rr) p15, 0, rr, c15, c12, 0 /* Performance Monitor Control Register */ +#define CP15_PMCCNTR(rr) p15, 0, rr, c15, c12, 1 /* PM Cycle Count Register */ +#else +#define CP15_L2CTLR(rr) p15, 1, rr, c9, c0, 2 /* L2 Control Register */ +#define CP15_PMCR(rr) p15, 0, rr, c9, c12, 0 /* Performance Monitor Control Register */ +#define CP15_PMCNTENSET(rr) p15, 0, rr, c9, c12, 1 /* PM Count Enable Set Register */ +#define CP15_PMCNTENCLR(rr) p15, 0, rr, c9, c12, 2 /* PM Count Enable Clear Register */ +#define CP15_PMOVSR(rr) p15, 0, rr, c9, c12, 3 /* PM Overflow Flag Status Register */ +#define CP15_PMSWINC(rr) p15, 0, rr, c9, c12, 4 /* PM Software Increment Register */ +#define CP15_PMSELR(rr) p15, 0, rr, c9, c12, 5 /* PM Event Counter Selection Register */ +#define CP15_PMCCNTR(rr) p15, 0, rr, c9, c13, 0 /* PM Cycle Count Register */ +#define CP15_PMXEVTYPER(rr) p15, 0, rr, c9, c13, 1 /* PM Event Type Select Register */ +#define CP15_PMXEVCNTRR(rr) p15, 0, rr, c9, c13, 2 /* PM Event Count Register */ +#define CP15_PMUSERENR(rr) p15, 0, rr, c9, c14, 0 /* PM User Enable Register */ +#define CP15_PMINTENSET(rr) p15, 0, rr, c9, c14, 1 /* PM Interrupt Enable Set Register */ +#define CP15_PMINTENCLR(rr) p15, 0, rr, c9, c14, 2 /* PM Interrupt Enable Clear Register */ +#endif + +/* + * CP15 C10 registers + */ +/* Without LPAE this is PRRR, with LPAE it's MAIR0 */ +#define CP15_PRRR(rr) p15, 0, rr, c10, c2, 0 /* Primary Region Remap Register */ +#define CP15_MAIR0(rr) p15, 0, rr, c10, c2, 0 /* Memory Attribute Indirection Register 0 */ +/* Without LPAE this is NMRR, with LPAE it's MAIR1 */ +#define CP15_NMRR(rr) p15, 0, rr, c10, c2, 1 /* Normal Memory Remap Register */ +#define CP15_MAIR1(rr) p15, 0, rr, c10, c2, 1 /* Memory Attribute Indirection Register 1 */ + +#define CP15_AMAIR0(rr) p15, 0, rr, c10, c3, 0 /* Auxiliary Memory Attribute Indirection Register 0 */ +#define CP15_AMAIR1(rr) p15, 0, rr, c10, c3, 1 /* Auxiliary Memory Attribute Indirection Register 1 */ + +#define CP15_HMAIR0(rr) p15, 4, rr, c10, c2, 0 /* Hyp Memory Attribute Indirection Register 0 */ +#define CP15_HMAIR1(rr) p15, 4, rr, c10, c2, 1 /* Hyp Memory Attribute Indirection Register 1 */ + +/* + * CP15 C12 registers + */ +#define CP15_VBAR(rr) p15, 0, rr, c12, c0, 0 /* Vector Base Address Register */ +#define CP15_MVBAR(rr) p15, 0, rr, c12, c0, 1 /* Monitor Vector Base Address Register */ + +#define CP15_ISR(rr) p15, 0, rr, c12, c1, 0 /* Interrupt Status Register */ +#define CP15_HVBAR(rr) p15, 4, rr, c12, c0, 0 /* Hyp Vector Base Address Register*/ + +/* + * CP15 C13 registers + */ +#define CP15_FCSEIDR(rr) p15, 0, rr, c13, c0, 0 /* FCSE Process ID Register */ +#define CP15_CONTEXTIDR(rr) p15, 0, rr, c13, c0, 1 /* Context ID Register */ +#define CP15_TPIDRURW(rr) p15, 0, rr, c13, c0, 2 /* User Read/Write Thread ID Register */ +#define CP15_TPIDRURO(rr) p15, 0, rr, c13, c0, 3 /* User Read-Only Thread ID Register */ +#define CP15_TPIDRPRW(rr) p15, 0, rr, c13, c0, 4 /* PL1 only Thread ID Register */ +#define CP15_HTPIDR(rr) p15, 4, rr, c13, c0, 2 /* Hyp Software Thread ID Register */ + +/* + * CP15 C14 registers + * These are the Generic Timer registers and may be unallocated on some SoCs. + * Only use these when you know the Generic Timer is available. + */ +#define CP15_CNTFRQ(rr) p15, 0, rr, c14, c0, 0 /* Counter Frequency Register */ +#define CP15_CNTKCTL(rr) p15, 0, rr, c14, c1, 0 /* Timer PL1 Control Register */ +#define CP15_CNTP_TVAL(rr) p15, 0, rr, c14, c2, 0 /* PL1 Physical Timer Value Register */ +#define CP15_CNTP_CTL(rr) p15, 0, rr, c14, c2, 1 /* PL1 Physical Timer Control Register */ +#define CP15_CNTV_TVAL(rr) p15, 0, rr, c14, c3, 0 /* Virtual Timer Value Register */ +#define CP15_CNTV_CTL(rr) p15, 0, rr, c14, c3, 1 /* Virtual Timer Control Register */ +#define CP15_CNTHCTL(rr) p15, 4, rr, c14, c1, 0 /* Timer PL2 Control Register */ +#define CP15_CNTHP_TVAL(rr) p15, 4, rr, c14, c2, 0 /* PL2 Physical Timer Value Register */ +#define CP15_CNTHP_CTL(rr) p15, 4, rr, c14, c2, 1 /* PL2 Physical Timer Control Register */ +/* 64-bit registers for use with mcrr/mrrc */ +#define CP15_CNTPCT(rq, rr) p15, 0, rq, rr, c14 /* Physical Count Register */ +#define CP15_CNTVCT(rq, rr) p15, 1, rq, rr, c14 /* Virtual Count Register */ +#define CP15_CNTP_CVAL(rq, rr) p15, 2, rq, rr, c14 /* PL1 Physical Timer Compare Value Register */ +#define CP15_CNTV_CVAL(rq, rr) p15, 3, rq, rr, c14 /* Virtual Timer Compare Value Register */ +#define CP15_CNTVOFF(rq, rr) p15, 4, rq, rr, c14 /* Virtual Offset Register */ +#define CP15_CNTHP_CVAL(rq, rr) p15, 6, rq, rr, c14 /* PL2 Physical Timer Compare Value Register */ + +#define CP15_VTTBR(rq, rr) p15, 6, rq, rr, c2 /* Virtualization Translation Table Base Register */ +#define CP15_HTTBR(rq, rr) p15, 4, rq, rr, c2 /* Hyp Translation Table Base Register */ +#define CP15_TTBR0_2(rq, rr) p15, 0, rq, rr, c2 /* Translation Table Base Register 0 */ +#define CP15_TTBR1_2(rq, rr) p15, 1, rq, rr, c2 /* Translation Table Base Register 1 */ +#define CP15_PAR_2(rq, rr) p15, 0, rq, rr, c7 /* Physical Address Register */ + +/* + * CP15 C15 registers + */ +#define CP15_CBAR(rr) p15, 4, rr, c15, c0, 0 /* Configuration Base Address Register */ + +#endif /* !MACHINE_SYSREG_H */ diff --git a/sys/arm/include/trap.h b/sys/arm/include/trap.h new file mode 100644 index 000000000000..ae1c571255f5 --- /dev/null +++ b/sys/arm/include/trap.h @@ -0,0 +1,11 @@ +/* $NetBSD: trap.h,v 1.1 2001/02/23 03:48:19 ichiro Exp $ */ +/* $FreeBSD$ */ + +#ifndef _MACHINE_TRAP_H_ +#define _MACHINE_TRAP_H_ +#define GDB_BREAKPOINT 0xe6000011 +#define GDB5_BREAKPOINT 0xe7ffdefe +#define PTRACE_BREAKPOINT 0xe7fffff0 +#define KERNEL_BREAKPOINT 0xe7ffffff +#define FBT_BREAKPOINT 0xe7f000f0 +#endif /* _MACHINE_TRAP_H_ */ diff --git a/sys/arm/include/ucontext.h b/sys/arm/include/ucontext.h new file mode 100644 index 000000000000..2fdc5b68230b --- /dev/null +++ b/sys/arm/include/ucontext.h @@ -0,0 +1,89 @@ +/* $NetBSD: mcontext.h,v 1.4 2003/10/08 22:43:01 thorpej Exp $ */ + +/*- + * SPDX-License-Identifier: BSD-2-Clause-NetBSD + * + * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Klaus Klein and by Jason R. Thorpe of Wasabi Systems, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_MCONTEXT_H_ +#define _MACHINE_MCONTEXT_H_ +/* + * General register state + */ +#define _NGREG 17 +typedef unsigned int __greg_t; +typedef __greg_t __gregset_t[_NGREG]; + +#define _REG_R0 0 +#define _REG_R1 1 +#define _REG_R2 2 +#define _REG_R3 3 +#define _REG_R4 4 +#define _REG_R5 5 +#define _REG_R6 6 +#define _REG_R7 7 +#define _REG_R8 8 +#define _REG_R9 9 +#define _REG_R10 10 +#define _REG_R11 11 +#define _REG_R12 12 +#define _REG_R13 13 +#define _REG_R14 14 +#define _REG_R15 15 +#define _REG_CPSR 16 +/* Convenience synonyms */ +#define _REG_FP _REG_R11 +#define _REG_SP _REG_R13 +#define _REG_LR _REG_R14 +#define _REG_PC _REG_R15 + +/* + * Floating point register state + */ +typedef struct { + __uint64_t mcv_reg[32]; + __uint32_t mcv_fpscr; +} mcontext_vfp_t; + +typedef struct { + __gregset_t __gregs; + + /* + * Originally, rest of this structure was named __fpu, 35 * 4 bytes + * long, never accessed from kernel. + */ + __size_t mc_vfp_size; + void *mc_vfp_ptr; + unsigned int mc_spare[33]; +} mcontext_t; + +#define UC_ +#endif /* !_MACHINE_MCONTEXT_H_ */ diff --git a/sys/arm/include/undefined.h b/sys/arm/include/undefined.h new file mode 100644 index 000000000000..139448be4c0e --- /dev/null +++ b/sys/arm/include/undefined.h @@ -0,0 +1,93 @@ +/* $NetBSD: undefined.h,v 1.4 2001/12/20 01:20:23 thorpej Exp $ */ + +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (c) 1995-1996 Mark Brinicombe. + * Copyright (c) 1995 Brini. + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Brini. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * RiscBSD kernel project + * + * undefined.h + * + * Undefined instruction types, symbols and prototypes + * + * Created : 08/02/95 + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_UNDEFINED_H_ +#define _MACHINE_UNDEFINED_H_ +#ifdef _KERNEL + +#include <sys/queue.h> + +struct trapframe; + +typedef int (*undef_handler_t) (unsigned int, unsigned int, struct trapframe *, int); + +#define FP_COPROC 1 +#define FP_COPROC2 2 +#define MAX_COPROCS 16 + +/* Prototypes for undefined.c */ + +void *install_coproc_handler (int, undef_handler_t); +void remove_coproc_handler (void *); +void undefined_init (void); + +/* + * XXX Stuff below here is for use before malloc() is available. Most code + * shouldn't use it. + */ + +struct undefined_handler { + LIST_ENTRY(undefined_handler) uh_link; + undef_handler_t uh_handler; +}; + +/* + * Handlers installed using install_coproc_handler_static shouldn't be + * removed. + */ +void install_coproc_handler_static (int, struct undefined_handler *); + +/* Calls up to undefined.c from trap handlers */ +void undefinedinstruction(struct trapframe *); + +#endif + +/* End of undefined.h */ + +#endif /* _MACHINE_UNDEFINED_H_ */ diff --git a/sys/arm/include/utrap.h b/sys/arm/include/utrap.h new file mode 100644 index 000000000000..b261d87d566f --- /dev/null +++ b/sys/arm/include/utrap.h @@ -0,0 +1,112 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2001 Jake Burkholder. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_UTRAP_H_ +#define _MACHINE_UTRAP_H_ + +#define UT_INSTRUCTION_EXCEPTION 1 +#define UT_INSTRUCTION_ERROR 2 +#define UT_INSTRUCTION_PROTECTION 3 +#define UT_ILLTRAP_INSTRUCTION 4 +#define UT_ILLEGAL_INSTRUCTION 5 +#define UT_PRIVILEGED_OPCODE 6 +#define UT_FP_DISABLED 7 +#define UT_FP_EXCEPTION_IEEE_754 8 +#define UT_FP_EXCEPTION_OTHER 9 +#define UT_TAG_OFERFLOW 10 +#define UT_DIVISION_BY_ZERO 11 +#define UT_DATA_EXCEPTION 12 +#define UT_DATA_ERROR 13 +#define UT_DATA_PROTECTION 14 +#define UT_MEM_ADDRESS_NOT_ALIGNED 15 +#define UT_PRIVILEGED_ACTION 16 +#define UT_ASYNC_DATA_ERROR 17 +#define UT_TRAP_INSTRUCTION_16 18 +#define UT_TRAP_INSTRUCTION_17 19 +#define UT_TRAP_INSTRUCTION_18 20 +#define UT_TRAP_INSTRUCTION_19 21 +#define UT_TRAP_INSTRUCTION_20 22 +#define UT_TRAP_INSTRUCTION_21 23 +#define UT_TRAP_INSTRUCTION_22 24 +#define UT_TRAP_INSTRUCTION_23 25 +#define UT_TRAP_INSTRUCTION_24 26 +#define UT_TRAP_INSTRUCTION_25 27 +#define UT_TRAP_INSTRUCTION_26 28 +#define UT_TRAP_INSTRUCTION_27 29 +#define UT_TRAP_INSTRUCTION_28 30 +#define UT_TRAP_INSTRUCTION_29 31 +#define UT_TRAP_INSTRUCTION_30 32 +#define UT_TRAP_INSTRUCTION_31 33 +#define UT_INSTRUCTION_MISS 34 +#define UT_DATA_MISS 35 +#define UT_MAX 36 + +#define ST_SUNOS_SYSCALL 0 +#define ST_BREAKPOINT 1 +#define ST_DIVISION_BY_ZERO 2 +#define ST_FLUSH_WINDOWS 3 /* XXX implement! */ +#define ST_CLEAN_WINDOW 4 +#define ST_RANGE_CHECK 5 +#define ST_FIX_ALIGNMENT 6 +#define ST_INTEGER_OVERFLOW 7 +/* 8 is 32-bit ABI syscall (old solaris syscall?) */ +#define ST_BSD_SYSCALL 9 +#define ST_FP_RESTORE 10 +/* 11-15 are available */ +/* 16 is linux 32 bit syscall (but supposed to be reserved, grr) */ +/* 17 is old linux 64 bit syscall (but supposed to be reserved, grr) */ +/* 16-31 are reserved for user applications (utraps) */ +#define ST_GETCC 32 /* XXX implement! */ +#define ST_SETCC 33 /* XXX implement! */ +#define ST_GETPSR 34 /* XXX implement! */ +#define ST_SETPSR 35 /* XXX implement! */ +/* 36-63 are available */ +#define ST_SOLARIS_SYSCALL 64 +#define ST_SYSCALL 65 +#define ST_SYSCALL32 66 +/* 67 is reserved to OS source licensee */ +/* 68 is return from deferred trap (not supported) */ +/* 69-95 are reserved to SPARC international */ +/* 96-108 are available */ +/* 109 is linux 64 bit syscall */ +/* 110 is linux 64 bit getcontext (?) */ +/* 111 is linux 64 bit setcontext (?) */ +/* 112-255 are available */ + +#define UTH_NOCHANGE (-1) + +#ifndef __ASM__ + +typedef int utrap_entry_t; +typedef void *utrap_handler_t; + +#endif + +#endif diff --git a/sys/arm/include/vdso.h b/sys/arm/include/vdso.h new file mode 100644 index 000000000000..8d805bba0d88 --- /dev/null +++ b/sys/arm/include/vdso.h @@ -0,0 +1,39 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright 2012 Konstantin Belousov <kib@FreeBSD.ORG>. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _ARM_VDSO_H +#define _ARM_VDSO_H + +#define VDSO_TIMEHANDS_MD \ + uint32_t th_physical; \ + uint32_t th_res[7]; + +#define VDSO_TH_ALGO_ARM_GENTIM VDSO_TH_ALGO_1 + +#endif diff --git a/sys/arm/include/vfp.h b/sys/arm/include/vfp.h new file mode 100644 index 000000000000..b9cc6efb9589 --- /dev/null +++ b/sys/arm/include/vfp.h @@ -0,0 +1,160 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2012 Mark Tinguely + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * $FreeBSD$ + */ + +#ifndef _MACHINE__VFP_H_ +#define _MACHINE__VFP_H_ + +/* fpsid, fpscr, fpexc are defined in the newer gas */ +#define VFPSID cr0 +#define VFPSCR cr1 +#define VMVFR1 cr6 +#define VMVFR0 cr7 +#define VFPEXC cr8 +#define VFPINST cr9 /* vfp 1 and 2 except instruction */ +#define VFPINST2 cr10 /* vfp 2? */ + +/* VFPSID */ +#define VFPSID_IMPLEMENTOR_OFF 24 +#define VFPSID_IMPLEMENTOR_MASK (0xff000000) +#define VFPSID_HARDSOFT_IMP (0x00800000) +#define VFPSID_SINGLE_PREC 20 /* version 1 and 2 */ +#define VFPSID_SUBVERSION_OFF 16 +#define VFPSID_SUBVERSION2_MASK (0x000f0000) /* version 1 and 2 */ +#define VFPSID_SUBVERSION3_MASK (0x007f0000) /* version 3 */ +#define VFP_ARCH1 0x0 +#define VFP_ARCH2 0x1 +#define VFP_ARCH3 0x2 +#define VFPSID_PARTNUMBER_OFF 8 +#define VFPSID_PARTNUMBER_MASK (0x0000ff00) +#define VFPSID_VARIANT_OFF 4 +#define VFPSID_VARIANT_MASK (0x000000f0) +#define VFPSID_REVISION_MASK 0x0f + +/* VFPSCR */ +#define VFPSCR_CC_N (0x80000000) /* comparison less than */ +#define VFPSCR_CC_Z (0x40000000) /* comparison equal */ +#define VFPSCR_CC_C (0x20000000) /* comparison = > unordered */ +#define VFPSCR_CC_V (0x10000000) /* comparison unordered */ +#define VFPSCR_QC (0x08000000) /* saturation cululative */ +#define VFPSCR_DN (0x02000000) /* default NaN enable */ +#define VFPSCR_FZ (0x01000000) /* flush to zero enabled */ + +#define VFPSCR_RMODE_OFF 22 /* rounding mode offset */ +#define VFPSCR_RMODE_MASK (0x00c00000) /* rounding mode mask */ +#define VFPSCR_RMODE_RN (0x00000000) /* round nearest */ +#define VFPSCR_RMODE_RPI (0x00400000) /* round to plus infinity */ +#define VFPSCR_RMODE_RNI (0x00800000) /* round to neg infinity */ +#define VFPSCR_RMODE_RM (0x00c00000) /* round to zero */ + +#define VFPSCR_STRIDE_OFF 20 /* vector stride -1 */ +#define VFPSCR_STRIDE_MASK (0x00300000) +#define VFPSCR_LEN_OFF 16 /* vector length -1 */ +#define VFPSCR_LEN_MASK (0x00070000) +#define VFPSCR_IDE (0x00008000) /* input subnormal exc enable */ +#define VFPSCR_IXE (0x00001000) /* inexact exception enable */ +#define VFPSCR_UFE (0x00000800) /* underflow exception enable */ +#define VFPSCR_OFE (0x00000400) /* overflow exception enable */ +#define VFPSCR_DNZ (0x00000200) /* div by zero exception en */ +#define VFPSCR_IOE (0x00000100) /* invalid op exec enable */ +#define VFPSCR_IDC (0x00000080) /* input subnormal cumul */ +#define VFPSCR_IXC (0x00000010) /* Inexact cumulative flag */ +#define VFPSCR_UFC (0x00000008) /* underflow cumulative flag */ +#define VFPSCR_OFC (0x00000004) /* overflow cumulative flag */ +#define VFPSCR_DZC (0x00000002) /* division by zero flag */ +#define VFPSCR_IOC (0x00000001) /* invalid operation cumul */ + +/* VFPEXC */ +#define VFPEXC_EX (0x80000000) /* exception v1 v2 */ +#define VFPEXC_EN (0x40000000) /* vfp enable */ +#define VFPEXC_DEX (0x20000000) /* Synchronous exception */ +#define VFPEXC_FP2V (0x10000000) /* FPINST2 valid */ +#define VFPEXC_INV (0x00000080) /* Input exception */ +#define VFPEXC_UFC (0x00000008) /* Underflow exception */ +#define VFPEXC_OFC (0x00000004) /* Overflow exception */ +#define VFPEXC_IOC (0x00000001) /* Invlaid operation */ + +/* version 3 registers */ +/* VMVFR0 */ +#define VMVFR0_RM_OFF 28 +#define VMVFR0_RM_MASK (0xf0000000) /* VFP rounding modes */ + +#define VMVFR0_SV_OFF 24 +#define VMVFR0_SV_MASK (0x0f000000) /* VFP short vector supp */ +#define VMVFR0_SR_OFF 20 +#define VMVFR0_SR (0x00f00000) /* VFP hw sqrt supp */ +#define VMVFR0_D_OFF 16 +#define VMVFR0_D_MASK (0x000f0000) /* VFP divide supp */ +#define VMVFR0_TE_OFF 12 +#define VMVFR0_TE_MASK (0x0000f000) /* VFP trap exception supp */ +#define VMVFR0_DP_OFF 8 +#define VMVFR0_DP_MASK (0x00000f00) /* VFP double prec support */ +#define VMVFR0_SP_OFF 4 +#define VMVFR0_SP_MASK (0x000000f0) /* VFP single prec support */ +#define VMVFR0_RB_MASK (0x0000000f) /* VFP 64 bit media support */ + +/* VMVFR1 */ +#define VMVFR1_FMAC_OFF 28 +#define VMVFR1_FMAC_MASK (0xf0000000) /* Neon FMAC support */ +#define VMVFR1_VFP_HP_OFF 24 +#define VMVFR1_VFP_HP_MASK (0x0f000000) /* VFP half prec support */ +#define VMVFR1_HP_OFF 20 +#define VMVFR1_HP_MASK (0x00f00000) /* Neon half prec support */ +#define VMVFR1_SP_OFF 16 +#define VMVFR1_SP_MASK (0x000f0000) /* Neon single prec support */ +#define VMVFR1_I_OFF 12 +#define VMVFR1_I_MASK (0x0000f000) /* Neon integer support */ +#define VMVFR1_LS_OFF 8 +#define VMVFR1_LS_MASK (0x00000f00) /* Neon ld/st instr support */ +#define VMVFR1_DN_OFF 4 +#define VMVFR1_DN_MASK (0x000000f0) /* Neon prop NaN support */ +#define VMVFR1_FZ_MASK (0x0000000f) /* Neon denormal arith supp */ + +#define COPROC10 (0x3 << 20) +#define COPROC11 (0x3 << 22) + +#ifndef LOCORE +struct vfp_state { + uint64_t reg[32]; + uint32_t fpscr; + uint32_t fpexec; + uint32_t fpinst; + uint32_t fpinst2; +}; + +#ifdef _KERNEL +void get_vfpcontext(struct thread *, mcontext_vfp_t *); +void set_vfpcontext(struct thread *, mcontext_vfp_t *); +void vfp_init(void); +void vfp_store(struct vfp_state *, boolean_t); +void vfp_discard(struct thread *); +#endif /* _KERNEL */ +#endif /* LOCORE */ + +#endif diff --git a/sys/arm/include/vm.h b/sys/arm/include/vm.h new file mode 100644 index 000000000000..b9f72fe9a5f7 --- /dev/null +++ b/sys/arm/include/vm.h @@ -0,0 +1,48 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2009 Alan L. Cox <alc@cs.rice.edu> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_VM_H_ +#define _MACHINE_VM_H_ + +#define VM_MEMATTR_WB_WA ((vm_memattr_t)0) +#define VM_MEMATTR_NOCACHE ((vm_memattr_t)1) +#define VM_MEMATTR_DEVICE ((vm_memattr_t)2) +#define VM_MEMATTR_SO ((vm_memattr_t)3) +#define VM_MEMATTR_WRITE_THROUGH ((vm_memattr_t)4) + +#define VM_MEMATTR_DEFAULT VM_MEMATTR_WB_WA +#define VM_MEMATTR_UNCACHEABLE VM_MEMATTR_SO /* misused by DMA */ +#ifdef _KERNEL +/* Don't export aliased VM_MEMATTR to userland */ +#define VM_MEMATTR_WRITE_COMBINING VM_MEMATTR_WRITE_THROUGH /* for DRM */ +#define VM_MEMATTR_WRITE_BACK VM_MEMATTR_WB_WA /* for DRM */ +#endif + +#endif /* !_MACHINE_VM_H_ */ diff --git a/sys/arm/include/vmparam.h b/sys/arm/include/vmparam.h new file mode 100644 index 000000000000..75c61fff803a --- /dev/null +++ b/sys/arm/include/vmparam.h @@ -0,0 +1,206 @@ +/* $NetBSD: vmparam.h,v 1.26 2003/08/07 16:27:47 agc Exp $ */ + +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 1988 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_VMPARAM_H_ +#define _MACHINE_VMPARAM_H_ + +/* + * Machine dependent constants for ARM. + */ + +/* + * Virtual memory related constants, all in bytes + */ +#ifndef MAXTSIZ +#define MAXTSIZ (256UL*1024*1024) /* max text size */ +#endif +#ifndef DFLDSIZ +#define DFLDSIZ (128UL*1024*1024) /* initial data size limit */ +#endif +#ifndef MAXDSIZ +#define MAXDSIZ (512UL*1024*1024) /* max data size */ +#endif +#ifndef DFLSSIZ +#define DFLSSIZ (4UL*1024*1024) /* initial stack size limit */ +#endif +#ifndef MAXSSIZ +#define MAXSSIZ (64UL*1024*1024) /* max stack size */ +#endif +#ifndef SGROWSIZ +#define SGROWSIZ (128UL*1024) /* amount to grow stack */ +#endif + +/* + * Address space constants + */ + +/* + * The line between user space and kernel space + * Mappings >= KERNEL_BASE are constant across all processes + */ +#ifndef KERNBASE +#define KERNBASE 0xc0000000 +#endif + +/* + * The virtual address the kernel is linked to run at. For armv4/5 platforms + * the low-order 30 bits of this must match the low-order bits of the physical + * address the kernel is loaded at, so the value is most often provided as a + * kernel config option in the std.platform file. For armv6/7 the kernel can + * be loaded at any 2MB boundary, and KERNVIRTADDR can also be set to any 2MB + * boundary. It is typically overridden in the std.platform file only when + * KERNBASE is also set to a lower address to provide more KVA. + */ +#ifndef KERNVIRTADDR +#define KERNVIRTADDR 0xc0000000 +#endif + +/* + * max number of non-contig chunks of physical RAM you can have + */ + +#define VM_PHYSSEG_MAX 32 + +/* + * The physical address space may be sparsely populated on some ARM systems. + */ +#define VM_PHYSSEG_SPARSE + +/* + * Create one free page pool. Since the ARM kernel virtual address + * space does not include a mapping onto the machine's entire physical + * memory, VM_FREEPOOL_DIRECT is defined as an alias for the default + * pool, VM_FREEPOOL_DEFAULT. + */ +#define VM_NFREEPOOL 1 +#define VM_FREEPOOL_DEFAULT 0 +#define VM_FREEPOOL_DIRECT 0 + +/* + * We need just one free list: DEFAULT. + */ +#define VM_NFREELIST 1 +#define VM_FREELIST_DEFAULT 0 + +/* + * The largest allocation size is 1MB. + */ +#define VM_NFREEORDER 9 + +/* + * Enable superpage reservations: 1 level. + */ +#ifndef VM_NRESERVLEVEL +#define VM_NRESERVLEVEL 1 +#endif + +/* + * Level 0 reservations consist of 256 pages. + */ +#ifndef VM_LEVEL_0_ORDER +#define VM_LEVEL_0_ORDER 8 +#endif + +#define VM_MIN_ADDRESS (0x00001000) +#ifndef VM_MAXUSER_ADDRESS +#define VM_MAXUSER_ADDRESS (KERNBASE - 0x00400000) /* !!! PT2MAP_SIZE */ +#endif +#define VM_MAX_ADDRESS VM_MAXUSER_ADDRESS + +#define SHAREDPAGE (VM_MAXUSER_ADDRESS - PAGE_SIZE) +#define USRSTACK SHAREDPAGE + +/* initial pagein size of beginning of executable file */ +#ifndef VM_INITIAL_PAGEIN +#define VM_INITIAL_PAGEIN 16 +#endif + +#ifndef VM_MIN_KERNEL_ADDRESS +#define VM_MIN_KERNEL_ADDRESS KERNBASE +#endif + +#define VM_MAX_KERNEL_ADDRESS (vm_max_kernel_address) + +/* + * How many physical pages per kmem arena virtual page. + */ +#ifndef VM_KMEM_SIZE_SCALE +#define VM_KMEM_SIZE_SCALE (3) +#endif + +/* + * Optional floor (in bytes) on the size of the kmem arena. + */ +#ifndef VM_KMEM_SIZE_MIN +#define VM_KMEM_SIZE_MIN (12 * 1024 * 1024) +#endif + +/* + * Optional ceiling (in bytes) on the size of the kmem arena: 40% of the + * kernel map. + */ +#ifndef VM_KMEM_SIZE_MAX +#define VM_KMEM_SIZE_MAX ((vm_max_kernel_address - \ + VM_MIN_KERNEL_ADDRESS + 1) * 2 / 5) +#endif + +extern vm_offset_t vm_max_kernel_address; + +#define ZERO_REGION_SIZE (64 * 1024) /* 64KB */ + +#ifndef VM_MAX_AUTOTUNE_MAXUSERS +#define VM_MAX_AUTOTUNE_MAXUSERS 384 +#endif + +#define SFBUF +#define SFBUF_MAP + +#define PMAP_HAS_DMAP 0 +#define PHYS_TO_DMAP(x) ({ panic("No direct map exists"); 0; }) +#define DMAP_TO_PHYS(x) ({ panic("No direct map exists"); 0; }) + +#define DEVMAP_MAX_VADDR ARM_VECTORS_HIGH + +/* + * No non-transparent large page support in the pmap. + */ +#define PMAP_HAS_LARGEPAGES 0 + +/* + * Need a page dump array for minidump. + */ +#define MINIDUMP_PAGE_TRACKING 1 + +#endif /* _MACHINE_VMPARAM_H_ */ |