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Diffstat (limited to 'sys/contrib/device-tree/Bindings/arm/qcom,coresight-tpdm.yaml')
-rw-r--r-- | sys/contrib/device-tree/Bindings/arm/qcom,coresight-tpdm.yaml | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/sys/contrib/device-tree/Bindings/arm/qcom,coresight-tpdm.yaml b/sys/contrib/device-tree/Bindings/arm/qcom,coresight-tpdm.yaml index 5c08342664ea..61ddc3b5b247 100644 --- a/sys/contrib/device-tree/Bindings/arm/qcom,coresight-tpdm.yaml +++ b/sys/contrib/device-tree/Bindings/arm/qcom,coresight-tpdm.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause # Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. %YAML 1.2 --- @@ -44,6 +44,23 @@ properties: minItems: 1 maxItems: 2 + qcom,dsb-element-size: + description: + Specifies the DSB(Discrete Single Bit) element size supported by + the monitor. The associated aggregator will read this size before it + is enabled. DSB element size currently only supports 32-bit and 64-bit. + $ref: /schemas/types.yaml#/definitions/uint8 + enum: [32, 64] + + qcom,dsb-msrs-num: + description: + Specifies the number of DSB(Discrete Single Bit) MSR(mux select register) + registers supported by the monitor. If this property is not configured + or set to 0, it means this DSB TPDM doesn't support MSR. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 32 + clocks: maxItems: 1 @@ -77,6 +94,9 @@ examples: compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0684c000 0x1000>; + qcom,dsb-element-size = /bits/ 8 <32>; + qcom,dsb-msrs-num = <16>; + clocks = <&aoss_qmp>; clock-names = "apb_pclk"; |