diff options
Diffstat (limited to 'sys/contrib/device-tree/Bindings/display/mediatek/mediatek,dsi.txt')
| -rw-r--r-- | sys/contrib/device-tree/Bindings/display/mediatek/mediatek,dsi.txt | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/sys/contrib/device-tree/Bindings/display/mediatek/mediatek,dsi.txt b/sys/contrib/device-tree/Bindings/display/mediatek/mediatek,dsi.txt index 8238a86686be..36b01458f45c 100644 --- a/sys/contrib/device-tree/Bindings/display/mediatek/mediatek,dsi.txt +++ b/sys/contrib/device-tree/Bindings/display/mediatek/mediatek,dsi.txt @@ -7,7 +7,7 @@ channel output. Required properties: - compatible: "mediatek,<chip>-dsi" -- the supported chips are mt2701, mt7623, mt8173 and mt8183. +- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - interrupts: The interrupt signal from the function block. - clocks: device clocks @@ -19,6 +19,11 @@ Required properties: Documentation/devicetree/bindings/graph.txt. This port should be connected to the input port of an attached DSI panel or DSI-to-eDP encoder chip. +Optional properties: +- resets: list of phandle + reset specifier pair, as described in [1]. + +[1] Documentation/devicetree/bindings/reset/reset.txt + MIPI TX Configuration Module ============================ @@ -45,6 +50,7 @@ dsi0: dsi@1401b000 { clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>, <&mipi_tx0>; clock-names = "engine", "digital", "hs"; + resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; phys = <&mipi_tx0>; phy-names = "dphy"; |