diff options
Diffstat (limited to 'sys/contrib/device-tree/src/arm64/renesas/rzg2l-smarc.dtsi')
| -rw-r--r-- | sys/contrib/device-tree/src/arm64/renesas/rzg2l-smarc.dtsi | 43 |
1 files changed, 40 insertions, 3 deletions
diff --git a/sys/contrib/device-tree/src/arm64/renesas/rzg2l-smarc.dtsi b/sys/contrib/device-tree/src/arm64/renesas/rzg2l-smarc.dtsi index 2a158a954b2f..37807f1bda4d 100644 --- a/sys/contrib/device-tree/src/arm64/renesas/rzg2l-smarc.dtsi +++ b/sys/contrib/device-tree/src/arm64/renesas/rzg2l-smarc.dtsi @@ -8,9 +8,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> -/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */ -#define PMOD1_SER0 1 - / { aliases { serial1 = &scif2; @@ -113,7 +110,47 @@ #sound-dai-cells = <0>; reg = <0x1a>; }; + + versa3: clock-generator@68 { + compatible = "renesas,5p35023"; + reg = <0x68>; + #clock-cells = <1>; + clocks = <&x1>; + + renesas,settings = [ + 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf + 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6 + 80 b0 45 c4 95 + ]; + + assigned-clocks = <&versa3 0>, <&versa3 1>, + <&versa3 2>, <&versa3 3>, + <&versa3 4>, <&versa3 5>; + assigned-clock-rates = <24000000>, <11289600>, + <11289600>, <12000000>, + <25000000>, <12288000>; + }; +}; + +#if PMOD_MTU3 +&mtu3 { + pinctrl-0 = <&mtu3_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +#if MTU3_COUNTER_Z_PHASE_SIGNAL +/* SDHI cd pin is muxed with counter Z phase signal */ +&sdhi1 { + status = "disabled"; +}; +#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */ + +&spi1 { + status = "disabled"; }; +#endif /* PMOD_MTU3 */ /* * To enable SCIF2 (SER0) on PMOD1 (CN7) |