diff options
Diffstat (limited to 'sys')
-rw-r--r-- | sys/mips/include/md_var.h | 1 | ||||
-rw-r--r-- | sys/mips/mips/cpu.c | 21 | ||||
-rw-r--r-- | sys/mips/mips/mp_machdep.c | 3 |
3 files changed, 22 insertions, 3 deletions
diff --git a/sys/mips/include/md_var.h b/sys/mips/include/md_var.h index 0150e6acd354..cca58e5cd1b3 100644 --- a/sys/mips/include/md_var.h +++ b/sys/mips/include/md_var.h @@ -72,6 +72,7 @@ void mips_wait(void); void mips_vector_init(void); void mips_cpu_init(void); +void mips_hwrena_init(void); void mips_pcpu0_init(void); void mips_proc0_init(void); void mips_postboot_fixup(void); diff --git a/sys/mips/mips/cpu.c b/sys/mips/mips/cpu.c index 0f8583dbd40a..37acb0d5effa 100644 --- a/sys/mips/mips/cpu.c +++ b/sys/mips/mips/cpu.c @@ -192,10 +192,11 @@ mips_get_identity(struct mips_cpuinfo *cpuinfo) /* Check to see if UserLocal register is implemented. */ if (cfg3 & MIPS_CONFIG3_ULR) { - /* UserLocal register is implemented, enable it. */ + /* + * UserLocal register is implemented, enable it later in + * mips_hwrena_init. + */ cpuinfo->userlocal_reg = true; - tmp = mips_rd_hwrena(); - mips_wr_hwrena(tmp | MIPS_HWRENA_UL); } else { /* * UserLocal register is not implemented. Patch @@ -328,10 +329,24 @@ mips_get_identity(struct mips_cpuinfo *cpuinfo) } void +mips_hwrena_init(void) +{ + uint32_t reg; + + reg = mips_rd_hwrena(); + + if (cpuinfo.userlocal_reg) + reg |= MIPS_HWRENA_UL; + + mips_wr_hwrena(reg); +} + +void mips_cpu_init(void) { platform_cpu_init(); mips_get_identity(&cpuinfo); + mips_hwrena_init(); num_tlbentries = cpuinfo.tlb_nentries; mips_wr_wired(0); tlb_invalidate_all(); diff --git a/sys/mips/mips/mp_machdep.c b/sys/mips/mips/mp_machdep.c index 1a5a023db381..0bf0981ecaae 100644 --- a/sys/mips/mips/mp_machdep.c +++ b/sys/mips/mips/mp_machdep.c @@ -54,6 +54,7 @@ __FBSDID("$FreeBSD$"); #include <machine/intr_machdep.h> #include <machine/cache.h> #include <machine/tlb.h> +#include <machine/md_var.h> struct pcb stoppcbs[MAXCPU]; @@ -278,6 +279,8 @@ void smp_init_secondary(u_int32_t cpuid) { + mips_hwrena_init(); + /* TLB */ mips_wr_wired(0); tlb_invalidate_all(); |