diff options
Diffstat (limited to 'test/CodeGen/AMDGPU/clamp-omod-special-case.mir')
| -rw-r--r-- | test/CodeGen/AMDGPU/clamp-omod-special-case.mir | 46 |
1 files changed, 7 insertions, 39 deletions
diff --git a/test/CodeGen/AMDGPU/clamp-omod-special-case.mir b/test/CodeGen/AMDGPU/clamp-omod-special-case.mir index 6ecf75c1acec..90fba0342090 100644 --- a/test/CodeGen/AMDGPU/clamp-omod-special-case.mir +++ b/test/CodeGen/AMDGPU/clamp-omod-special-case.mir @@ -1,36 +1,4 @@ # RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s ---- | - define amdgpu_ps void @v_max_self_clamp_not_set_f32() #0 { - ret void - } - - define amdgpu_ps void @v_clamp_omod_already_set_f32() #0 { - ret void - } - - define amdgpu_ps void @v_omod_mul_omod_already_set_f32() #0 { - ret void - } - - define amdgpu_ps void @v_omod_mul_clamp_already_set_f32() #0 { - ret void - } - - define amdgpu_ps void @v_omod_add_omod_already_set_f32() #0 { - ret void - } - - define amdgpu_ps void @v_omod_add_clamp_already_set_f32() #0 { - ret void - } - - define amdgpu_ps void @v_max_reg_imm_f32() #0 { - ret void - } - - attributes #0 = { nounwind "no-signed-zeros-fp-math"="false" } - -... --- # GCN-LABEL: name: v_max_self_clamp_not_set_f32 # GCN: %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec @@ -70,7 +38,7 @@ liveins: - { reg: '%sgpr0_sgpr1', virtual-reg: '%0' } - { reg: '%vgpr0', virtual-reg: '%3' } body: | - bb.0 (%ir-block.0): + bb.0: liveins: %sgpr0_sgpr1, %vgpr0 %3 = COPY %vgpr0 @@ -132,7 +100,7 @@ liveins: - { reg: '%sgpr0_sgpr1', virtual-reg: '%0' } - { reg: '%vgpr0', virtual-reg: '%3' } body: | - bb.0 (%ir-block.0): + bb.0: liveins: %sgpr0_sgpr1, %vgpr0 %3 = COPY %vgpr0 @@ -195,7 +163,7 @@ liveins: - { reg: '%sgpr0_sgpr1', virtual-reg: '%0' } - { reg: '%vgpr0', virtual-reg: '%3' } body: | - bb.0 (%ir-block.0): + bb.0: liveins: %sgpr0_sgpr1, %vgpr0 %3 = COPY %vgpr0 @@ -260,7 +228,7 @@ liveins: - { reg: '%sgpr0_sgpr1', virtual-reg: '%0' } - { reg: '%vgpr0', virtual-reg: '%3' } body: | - bb.0 (%ir-block.0): + bb.0: liveins: %sgpr0_sgpr1, %vgpr0 %3 = COPY %vgpr0 @@ -337,7 +305,7 @@ liveins: - { reg: '%sgpr0_sgpr1', virtual-reg: '%0' } - { reg: '%vgpr0', virtual-reg: '%3' } body: | - bb.0 (%ir-block.0): + bb.0: liveins: %sgpr0_sgpr1, %vgpr0 %3 = COPY %vgpr0 @@ -402,7 +370,7 @@ liveins: - { reg: '%sgpr0_sgpr1', virtual-reg: '%0' } - { reg: '%vgpr0', virtual-reg: '%3' } body: | - bb.0 (%ir-block.0): + bb.0: liveins: %sgpr0_sgpr1, %vgpr0 %3 = COPY %vgpr0 @@ -435,7 +403,7 @@ registers: - { id: 0, class: vgpr_32 } - { id: 1, class: vgpr_32 } body: | - bb.0 (%ir-block.0): + bb.0: liveins: %vgpr0 %0 = COPY %vgpr0 |