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-rw-r--r--test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir100
-rw-r--r--test/CodeGen/ARM/GlobalISel/arm-legalizer.mir52
-rw-r--r--test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir66
-rw-r--r--test/CodeGen/ARM/avoid-cpsr-rmw.ll4
-rw-r--r--test/CodeGen/ARM/su-addsub-overflow.ll135
-rw-r--r--test/CodeGen/ARM/usat.ll214
6 files changed, 569 insertions, 2 deletions
diff --git a/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir b/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
index 7c2666e3680f..8b9b83f6d0e7 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
@@ -6,6 +6,7 @@
define void @test_trunc_and_zext_s16() { ret void }
define void @test_trunc_and_anyext_s8() { ret void }
define void @test_trunc_and_anyext_s16() { ret void }
+ define void @test_trunc_s64() #0 { ret void }
define void @test_add_s32() { ret void }
define void @test_add_fold_imm_s32() { ret void }
@@ -46,6 +47,10 @@
define void @test_gep() { ret void }
define void @test_constant_imm() { ret void }
define void @test_constant_cimm() { ret void }
+ define void @test_pointer_constant() { ret void }
+
+ define void @test_inttoptr_s32() { ret void }
+ define void @test_ptrtoint_s32() { ret void }
define void @test_select_s32() { ret void }
define void @test_select_ptr() { ret void }
@@ -241,6 +246,36 @@ body: |
; CHECK: BX_RET 14, %noreg, implicit %r0
...
---
+name: test_trunc_s64
+# CHECK-LABEL: name: test_trunc_s64
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: fprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+body: |
+ bb.0:
+ liveins: %r0, %d0
+
+ %0(s64) = COPY %d0
+ ; CHECK: [[VREG:%[0-9]+]]:dpr = COPY %d0
+
+ %2(p0) = COPY %r0
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY %r0
+
+ %1(s32) = G_TRUNC %0(s64)
+ ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr, [[UNINTERESTING:%[0-9]+]]:gpr = VMOVRRD [[VREG]]
+
+ G_STORE %1(s32), %2 :: (store 4)
+ ; CHECK: STRi12 [[VREGTRUNC]], [[PTR]], 0, 14, %noreg
+
+ BX_RET 14, %noreg
+ ; CHECK: BX_RET 14, %noreg
+...
+---
name: test_add_s32
# CHECK-LABEL: name: test_add_s32
legalized: true
@@ -1075,6 +1110,71 @@ body: |
BX_RET 14, %noreg, implicit %r0
...
---
+name: test_pointer_constant
+# CHECK-LABEL: name: test_pointer_constant
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+body: |
+ bb.0:
+ %0(p0) = G_CONSTANT i32 0
+ ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
+
+ %r0 = COPY %0(p0)
+ BX_RET 14, %noreg, implicit %r0
+...
+---
+name: test_inttoptr_s32
+# CHECK-LABEL: name: test_inttoptr_s32
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+body: |
+ bb.0:
+ liveins: %r0
+
+ %0(s32) = COPY %r0
+ %1(p0) = G_INTTOPTR %0(s32)
+ ; CHECK: [[INT:%[0-9]+]]:gpr = COPY %r0
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY [[INT]]
+
+ %r0 = COPY %1(p0)
+ ; CHECK: %r0 = COPY [[PTR]]
+
+ BX_RET 14, %noreg, implicit %r0
+...
+---
+name: test_ptrtoint_s32
+# CHECK-LABEL: name: test_ptrtoint_s32
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+body: |
+ bb.0:
+ liveins: %r0
+
+ %0(p0) = COPY %r0
+ %1(s32) = G_PTRTOINT %0(p0)
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY %r0
+ ; CHECK: [[INT:%[0-9]+]]:gpr = COPY [[PTR]]
+
+ %r0 = COPY %1(s32)
+ ; CHECK: %r0 = COPY [[INT]]
+
+ BX_RET 14, %noreg, implicit %r0
+...
+---
name: test_select_s32
# CHECK-LABEL: name: test_select_s32
legalized: true
diff --git a/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir b/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
index e3e206cf76e9..204434e981b4 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
@@ -3,6 +3,9 @@
define void @test_sext_s8() { ret void }
define void @test_zext_s16() { ret void }
+ define void @test_inttoptr_s32() { ret void }
+ define void @test_ptrtoint_s32() { ret void }
+
define void @test_add_s8() { ret void }
define void @test_add_s16() { ret void }
define void @test_add_s32() { ret void }
@@ -101,6 +104,50 @@ body: |
BX_RET 14, %noreg, implicit %r0
...
---
+name: test_inttoptr_s32
+# CHECK-LABEL: name: test_inttoptr_s32
+legalized: false
+# CHECK: legalized: true
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %r0
+
+ %0(s32) = COPY %r0
+ %1(p0) = G_INTTOPTR %0(s32)
+ ; G_INTTOPTR with s32 is legal, so we should find it unchanged in the output
+ ; CHECK: {{%[0-9]+}}:_(p0) = G_INTTOPTR {{%[0-9]+}}
+ %r0 = COPY %1(p0)
+ BX_RET 14, %noreg, implicit %r0
+...
+---
+name: test_ptrtoint_s32
+# CHECK-LABEL: name: test_ptrtoint_s32
+legalized: false
+# CHECK: legalized: true
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %r0
+
+ %0(p0) = COPY %r0
+ %1(s32) = G_PTRTOINT %0(p0)
+ ; G_PTRTOINT with s32 is legal, so we should find it unchanged in the output
+ ; CHECK: {{%[0-9]+}}:_(s32) = G_PTRTOINT {{%[0-9]+}}
+ %r0 = COPY %1(s32)
+ BX_RET 14, %noreg, implicit %r0
+...
+---
name: test_add_s8
# CHECK-LABEL: name: test_add_s8
legalized: false
@@ -826,6 +873,7 @@ registers:
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
+ - { id: 5, class: _ }
body: |
bb.0:
liveins: %r0
@@ -856,6 +904,10 @@ body: |
; CHECK: {{%[0-9]+}}:_(s1) = G_TRUNC [[EXT]](s32)
; CHECK-NOT: G_CONSTANT i1
+ %5(p0) = G_CONSTANT 0
+ G_STORE %5(p0), %4(p0) :: (store 4)
+ ; CHECK: {{%[0-9]+}}:_(p0) = G_CONSTANT 0
+
%r0 = COPY %0(s32)
BX_RET 14, %noreg, implicit %r0
...
diff --git a/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir b/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
index 044740e33a2d..175333626f97 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
@@ -24,6 +24,9 @@
define void @test_constants() { ret void }
+ define void @test_inttoptr_s32() { ret void }
+ define void @test_ptrtoint_s32() { ret void }
+
@a_global = global float 1.0
define void @test_globals() { ret void }
@@ -31,6 +34,7 @@
define void @test_anyext_s16_32() { ret void }
define void @test_trunc_s32_16() { ret void }
+ define void @test_trunc_s64_32() #0 { ret void }
define void @test_icmp_eq_s32() { ret void }
define void @test_fcmp_one_s32() #0 { ret void }
@@ -496,6 +500,44 @@ body: |
BX_RET 14, %noreg, implicit %r0
...
---
+name: test_inttoptr_s32
+# CHECK-LABEL: name: test_inttoptr_s32
+legalized: true
+regBankSelected: false
+selected: false
+# CHECK: registers:
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ %0(s32) = COPY %r0
+ %1(p0) = G_INTTOPTR %0(s32)
+ %r0 = COPY %1(p0)
+ BX_RET 14, %noreg, implicit %r0
+...
+---
+name: test_ptrtoint_s32
+# CHECK-LABEL: name: test_ptrtoint_s32
+legalized: true
+regBankSelected: false
+selected: false
+# CHECK: registers:
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ %0(p0) = COPY %r0
+ %1(s32) = G_PTRTOINT %0(p0)
+ %r0 = COPY %1(s32)
+ BX_RET 14, %noreg, implicit %r0
+...
+---
name: test_globals
# CHECK-LABEL: name: test_globals
legalized: true
@@ -584,6 +626,30 @@ body: |
BX_RET 14, %noreg
...
---
+name: test_trunc_s64_32
+# CHECK-LABEL: name: test_trunc_s64_32
+legalized: true
+regBankSelected: false
+selected: false
+# CHECK: registers:
+# CHECK: - { id: 0, class: fprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+# CHECK: - { id: 2, class: gprb, preferred-register: '' }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0:
+ liveins: %r0, %d0
+
+ %0(s64) = COPY %d0
+ %2(p0) = COPY %r0
+ %1(s32) = G_TRUNC %0(s64)
+ G_STORE %1(s32), %2 :: (store 4)
+ BX_RET 14, %noreg
+...
+---
name: test_icmp_eq_s32
# CHECK-LABEL: name: test_icmp_eq_s32
legalized: true
diff --git a/test/CodeGen/ARM/avoid-cpsr-rmw.ll b/test/CodeGen/ARM/avoid-cpsr-rmw.ll
index 78d3ebf371a4..9373c5d44210 100644
--- a/test/CodeGen/ARM/avoid-cpsr-rmw.ll
+++ b/test/CodeGen/ARM/avoid-cpsr-rmw.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-CORTEX
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=swift | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-SWIFT
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 -simplifycfg-sink-common=false | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-CORTEX
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=swift -simplifycfg-sink-common=false | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-SWIFT
; Avoid some 's' 16-bit instruction which partially update CPSR (and add false
; dependency) when it isn't dependent on last CPSR defining instruction.
; rdar://8928208
diff --git a/test/CodeGen/ARM/su-addsub-overflow.ll b/test/CodeGen/ARM/su-addsub-overflow.ll
new file mode 100644
index 000000000000..eef531282033
--- /dev/null
+++ b/test/CodeGen/ARM/su-addsub-overflow.ll
@@ -0,0 +1,135 @@
+; RUN: llc < %s -mtriple=arm-eabi -mcpu=generic | FileCheck %s
+
+define i32 @sadd(i32 %a, i32 %b) local_unnamed_addr #0 {
+; CHECK-LABEL: sadd:
+; CHECK: mov r[[R0:[0-9]+]], r0
+; CHECK-NEXT: add r[[R1:[0-9]+]], r[[R0]], r1
+; CHECK-NEXT: cmp r[[R1]], r[[R0]]
+; CHECK-NEXT: movvc pc, lr
+entry:
+ %0 = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
+ %1 = extractvalue { i32, i1 } %0, 1
+ br i1 %1, label %trap, label %cont
+
+trap:
+ tail call void @llvm.trap() #2
+ unreachable
+
+cont:
+ %2 = extractvalue { i32, i1 } %0, 0
+ ret i32 %2
+
+}
+
+define i32 @uadd(i32 %a, i32 %b) local_unnamed_addr #0 {
+; CHECK-LABEL: uadd:
+; CHECK: mov r[[R0:[0-9]+]], r0
+; CHECK-NEXT: adds r[[R1:[0-9]+]], r[[R0]], r1
+; CHECK-NEXT: cmp r[[R1]], r[[R0]]
+; CHECK-NEXT: movhs pc, lr
+entry:
+ %0 = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
+ %1 = extractvalue { i32, i1 } %0, 1
+ br i1 %1, label %trap, label %cont
+
+trap:
+ tail call void @llvm.trap() #2
+ unreachable
+
+cont:
+ %2 = extractvalue { i32, i1 } %0, 0
+ ret i32 %2
+
+}
+
+define i32 @ssub(i32 %a, i32 %b) local_unnamed_addr #0 {
+; CHECK-LABEL: ssub:
+; CHECK: cmp r0, r1
+; CHECK-NEXT: subvc r0, r0, r1
+; CHECK-NEXT: movvc pc, lr
+entry:
+ %0 = tail call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %a, i32 %b)
+ %1 = extractvalue { i32, i1 } %0, 1
+ br i1 %1, label %trap, label %cont
+
+trap:
+ tail call void @llvm.trap() #2
+ unreachable
+
+cont:
+ %2 = extractvalue { i32, i1 } %0, 0
+ ret i32 %2
+
+}
+
+define i32 @usub(i32 %a, i32 %b) local_unnamed_addr #0 {
+; CHECK-LABEL: usub:
+; CHECK: mov r[[R0:[0-9]+]], r0
+; CHECK-NEXT: subs r[[R1:[0-9]+]], r[[R0]], r1
+; CHECK-NEXT: cmp r[[R0]], r1
+; CHECK-NEXT: movhs pc, lr
+entry:
+ %0 = tail call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
+ %1 = extractvalue { i32, i1 } %0, 1
+ br i1 %1, label %trap, label %cont
+
+trap:
+ tail call void @llvm.trap() #2
+ unreachable
+
+cont:
+ %2 = extractvalue { i32, i1 } %0, 0
+ ret i32 %2
+
+}
+
+define void @sum(i32* %a, i32* %b, i32 %n) local_unnamed_addr #0 {
+; CHECK-LABEL: sum:
+; CHECK: ldr [[R0:r[0-9]+]],
+; CHECK-NEXT: ldr [[R1:r[0-9]+|lr]],
+; CHECK-NEXT: add [[R2:r[0-9]+]], [[R1]], [[R0]]
+; CHECK-NEXT: cmp [[R2]], [[R1]]
+; CHECK-NEXT: strvc [[R2]],
+; CHECK-NEXT: addvc
+; CHECK-NEXT: cmpvc
+; CHECK-NEXT: bvs
+entry:
+ %cmp7 = icmp eq i32 %n, 0
+ br i1 %cmp7, label %for.cond.cleanup, label %for.body
+
+for.cond.cleanup:
+ ret void
+
+for.body:
+ %i.08 = phi i32 [ %7, %cont2 ], [ 0, %entry ]
+ %arrayidx = getelementptr inbounds i32, i32* %b, i32 %i.08
+ %0 = load i32, i32* %arrayidx, align 4
+ %arrayidx1 = getelementptr inbounds i32, i32* %a, i32 %i.08
+ %1 = load i32, i32* %arrayidx1, align 4
+ %2 = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %1, i32 %0)
+ %3 = extractvalue { i32, i1 } %2, 1
+ br i1 %3, label %trap, label %cont
+
+trap:
+ tail call void @llvm.trap() #2
+ unreachable
+
+cont:
+ %4 = extractvalue { i32, i1 } %2, 0
+ store i32 %4, i32* %arrayidx1, align 4
+ %5 = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %i.08, i32 1)
+ %6 = extractvalue { i32, i1 } %5, 1
+ br i1 %6, label %trap, label %cont2
+
+cont2:
+ %7 = extractvalue { i32, i1 } %5, 0
+ %cmp = icmp eq i32 %7, %n
+ br i1 %cmp, label %for.cond.cleanup, label %for.body
+
+}
+
+declare void @llvm.trap() #2
+declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) #1
+declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) #1
+declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32) #1
+declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) #1
diff --git a/test/CodeGen/ARM/usat.ll b/test/CodeGen/ARM/usat.ll
new file mode 100644
index 000000000000..8f19d11ef7bb
--- /dev/null
+++ b/test/CodeGen/ARM/usat.ll
@@ -0,0 +1,214 @@
+; RUN: llc -mtriple=armv4t-eabi %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=V4T
+; RUN: llc -mtriple=armv6-eabi %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=V6
+; RUN: llc -mtriple=armv6t2-eabi %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=V6T2
+
+; Check for several conditions that should result in USAT.
+; For example, the base test is equivalent to
+; x < 0 ? 0 : (x > k ? k : x) in C. All patterns that bound x
+; to the interval [0, k] where k + 1 is a power of 2 can be
+; transformed into USAT. At the end there are some tests
+; checking that conditionals are not transformed if they don't
+; match the right pattern.
+
+;
+; Base tests with different bit widths
+;
+
+; x < 0 ? 0 : (x > k ? k : x)
+; 32-bit base test
+define i32 @unsigned_sat_base_32bit(i32 %x) #0 {
+; CHECK-LABEL: unsigned_sat_base_32bit:
+; V6: usat r0, #23, r0
+; V6T2: usat r0, #23, r0
+; V4T-NOT: usat
+entry:
+ %cmpLow = icmp slt i32 %x, 0
+ %cmpUp = icmp sgt i32 %x, 8388607
+ %saturateUp = select i1 %cmpUp, i32 8388607, i32 %x
+ %saturateLow = select i1 %cmpLow, i32 0, i32 %saturateUp
+ ret i32 %saturateLow
+}
+
+; x < 0 ? 0 : (x > k ? k : x)
+; 16-bit base test
+define i16 @unsigned_sat_base_16bit(i16 %x) #0 {
+; CHECK-LABEL: unsigned_sat_base_16bit:
+; V6: usat r0, #11, r0
+; V6T2: usat r0, #11, r0
+; V4T-NOT: usat
+entry:
+ %cmpLow = icmp slt i16 %x, 0
+ %cmpUp = icmp sgt i16 %x, 2047
+ %saturateUp = select i1 %cmpUp, i16 2047, i16 %x
+ %saturateLow = select i1 %cmpLow, i16 0, i16 %saturateUp
+ ret i16 %saturateLow
+}
+
+; x < 0 ? 0 : (x > k ? k : x)
+; 8-bit base test
+define i8 @unsigned_sat_base_8bit(i8 %x) #0 {
+; CHECK-LABEL: unsigned_sat_base_8bit:
+; V6: usat r0, #5, r0
+; V6T2: usat r0, #5, r0
+; V4T-NOT: usat
+entry:
+ %cmpLow = icmp slt i8 %x, 0
+ %cmpUp = icmp sgt i8 %x, 31
+ %saturateUp = select i1 %cmpUp, i8 31, i8 %x
+ %saturateLow = select i1 %cmpLow, i8 0, i8 %saturateUp
+ ret i8 %saturateLow
+}
+
+;
+; Tests where the conditionals that check for upper and lower bounds,
+; or the < and > operators, are arranged in different ways. Only some
+; of the possible combinations that lead to USAT are tested.
+;
+; x < 0 ? 0 : (x < k ? x : k)
+define i32 @unsigned_sat_lower_upper_1(i32 %x) #0 {
+; CHECK-LABEL: unsigned_sat_lower_upper_1:
+; V6: usat r0, #23, r0
+; V6T2: usat r0, #23, r0
+; V4T-NOT: usat
+entry:
+ %cmpLow = icmp slt i32 %x, 0
+ %cmpUp = icmp slt i32 %x, 8388607
+ %saturateUp = select i1 %cmpUp, i32 %x, i32 8388607
+ %saturateLow = select i1 %cmpLow, i32 0, i32 %saturateUp
+ ret i32 %saturateLow
+}
+
+; x > 0 ? (x > k ? k : x) : 0
+define i32 @unsigned_sat_lower_upper_2(i32 %x) #0 {
+; CHECK-LABEL: unsigned_sat_lower_upper_2:
+; V6: usat r0, #23, r0
+; V6T2: usat r0, #23, r0
+; V4T-NOT: usat
+entry:
+ %cmpLow = icmp sgt i32 %x, 0
+ %cmpUp = icmp sgt i32 %x, 8388607
+ %saturateUp = select i1 %cmpUp, i32 8388607, i32 %x
+ %saturateLow = select i1 %cmpLow, i32 %saturateUp, i32 0
+ ret i32 %saturateLow
+}
+
+; x < k ? (x < 0 ? 0 : x) : k
+define i32 @unsigned_sat_upper_lower_1(i32 %x) #0 {
+; CHECK-LABEL: unsigned_sat_upper_lower_1:
+; V6: usat r0, #23, r0
+; V6T2: usat r0, #23, r0
+; V4T-NOT: usat
+entry:
+ %cmpUp = icmp slt i32 %x, 8388607
+ %cmpLow = icmp slt i32 %x, 0
+ %saturateLow = select i1 %cmpLow, i32 0, i32 %x
+ %saturateUp = select i1 %cmpUp, i32 %saturateLow, i32 8388607
+ ret i32 %saturateUp
+}
+
+; x > k ? k : (x < 0 ? 0 : x)
+define i32 @unsigned_sat_upper_lower_2(i32 %x) #0 {
+; CHECK-LABEL: unsigned_sat_upper_lower_2:
+; V6: usat r0, #23, r0
+; V6T2: usat r0, #23, r0
+; V4T-NOT: usat
+entry:
+ %cmpUp = icmp sgt i32 %x, 8388607
+ %cmpLow = icmp slt i32 %x, 0
+ %saturateLow = select i1 %cmpLow, i32 0, i32 %x
+ %saturateUp = select i1 %cmpUp, i32 8388607, i32 %saturateLow
+ ret i32 %saturateUp
+}
+
+; k < x ? k : (x > 0 ? x : 0)
+define i32 @unsigned_sat_upper_lower_3(i32 %x) #0 {
+; CHECK-LABEL: unsigned_sat_upper_lower_3:
+; V6: usat r0, #23, r0
+; V6T2: usat r0, #23, r0
+; V4T-NOT: usat
+entry:
+ %cmpUp = icmp slt i32 8388607, %x
+ %cmpLow = icmp sgt i32 %x, 0
+ %saturateLow = select i1 %cmpLow, i32 %x, i32 0
+ %saturateUp = select i1 %cmpUp, i32 8388607, i32 %saturateLow
+ ret i32 %saturateUp
+}
+
+;
+; The following tests check for patterns that should not transform
+; into USAT but are similar enough that could confuse the selector.
+;
+; x > k ? k : (x > 0 ? 0 : x)
+; First condition upper-saturates, second doesn't lower-saturate.
+define i32 @no_unsigned_sat_missing_lower(i32 %x) #0 {
+; CHECK-LABEL: no_unsigned_sat_missing_lower
+; CHECK-NOT: usat
+entry:
+ %cmpUp = icmp sgt i32 %x, 8388607
+ %cmpLow = icmp sgt i32 %x, 0
+ %saturateLow = select i1 %cmpLow, i32 0, i32 %x
+ %saturateUp = select i1 %cmpUp, i32 8388607, i32 %saturateLow
+ ret i32 %saturateUp
+}
+
+; x < k ? k : (x < 0 ? 0 : x)
+; Second condition lower-saturates, first doesn't upper-saturate.
+define i32 @no_unsigned_sat_missing_upper(i32 %x) #0 {
+; CHECK-LABEL: no_unsigned_sat_missing_upper:
+; CHECK-NOT: usat
+entry:
+ %cmpUp = icmp slt i32 %x, 8388607
+ %cmpLow = icmp slt i32 %x, 0
+ %saturateLow = select i1 %cmpLow, i32 0, i32 %x
+ %saturateUp = select i1 %cmpUp, i32 8388607, i32 %saturateLow
+ ret i32 %saturateUp
+}
+
+; Lower constant is different in the select and in the compare
+define i32 @no_unsigned_sat_incorrect_constant(i32 %x) #0 {
+; CHECK-LABEL: no_unsigned_sat_incorrect_constant:
+; CHECK-NOT: usat
+entry:
+ %cmpUp = icmp sgt i32 %x, 8388607
+ %cmpLow = icmp slt i32 %x, 0
+ %saturateLow = select i1 %cmpLow, i32 -1, i32 %x
+ %saturateUp = select i1 %cmpUp, i32 8388607, i32 %saturateLow
+ ret i32 %saturateUp
+}
+
+; The interval is not [0, k]
+define i32 @no_unsigned_sat_incorrect_interval(i32 %x) #0 {
+; CHECK-LABEL: no_unsigned_sat_incorrect_interval:
+; CHECK-NOT: usat
+entry:
+ %cmpUp = icmp sgt i32 %x, 8388607
+ %cmpLow = icmp slt i32 %x, -4
+ %saturateLow = select i1 %cmpLow, i32 -4, i32 %x
+ %saturateUp = select i1 %cmpUp, i32 8388607, i32 %saturateLow
+ ret i32 %saturateUp
+}
+
+; The returned value (y) is not the same as the tested value (x).
+define i32 @no_unsigned_sat_incorrect_return(i32 %x, i32 %y) #0 {
+; CHECK-LABEL: no_unsigned_sat_incorrect_return:
+; CHECK-NOT: usat
+entry:
+ %cmpUp = icmp sgt i32 %x, 8388607
+ %cmpLow = icmp slt i32 %x, 0
+ %saturateLow = select i1 %cmpLow, i32 0, i32 %y
+ %saturateUp = select i1 %cmpUp, i32 8388607, i32 %saturateLow
+ ret i32 %saturateUp
+}
+
+; One of the values in a compare (y) is not the same as the rest
+; of the compare and select values (x).
+define i32 @no_unsigned_sat_incorrect_compare(i32 %x, i32 %y) #0 {
+; CHECK-LABEL: no_unsigned_sat_incorrect_compare:
+; CHECK-NOT: usat
+entry:
+ %cmpUp = icmp sgt i32 %x, 8388607
+ %cmpLow = icmp slt i32 %y, 0
+ %saturateLow = select i1 %cmpLow, i32 0, i32 %x
+ %saturateUp = select i1 %cmpUp, i32 8388607, i32 %saturateLow
+ ret i32 %saturateUp
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-30 14:53:22 +0000