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-rw-r--r--test/CodeGen/CellSPU/mul-with-overflow.ll15
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diff --git a/test/CodeGen/CellSPU/mul-with-overflow.ll b/test/CodeGen/CellSPU/mul-with-overflow.ll
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index 000000000000..755b99be9cdd
--- /dev/null
+++ b/test/CodeGen/CellSPU/mul-with-overflow.ll
@@ -0,0 +1,15 @@
+; RUN: llvm-as < %s | llc -march=cellspu
+
+declare {i16, i1} @llvm.smul.with.overflow.i16(i16 %a, i16 %b)
+define i1 @a(i16 %x) zeroext nounwind {
+ %res = call {i16, i1} @llvm.smul.with.overflow.i16(i16 %x, i16 3)
+ %obil = extractvalue {i16, i1} %res, 1
+ ret i1 %obil
+}
+
+declare {i16, i1} @llvm.umul.with.overflow.i16(i16 %a, i16 %b)
+define i1 @b(i16 %x) zeroext nounwind {
+ %res = call {i16, i1} @llvm.umul.with.overflow.i16(i16 %x, i16 3)
+ %obil = extractvalue {i16, i1} %res, 1
+ ret i1 %obil
+}