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-rw-r--r--test/CodeGen/Hexagon/intrinsics/xtype_perm.ll71
1 files changed, 37 insertions, 34 deletions
diff --git a/test/CodeGen/Hexagon/intrinsics/xtype_perm.ll b/test/CodeGen/Hexagon/intrinsics/xtype_perm.ll
index 0b761323e31e..3e044e3838de 100644
--- a/test/CodeGen/Hexagon/intrinsics/xtype_perm.ll
+++ b/test/CodeGen/Hexagon/intrinsics/xtype_perm.ll
@@ -1,41 +1,44 @@
; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
+; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s
; Hexagon Programmer's Reference Manual 11.10.6 XTYPE/PERM
+; CHECK-CALL-NOT: call
+
; Saturate
declare i32 @llvm.hexagon.A2.sat(i64)
define i32 @A2_sat(i64 %a) {
%z = call i32 @llvm.hexagon.A2.sat(i64 %a)
ret i32 %z
}
-; CHECK: r0 = sat(r1:0)
+; CHECK: = sat({{.*}})
declare i32 @llvm.hexagon.A2.sath(i32)
define i32 @A2_sath(i32 %a) {
%z = call i32 @llvm.hexagon.A2.sath(i32 %a)
ret i32 %z
}
-; CHECK: r0 = sath(r0)
+; CHECK: = sath({{.*}})
declare i32 @llvm.hexagon.A2.satuh(i32)
define i32 @A2_satuh(i32 %a) {
%z = call i32 @llvm.hexagon.A2.satuh(i32 %a)
ret i32 %z
}
-; CHECK: r0 = satuh(r0)
+; CHECK: = satuh({{.*}})
declare i32 @llvm.hexagon.A2.satub(i32)
define i32 @A2_satub(i32 %a) {
%z = call i32 @llvm.hexagon.A2.satub(i32 %a)
ret i32 %z
}
-; CHECK: r0 = satub(r0)
+; CHECK: = satub({{.*}})
declare i32 @llvm.hexagon.A2.satb(i32)
define i32 @A2_satb(i32 %a) {
%z = call i32 @llvm.hexagon.A2.satb(i32 %a)
ret i32 %z
}
-; CHECK: r0 = satb(r0)
+; CHECK: = satb({{.*}})
; Swizzle bytes
declare i32 @llvm.hexagon.A2.swiz(i32)
@@ -43,7 +46,7 @@ define i32 @A2_swiz(i32 %a) {
%z = call i32 @llvm.hexagon.A2.swiz(i32 %a)
ret i32 %z
}
-; CHECK: r0 = swiz(r0)
+; CHECK: = swiz({{.*}})
; Vector round and pack
declare i32 @llvm.hexagon.S2.vrndpackwh(i64)
@@ -51,14 +54,14 @@ define i32 @S2_vrndpackwh(i64 %a) {
%z = call i32 @llvm.hexagon.S2.vrndpackwh(i64 %a)
ret i32 %z
}
-; CHECK: r0 = vrndwh(r1:0)
+; CHECK: = vrndwh({{.*}})
declare i32 @llvm.hexagon.S2.vrndpackwhs(i64)
define i32 @S2_vrndpackwhs(i64 %a) {
%z = call i32 @llvm.hexagon.S2.vrndpackwhs(i64 %a)
ret i32 %z
}
-; CHECK: r0 = vrndwh(r1:0):sat
+; CHECK: = vrndwh({{.*}}):sat
; Vector saturate and pack
declare i32 @llvm.hexagon.S2.vsathub(i64)
@@ -66,42 +69,42 @@ define i32 @S2_vsathub(i64 %a) {
%z = call i32 @llvm.hexagon.S2.vsathub(i64 %a)
ret i32 %z
}
-; CHECK: r0 = vsathub(r1:0)
+; CHECK: = vsathub({{.*}})
declare i32 @llvm.hexagon.S2.vsatwh(i64)
define i32 @S2_vsatwh(i64 %a) {
%z = call i32 @llvm.hexagon.S2.vsatwh(i64 %a)
ret i32 %z
}
-; CHECK: r0 = vsatwh(r1:0)
+; CHECK: = vsatwh({{.*}})
declare i32 @llvm.hexagon.S2.vsatwuh(i64)
define i32 @S2_vsatwuh(i64 %a) {
%z = call i32 @llvm.hexagon.S2.vsatwuh(i64 %a)
ret i32 %z
}
-; CHECK: r0 = vsatwuh(r1:0)
+; CHECK: = vsatwuh({{.*}})
declare i32 @llvm.hexagon.S2.vsathb(i64)
define i32 @S2_vsathb(i64 %a) {
%z = call i32 @llvm.hexagon.S2.vsathb(i64 %a)
ret i32 %z
}
-; CHECK: r0 = vsathb(r1:0)
+; CHECK: = vsathb({{.*}})
declare i32 @llvm.hexagon.S2.svsathb(i32)
define i32 @S2_svsathb(i32 %a) {
%z = call i32 @llvm.hexagon.S2.svsathb(i32 %a)
ret i32 %z
}
-; CHECK: r0 = vsathb(r0)
+; CHECK: = vsathb({{.*}})
declare i32 @llvm.hexagon.S2.svsathub(i32)
define i32 @S2_svsathub(i32 %a) {
%z = call i32 @llvm.hexagon.S2.svsathub(i32 %a)
ret i32 %z
}
-; CHECK: r0 = vsathub(r0)
+; CHECK: = vsathub({{.*}})
; Vector saturate without pack
declare i64 @llvm.hexagon.S2.vsathub.nopack(i64)
@@ -109,28 +112,28 @@ define i64 @S2_vsathub_nopack(i64 %a) {
%z = call i64 @llvm.hexagon.S2.vsathub.nopack(i64 %a)
ret i64 %z
}
-; CHECK: r1:0 = vsathub(r1:0)
+; CHECK: = vsathub({{.*}})
declare i64 @llvm.hexagon.S2.vsatwuh.nopack(i64)
define i64 @S2_vsatwuh_nopack(i64 %a) {
%z = call i64 @llvm.hexagon.S2.vsatwuh.nopack(i64 %a)
ret i64 %z
}
-; CHECK: r1:0 = vsatwuh(r1:0)
+; CHECK: = vsatwuh({{.*}})
declare i64 @llvm.hexagon.S2.vsatwh.nopack(i64)
define i64 @S2_vsatwh_nopack(i64 %a) {
%z = call i64 @llvm.hexagon.S2.vsatwh.nopack(i64 %a)
ret i64 %z
}
-; CHECK: r1:0 = vsatwh(r1:0)
+; CHECK: = vsatwh({{.*}})
declare i64 @llvm.hexagon.S2.vsathb.nopack(i64)
define i64 @S2_vsathb_nopack(i64 %a) {
%z = call i64 @llvm.hexagon.S2.vsathb.nopack(i64 %a)
ret i64 %z
}
-; CHECK: r1:0 = vsathb(r1:0)
+; CHECK: = vsathb({{.*}})
; Vector shuffle
declare i64 @llvm.hexagon.S2.shuffeb(i64, i64)
@@ -138,28 +141,28 @@ define i64 @S2_shuffeb(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.shuffeb(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: r1:0 = shuffeb(r1:0, r3:2)
+; CHECK: = shuffeb({{.*}}, {{.*}})
declare i64 @llvm.hexagon.S2.shuffob(i64, i64)
define i64 @S2_shuffob(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.shuffob(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: r1:0 = shuffob(r1:0, r3:2)
+; CHECK: = shuffob({{.*}}, {{.*}})
declare i64 @llvm.hexagon.S2.shuffeh(i64, i64)
define i64 @S2_shuffeh(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.shuffeh(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: r1:0 = shuffeh(r1:0, r3:2)
+; CHECK: = shuffeh({{.*}}, {{.*}})
declare i64 @llvm.hexagon.S2.shuffoh(i64, i64)
define i64 @S2_shuffoh(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.shuffoh(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: r1:0 = shuffoh(r1:0, r3:2)
+; CHECK: = shuffoh({{.*}}, {{.*}})
; Vector splat bytes
declare i32 @llvm.hexagon.S2.vsplatrb(i32)
@@ -167,7 +170,7 @@ define i32 @S2_vsplatrb(i32 %a) {
%z = call i32 @llvm.hexagon.S2.vsplatrb(i32 %a)
ret i32 %z
}
-; CHECK: r0 = vsplatb(r0)
+; CHECK: = vsplatb({{.*}})
; Vector splat halfwords
declare i64 @llvm.hexagon.S2.vsplatrh(i32)
@@ -175,7 +178,7 @@ define i64 @S2_vsplatrh(i32 %a) {
%z = call i64 @llvm.hexagon.S2.vsplatrh(i32 %a)
ret i64 %z
}
-; CHECK: = vsplath(r0)
+; CHECK: = vsplath({{.*}})
; Vector splice
declare i64 @llvm.hexagon.S2.vspliceib(i64, i64, i32)
@@ -183,14 +186,14 @@ define i64 @S2_vspliceib(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.vspliceib(i64 %a, i64 %b, i32 0)
ret i64 %z
}
-; CHECK: r1:0 = vspliceb(r1:0, r3:2, #0)
+; CHECK: = vspliceb({{.*}}, {{.*}}, #0)
declare i64 @llvm.hexagon.S2.vsplicerb(i64, i64, i32)
define i64 @S2_vsplicerb(i64 %a, i64 %b, i32 %c) {
%z = call i64 @llvm.hexagon.S2.vsplicerb(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: r1:0 = vspliceb(r1:0, r3:2, p0)
+; CHECK: = vspliceb({{.*}}, {{.*}}, {{.*}})
; Vector sign extend
declare i64 @llvm.hexagon.S2.vsxtbh(i32)
@@ -198,14 +201,14 @@ define i64 @S2_vsxtbh(i32 %a) {
%z = call i64 @llvm.hexagon.S2.vsxtbh(i32 %a)
ret i64 %z
}
-; CHECK: = vsxtbh(r0)
+; CHECK: = vsxtbh({{.*}})
declare i64 @llvm.hexagon.S2.vsxthw(i32)
define i64 @S2_vsxthw(i32 %a) {
%z = call i64 @llvm.hexagon.S2.vsxthw(i32 %a)
ret i64 %z
}
-; CHECK: = vsxthw(r0)
+; CHECK: = vsxthw({{.*}})
; Vector truncate
declare i32 @llvm.hexagon.S2.vtrunohb(i64)
@@ -213,28 +216,28 @@ define i32 @S2_vtrunohb(i64 %a) {
%z = call i32 @llvm.hexagon.S2.vtrunohb(i64 %a)
ret i32 %z
}
-; CHECK: r0 = vtrunohb(r1:0)
+; CHECK: = vtrunohb({{.*}})
declare i32 @llvm.hexagon.S2.vtrunehb(i64)
define i32 @S2_vtrunehb(i64 %a) {
%z = call i32 @llvm.hexagon.S2.vtrunehb(i64 %a)
ret i32 %z
}
-; CHECK: r0 = vtrunehb(r1:0)
+; CHECK: = vtrunehb({{.*}})
declare i64 @llvm.hexagon.S2.vtrunowh(i64, i64)
define i64 @S2_vtrunowh(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.vtrunowh(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: r1:0 = vtrunowh(r1:0, r3:2)
+; CHECK: = vtrunowh({{.*}}, {{.*}})
declare i64 @llvm.hexagon.S2.vtrunewh(i64, i64)
define i64 @S2_vtrunewh(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.vtrunewh(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: r1:0 = vtrunewh(r1:0, r3:2)
+; CHECK: = vtrunewh({{.*}}, {{.*}})
; Vector zero extend
declare i64 @llvm.hexagon.S2.vzxtbh(i32)
@@ -242,11 +245,11 @@ define i64 @S2_vzxtbh(i32 %a) {
%z = call i64 @llvm.hexagon.S2.vzxtbh(i32 %a)
ret i64 %z
}
-; CHECK: = vzxtbh(r0)
+; CHECK: = vzxtbh({{.*}})
declare i64 @llvm.hexagon.S2.vzxthw(i32)
define i64 @S2_vzxthw(i32 %a) {
%z = call i64 @llvm.hexagon.S2.vzxthw(i32 %a)
ret i64 %z
}
-; CHECK: = vzxthw(r0)
+; CHECK: = vzxthw({{.*}})
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-02 04:06:16 +0000