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-rw-r--r--test/CodeGen/Mips/llvm-ir/mul.ll110
1 files changed, 74 insertions, 36 deletions
diff --git a/test/CodeGen/Mips/llvm-ir/mul.ll b/test/CodeGen/Mips/llvm-ir/mul.ll
index a7582805dd74..8d63e496806c 100644
--- a/test/CodeGen/Mips/llvm-ir/mul.ll
+++ b/test/CodeGen/Mips/llvm-ir/mul.ll
@@ -1,27 +1,33 @@
-; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL \
-; RUN: -check-prefix=M2 -check-prefix=GP32
-; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=ALL \
-; RUN: -check-prefix=32R1-R5 -check-prefix=GP32
-; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL \
-; RUN: -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32
-; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=ALL \
-; RUN: -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32
-; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=ALL \
-; RUN: -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32
-; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL \
-; RUN: -check-prefix=32R6 -check-prefix=GP32
-; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefix=ALL \
-; RUN: -check-prefix=M4 -check-prefix=GP64-NOT-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL \
-; RUN: -check-prefix=64R1-R5 -check-prefix=GP64-NOT-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL \
-; RUN: -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s -check-prefix=ALL \
-; RUN: -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s -check-prefix=ALL \
-; RUN: -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL \
-; RUN: -check-prefix=64R6
+; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | \
+; RUN: FileCheck %s -check-prefixes=ALL,M2,GP32
+; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | \
+; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | \
+; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | \
+; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | \
+; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | \
+; RUN: FileCheck %s -check-prefixes=ALL,32R6,GP32
+; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | \
+; RUN: FileCheck %s -check-prefixes=ALL,M4,GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | \
+; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | \
+; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | \
+; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | \
+; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | \
+; RUN: FileCheck %s -check-prefixes=ALL,64R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | \
+; RUN: FileCheck %s -check-prefixes=MM32,MM32R3
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | \
+; RUN: FileCheck %s -check-prefixes=MM32,MM32R6
+; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | \
+; RUN: FileCheck %s -check-prefix=64R6
define signext i1 @mul_i1(i1 signext %a, i1 signext %b) {
entry:
@@ -53,6 +59,10 @@ entry:
; 64R6: sll $[[T0]], $[[T0]], 31
; 64R6: sra $2, $[[T0]], 31
+ ; MM32: mul $[[T0:[0-9]+]], $4, $5
+ ; MM32: sll $[[T0]], $[[T0]], 31
+ ; MM32: sra $2, $[[T0]], 31
+
%r = mul i1 %a, %b
ret i1 %r
}
@@ -90,6 +100,10 @@ entry:
; 64R6: mul $[[T0:[0-9]+]], $4, $5
; 64R6: seb $2, $[[T0]]
+
+ ; MM32: mul $[[T0:[0-9]+]], $4, $5
+ ; MM32: seb $2, $[[T0]]
+
%r = mul i8 %a, %b
ret i8 %r
}
@@ -127,6 +141,10 @@ entry:
; 64R6: mul $[[T0:[0-9]+]], $4, $5
; 64R6: seh $2, $[[T0]]
+
+ ; MM32: mul $[[T0:[0-9]+]], $4, $5
+ ; MM32: seh $2, $[[T0]]
+
%r = mul i16 %a, %b
ret i16 %r
}
@@ -143,6 +161,9 @@ entry:
; 64R1-R5: mul $2, $4, $5
; 64R6: mul $2, $4, $5
+
+ ; MM32: mul $2, $4, $5
+
%r = mul i32 %a, %b
ret i32 %r
}
@@ -169,12 +190,12 @@ entry:
; 32R1-R5: addu $[[T0]], $[[T0]], $[[T2:[0-9]+]]
; 32R1-R5: addu $2, $[[T0]], $[[T1]]
- ; 32R6: mul $[[T0:[0-9]+]], $5, $6
- ; 32R6: muhu $[[T1:[0-9]+]], $5, $7
- ; 32R6: addu $[[T0]], $[[T1]], $[[T0]]
- ; 32R6: mul $[[T2:[0-9]+]], $4, $7
- ; 32R6: addu $2, $[[T0]], $[[T2]]
- ; 32R6: mul $3, $5, $7
+ ; 32R6-DAG: mul $3, $5, $7
+ ; 32R6-DAG: mul $[[T0:[0-9]+]], $4, $7
+ ; 32R6-DAG: mul $[[T1:[0-9]+]], $5, $6
+ ; 32R6: muhu $[[T2:[0-9]+]], $5, $7
+ ; 32R6: addu $[[T1]], $[[T2]], $[[T1]]
+ ; 32R6: addu $2, $[[T1]], $[[T0]]
; M4: dmult $4, $5
; M4: mflo $2
@@ -184,6 +205,21 @@ entry:
; 64R6: dmul $2, $4, $5
+ ; MM32R3: multu $[[T0:[0-9]+]], $7
+ ; MM32R3: mflo $[[T1:[0-9]+]]
+ ; MM32R3: mfhi $[[T2:[0-9]+]]
+ ; MM32R3: mul $[[T3:[0-9]+]], $4, $7
+ ; MM32R3: mul $[[T0]], $[[T0]], $6
+ ; MM32R3: addu16 $[[T2]], $[[T2]], $[[T0]]
+ ; MM32R3: addu16 $2, $[[T2]], $[[T3]]
+
+ ; MM32R6: mul $[[T0:[0-9]+]], $5, $7
+ ; MM32R6: mul $[[T1:[0-9]+]], $4, $7
+ ; MM32R6: mul $[[T2:[0-9]+]], $5, $6
+ ; MM32R6: muhu $[[T3:[0-9]+]], $5, $7
+ ; MM32R6: addu16 $[[T2]], $[[T3]], $[[T2]]
+ ; MM32R6: addu16 $2, $[[T2]], $[[T1]]
+
%r = mul i64 %a, %b
ret i64 %r
}
@@ -204,12 +240,14 @@ entry:
; GP64-NOT-R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
; GP64-NOT-R6: daddu $2, $[[T3:[0-9]+]], $[[T0]]
- ; 64R6: dmul $[[T0:[0-9]+]], $5, $6
- ; 64R6: dmuhu $[[T1:[0-9]+]], $5, $7
- ; 64R6: daddu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
- ; 64R6: dmul $[[T3:[0-9]+]], $4, $7
- ; 64R6: daddu $2, $[[T2]], $[[T3]]
- ; 64R6: dmul $3, $5, $7
+ ; 64R6-DAG: dmul $3, $5, $7
+ ; 64R6-DAG: dmul $[[T0:[0-9]+]], $4, $7
+ ; 64R6-DAG: dmul $[[T1:[0-9]+]], $5, $6
+ ; 64R6: dmuhu $[[T2:[0-9]+]], $5, $7
+ ; 64R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+ ; 64R6: daddu $2, $[[T1]], $[[T0]]
+
+ ; MM32: lw $25, %call16(__multi3)($2)
%r = mul i128 %a, %b
ret i128 %r
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-08 10:23:21 +0000