diff options
Diffstat (limited to 'test/CodeGen/Mips/llvm-ir')
24 files changed, 3678 insertions, 1183 deletions
diff --git a/test/CodeGen/Mips/llvm-ir/add.ll b/test/CodeGen/Mips/llvm-ir/add.ll index 6cccc7df19f9..7a60585d8fbf 100644 --- a/test/CodeGen/Mips/llvm-ir/add.ll +++ b/test/CodeGen/Mips/llvm-ir/add.ll @@ -1,37 +1,51 @@ ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=ALL,NOT-R2-R6,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=ALL,NOT-R2-R6,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=ALL,R2-R6,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=ALL,R2-R6,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=ALL,R2-R6,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=ALL,R2-R6,GP32 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=ALL,R2-R6,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=ALL,R2-R6,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=ALL,R2-R6,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=ALL,R2-R6,GP64 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -O2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -O2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -O2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM64 define signext i1 @add_i1(i1 signext %a, i1 signext %b) { entry: ; ALL-LABEL: add_i1: - ; ALL: addu $[[T0:[0-9]+]], $4, $5 - ; ALL: sll $[[T0]], $[[T0]], 31 - ; ALL: sra $2, $[[T0]], 31 + ; NOT-R2-R6: addu $[[T0:[0-9]+]], $4, $5 + ; NOT-R2-R6: sll $[[T0]], $[[T0]], 31 + ; NOT-R2-R6: sra $2, $[[T0]], 31 + + ; R2-R6: addu $[[T0:[0-9]+]], $4, $5 + ; R2-R6: sll $[[T0]], $[[T0]], 31 + ; R2-R6: sra $2, $[[T0]], 31 + + ; MMR6: addu16 $[[T0:[0-9]+]], $4, $5 + ; MMR6: sll $[[T1:[0-9]+]], $[[T0]], 31 + ; MMR6: sra $2, $[[T1]], 31 %r = add i1 %a, %b ret i1 %r @@ -45,8 +59,11 @@ entry: ; NOT-R2-R6: sll $[[T0]], $[[T0]], 24 ; NOT-R2-R6: sra $2, $[[T0]], 24 - ; R2-R6: addu $[[T0:[0-9]+]], $4, $5 - ; R2-R6: seb $2, $[[T0:[0-9]+]] + ; R2-R6: addu $[[T0:[0-9]+]], $4, $5 + ; R2-R6: seb $2, $[[T0:[0-9]+]] + + ; MMR6: addu16 $[[T0:[0-9]+]], $4, $5 + ; MMR6: seb $2, $[[T0]] %r = add i8 %a, %b ret i8 %r @@ -60,8 +77,11 @@ entry: ; NOT-R2-R6: sll $[[T0]], $[[T0]], 16 ; NOT-R2-R6: sra $2, $[[T0]], 16 - ; R2-R6: addu $[[T0:[0-9]+]], $4, $5 - ; R2-R6: seh $2, $[[T0:[0-9]+]] + ; R2-R6: addu $[[T0:[0-9]+]], $4, $5 + ; R2-R6: seh $2, $[[T0]] + + ; MMR6: addu16 $[[T0:[0-9]+]], $4, $5 + ; MMR6: seh $2, $[[T0]] %r = add i16 %a, %b ret i16 %r @@ -71,7 +91,10 @@ define signext i32 @add_i32(i32 signext %a, i32 signext %b) { entry: ; ALL-LABEL: add_i32: - ; ALL: addu $2, $4, $5 + ; NOT-R2-R6: addu $2, $4, $5 + ; R2-R6: addu $2, $4, $5 + + ; MMR6: addu16 $[[T0:[0-9]+]], $4, $5 %r = add i32 %a, %b ret i32 %r @@ -88,6 +111,13 @@ entry: ; GP64: daddu $2, $4, $5 + ; MM32: addu $3, $5, $7 + ; MM32: sltu $[[T0:[0-9]+]], $3, $7 + ; MM32: addu $[[T1:[0-9]+]], $[[T0]], $6 + ; MM32: addu $2, $4, $[[T1]] + + ; MM64: daddu $2, $4, $5 + %r = add i64 %a, %b ret i64 %r } @@ -102,13 +132,13 @@ entry: ; GP32: lw $[[T3:[0-9]+]], 24($sp) ; GP32: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]] ; GP32: addu $[[T5:[0-9]+]], $6, $[[T4]] - ; GP32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]] + ; GP32: lw $[[T6:[0-9]+]], 16($sp) ; GP32: lw $[[T7:[0-9]+]], 20($sp) - ; GP32: addu $[[T8:[0-9]+]], $[[T6]], $[[T7]] - ; GP32: lw $[[T9:[0-9]+]], 16($sp) + ; GP32: sltu $[[T8:[0-9]+]], $[[T5]], $[[T3]] + ; GP32: addu $[[T9:[0-9]+]], $[[T8]], $[[T7]] ; GP32: addu $3, $5, $[[T8]] ; GP32: sltu $[[T10:[0-9]+]], $3, $[[T7]] - ; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T9]] + ; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T6]] ; GP32: addu $2, $4, $[[T11]] ; GP32: move $4, $[[T5]] ; GP32: move $5, $[[T1]] @@ -118,6 +148,285 @@ entry: ; GP64: daddu $[[T1:[0-9]+]], $[[T0]], $6 ; GP64: daddu $2, $4, $[[T1]] + ; MM32: lw $[[T0:[0-9]+]], 28($sp) + ; MM32: addu $[[T1:[0-9]+]], $7, $[[T0]] + ; MM32: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]] + ; MM32: lw $[[T3:[0-9]+]], 24($sp) + ; MM32: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]] + ; MM32: addu $[[T5:[0-9]+]], $6, $[[T4]] + ; MM32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]] + ; MM32: lw $[[T7:[0-9]+]], 20($sp) + ; MM32: addu $[[T8:[0-9]+]], $[[T6]], $[[T7]] + ; MM32: addu $[[T9:[0-9]+]], $5, $[[T8]] + ; MM32: lw $[[T10:[0-9]+]], 16($sp) + ; MM32: sltu $[[T11:[0-9]+]], $[[T9]], $[[T7]] + ; MM32: addu $[[T12:[0-9]+]], $[[T11]], $[[T10]] + ; MM32: addu $[[T13:[0-9]+]], $4, $[[T12]] + ; MM32: move $4, $[[T5]] + ; MM32: move $5, $[[T1]] + + ; MM64: daddu $3, $5, $7 + ; MM64: sltu $[[T0:[0-9]+]], $3, $7 + ; MM64: daddu $[[T1:[0-9]+]], $[[T0]], $6 + ; MM64: daddu $2, $4, $[[T1]] + %r = add i128 %a, %b ret i128 %r } + +define signext i1 @add_i1_4(i1 signext %a) { +; ALL-LABEL: add_i1_4: + + ; ALL: move $2, $4 + + %r = add i1 4, %a + ret i1 %r +} + +define signext i8 @add_i8_4(i8 signext %a) { +; ALL-LABEL: add_i8_4: + + ; NOT-R2-R6: sll $[[T0:[0-9]+]], $4, 24 + ; NOT-R2-R6: lui $[[T1:[0-9]+]], 1024 + ; NOT-R2-R6: addu $[[T0]], $[[T0]], $[[T1]] + ; NOT-R2-R6: sra $2, $[[T0]], 24 + + ; R2-R6: addiu $[[T0:[0-9]+]], $4, 4 + ; R2-R6: seb $2, $[[T0]] + + ; MM32: addiur2 $[[T0:[0-9]+]], $4, 4 + ; MM32: seb $2, $[[T0]] + + ; MM64: addiur2 $[[T0:[0-9]+]], $4, 4 + ; MM64: seb $2, $[[T0]] + + %r = add i8 4, %a + ret i8 %r +} + +define signext i16 @add_i16_4(i16 signext %a) { +; ALL-LABEL: add_i16_4: + + ; NOT-R2-R6: sll $[[T0:[0-9]+]], $4, 16 + ; NOT-R2-R6: lui $[[T1:[0-9]+]], 4 + ; NOT-R2-R6: addu $[[T0]], $[[T0]], $[[T1]] + ; NOT-R2-R6: sra $2, $[[T0]], 16 + + ; R2-R6: addiu $[[T0:[0-9]+]], $4, 4 + ; R2-R6: seh $2, $[[T0]] + + ; MM32: addiur2 $[[T0:[0-9]+]], $4, 4 + ; MM32: seh $2, $[[T0]] + + ; MM64: addiur2 $[[T0:[0-9]+]], $4, 4 + ; MM64: seh $2, $[[T0]] + + %r = add i16 4, %a + ret i16 %r +} + +define signext i32 @add_i32_4(i32 signext %a) { +; ALL-LABEL: add_i32_4: + + ; GP32: addiu $2, $4, 4 + + ; GP64: addiu $2, $4, 4 + + ; MM32: addiur2 $2, $4, 4 + + ; MM64: addiur2 $2, $4, 4 + + %r = add i32 4, %a + ret i32 %r +} + +define signext i64 @add_i64_4(i64 signext %a) { +; ALL-LABEL: add_i64_4: + + ; GP32: addiu $[[T0:[0-9]+]], $5, 4 + ; GP32: addiu $[[T1:[0-9]+]], $zero, 4 + ; GP32: sltu $[[T1]], $[[T0]], $[[T1]] + ; GP32: addu $2, $4, $[[T1]] + + ; GP64: daddiu $2, $4, 4 + + ; MM32: addiu $[[T0:[0-9]+]], $5, 4 + ; MM32: li16 $[[T1:[0-9]+]], 4 + ; MM32: sltu $[[T2:[0-9]+]], $[[T0]], $[[T1]] + ; MM32: addu $2, $4, $[[T2]] + + ; MM64: daddiu $2, $4, 4 + + %r = add i64 4, %a + ret i64 %r +} + +define signext i128 @add_i128_4(i128 signext %a) { +; ALL-LABEL: add_i128_4: + + ; GP32: addiu $[[T0:[0-9]+]], $7, 4 + ; GP32: addiu $[[T1:[0-9]+]], $zero, 4 + ; GP32: sltu $[[T1]], $[[T0]], $[[T1]] + ; GP32: addu $[[T2:[0-9]+]], $6, $[[T1]] + ; GP32: sltu $[[T1]], $[[T2]], $zero + ; GP32: addu $[[T3:[0-9]+]], $5, $[[T1]] + ; GP32: sltu $[[T1]], $[[T3]], $zero + ; GP32: addu $[[T1]], $4, $[[T1]] + ; GP32: move $4, $[[T2]] + ; GP32: move $5, $[[T0]] + + ; GP64: daddiu $[[T0:[0-9]+]], $5, 4 + ; GP64: daddiu $[[T1:[0-9]+]], $zero, 4 + ; GP64: sltu $[[T1]], $[[T0]], $[[T1]] + ; GP64: daddu $2, $4, $[[T1]] + + ; MM32: addiu $[[T0:[0-9]+]], $7, 4 + ; MM32: li16 $[[T1:[0-9]+]], 4 + ; MM32: sltu $[[T1]], $[[T0]], $[[T1]] + ; MM32: addu $[[T2:[0-9]+]], $6, $[[T1]] + ; MM32: lui $[[T1]], 0 + ; MM32: sltu $[[T3:[0-9]+]], $[[T2]], $[[T1]] + ; MM32: addu $[[T3]], $5, $[[T3]] + ; MM32: sltu $[[T1]], $[[T3]], $[[T1]] + ; MM32: addu $[[T1]], $4, $[[T1]] + ; MM32: move $4, $[[T2]] + ; MM32: move $5, $[[T0]] + + ; MM64: daddiu $[[T0:[0-9]+]], $5, 4 + ; MM64: daddiu $[[T1:[0-9]+]], $zero, 4 + ; MM64: sltu $[[T1]], $[[T0]], $[[T1]] + ; MM64: daddu $2, $4, $[[T1]] + + %r = add i128 4, %a + ret i128 %r +} + +define signext i1 @add_i1_3(i1 signext %a) { +; ALL-LABEL: add_i1_3: + + ; ALL: sll $[[T0:[0-9]+]], $4, 31 + ; ALL: lui $[[T1:[0-9]+]], 32768 + + ; GP32: addu $[[T0]], $[[T0]], $[[T1]] + ; GP32: sra $[[T1]], $[[T0]], 31 + + ; GP64: addu $[[T0]], $[[T0]], $[[T1]] + ; GP64: sra $[[T1]], $[[T0]], 31 + + ; MMR6: addu16 $[[T0]], $[[T0]], $[[T1]] + ; MMR6: sra $[[T0]], $[[T0]], 31 + + %r = add i1 3, %a + ret i1 %r +} + +define signext i8 @add_i8_3(i8 signext %a) { +; ALL-LABEL: add_i8_3: + + ; NOT-R2-R6: sll $[[T0:[0-9]+]], $4, 24 + ; NOT-R2-R6: lui $[[T1:[0-9]+]], 768 + ; NOT-R2-R6: addu $[[T0]], $[[T0]], $[[T1]] + ; NOT-R2-R6: sra $2, $[[T0]], 24 + + ; R2-R6: addiu $[[T0:[0-9]+]], $4, 3 + ; R2-R6: seb $2, $[[T0]] + + ; MMR6: addius5 $[[T0:[0-9]+]], 3 + ; MMR6: seb $2, $[[T0]] + + %r = add i8 3, %a + ret i8 %r +} + +define signext i16 @add_i16_3(i16 signext %a) { +; ALL-LABEL: add_i16_3: + + ; NOT-R2-R6: sll $[[T0:[0-9]+]], $4, 16 + ; NOT-R2-R6: lui $[[T1:[0-9]+]], 3 + ; NOT-R2-R6: addu $[[T0]], $[[T0]], $[[T1]] + ; NOT-R2-R6: sra $2, $[[T0]], 16 + + ; R2-R6: addiu $[[T0:[0-9]+]], $4, 3 + ; R2-R6: seh $2, $[[T0]] + + ; MMR6: addius5 $[[T0:[0-9]+]], 3 + ; MMR6: seh $2, $[[T0]] + + %r = add i16 3, %a + ret i16 %r +} + +define signext i32 @add_i32_3(i32 signext %a) { +; ALL-LABEL: add_i32_3: + + ; NOT-R2-R6: addiu $2, $4, 3 + + ; R2-R6: addiu $2, $4, 3 + + ; MMR6: addius5 $[[T0:[0-9]+]], 3 + ; MMR6: move $2, $[[T0]] + + %r = add i32 3, %a + ret i32 %r +} + +define signext i64 @add_i64_3(i64 signext %a) { +; ALL-LABEL: add_i64_3: + + ; GP32: addiu $[[T0:[0-9]+]], $5, 3 + ; GP32: addiu $[[T1:[0-9]+]], $zero, 3 + ; GP32: sltu $[[T1]], $[[T0]], $[[T1]] + ; GP32: addu $2, $4, $[[T1]] + + ; GP64: daddiu $2, $4, 3 + + ; MM32: addiu $[[T0:[0-9]+]], $5, 3 + ; MM32: li16 $[[T1:[0-9]+]], 3 + ; MM32: sltu $[[T2:[0-9]+]], $[[T0]], $[[T1]] + ; MM32: addu $2, $4, $[[T2]] + + ; MM64: daddiu $2, $4, 3 + + %r = add i64 3, %a + ret i64 %r +} + +define signext i128 @add_i128_3(i128 signext %a) { +; ALL-LABEL: add_i128_3: + + ; GP32: addiu $[[T0:[0-9]+]], $7, 3 + ; GP32: addiu $[[T1:[0-9]+]], $zero, 3 + ; GP32: sltu $[[T1]], $[[T0]], $[[T1]] + ; GP32: addu $[[T2:[0-9]+]], $6, $[[T1]] + ; GP32: sltu $[[T3:[0-9]+]], $[[T2]], $zero + ; GP32: addu $[[T4:[0-9]+]], $5, $[[T3]] + ; GP32: sltu $[[T5:[0-9]+]], $[[T4]], $zero + ; GP32: addu $[[T5]], $4, $[[T5]] + ; GP32: move $4, $[[T2]] + ; GP32: move $5, $[[T0]] + + ; GP64: daddiu $[[T0:[0-9]+]], $5, 3 + ; GP64: daddiu $[[T1:[0-9]+]], $zero, 3 + ; GP64: sltu $[[T1]], $[[T0]], $[[T1]] + ; GP64: daddu $2, $4, $[[T1]] + + ; MM32: addiu $[[T0:[0-9]+]], $7, 3 + ; MM32: li16 $[[T1:[0-9]+]], 3 + ; MM32: sltu $[[T1]], $[[T0]], $[[T1]] + ; MM32: addu $[[T2:[0-9]+]], $6, $[[T1]] + ; MM32: lui $[[T3:[0-9]+]], 0 + ; MM32: sltu $[[T4:[0-9]+]], $[[T2]], $[[T3]] + ; MM32: addu $[[T4]], $5, $[[T4]] + ; MM32: sltu $[[T5:[0-9]+]], $[[T4]], $[[T3]] + ; MM32: addu $[[T5]], $4, $[[T5]] + ; MM32: move $4, $[[T2]] + ; MM32: move $5, $[[T0]] + + ; MM64: daddiu $[[T0:[0-9]+]], $5, 3 + ; MM64: daddiu $[[T1:[0-9]+]], $zero, 3 + ; MM64: sltu $[[T1]], $[[T0]], $[[T1]] + ; MM64: daddu $2, $4, $[[T1]] + + %r = add i128 3, %a + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/and.ll b/test/CodeGen/Mips/llvm-ir/and.ll index c4121701ec15..d320ce60f291 100644 --- a/test/CodeGen/Mips/llvm-ir/and.ll +++ b/test/CodeGen/Mips/llvm-ir/and.ll @@ -1,35 +1,46 @@ ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM64 define signext i1 @and_i1(i1 signext %a, i1 signext %b) { entry: ; ALL-LABEL: and_i1: - ; ALL: and $2, $4, $5 + ; GP32: and $2, $4, $5 + + ; GP64: and $2, $4, $5 + + ; MM: and16 $[[T0:[0-9]+]], $5 + ; MM: move $2, $[[T0]] %r = and i1 %a, %b ret i1 %r @@ -39,7 +50,12 @@ define signext i8 @and_i8(i8 signext %a, i8 signext %b) { entry: ; ALL-LABEL: and_i8: - ; ALL: and $2, $4, $5 + ; GP32: and $2, $4, $5 + + ; GP64: and $2, $4, $5 + + ; MM: and16 $[[T0:[0-9]+]], $5 + ; MM: move $2, $[[T0]] %r = and i8 %a, %b ret i8 %r @@ -49,7 +65,12 @@ define signext i16 @and_i16(i16 signext %a, i16 signext %b) { entry: ; ALL-LABEL: and_i16: - ; ALL: and $2, $4, $5 + ; GP32: and $2, $4, $5 + + ; GP64: and $2, $4, $5 + + ; MM: and16 $[[T0:[0-9]+]], $5 + ; MM: move $2, $[[T0]] %r = and i16 %a, %b ret i16 %r @@ -64,6 +85,12 @@ entry: ; GP64: and $[[T0:[0-9]+]], $4, $5 ; GP64: sll $2, $[[T0]], 0 + ; MM32: and16 $[[T0:[0-9]+]], $5 + ; MM32: move $2, $[[T0]] + + ; MM64: and $[[T0:[0-9]+]], $4, $5 + ; MM64: sll $2, $[[T0]], 0 + %r = and i32 %a, %b ret i32 %r } @@ -77,6 +104,13 @@ entry: ; GP64: and $2, $4, $5 + ; MM32: and16 $[[T0:[0-9]+]], $6 + ; MM32: and16 $[[T1:[0-9]+]], $7 + ; MM32: move $2, $[[T0]] + ; MM32: move $3, $[[T1]] + + ; MM64: and $2, $4, $5 + %r = and i64 %a, %b ret i64 %r } @@ -97,6 +131,573 @@ entry: ; GP64: and $2, $4, $6 ; GP64: and $3, $5, $7 + ; MM32: lw $[[T0:[0-9]+]], 20($sp) + ; MM32: lw $[[T1:[0-9]+]], 16($sp) + ; MM32: and16 $[[T1]], $4 + ; MM32: and16 $[[T0]], $5 + ; MM32: lw $[[T2:[0-9]+]], 24($sp) + ; MM32: and16 $[[T2]], $6 + ; MM32: lw $[[T3:[0-9]+]], 28($sp) + ; MM32: and16 $[[T3]], $7 + + ; MM64: and $2, $4, $6 + ; MM64: and $3, $5, $7 + %r = and i128 %a, %b ret i128 %r } + +define signext i1 @and_i1_4(i1 signext %b) { +entry: +; ALL-LABEL: and_i1_4: + + ; GP32: addiu $2, $zero, 0 + + ; GP64: addiu $2, $zero, 0 + + ; MM: lui $2, 0 + + %r = and i1 4, %b + ret i1 %r +} + +define signext i8 @and_i8_4(i8 signext %b) { +entry: +; ALL-LABEL: and_i8_4: + + ; GP32: andi $2, $4, 4 + + ; GP64: andi $2, $4, 4 + + ; MM: andi16 $2, $4, 4 + + %r = and i8 4, %b + ret i8 %r +} + +define signext i16 @and_i16_4(i16 signext %b) { +entry: +; ALL-LABEL: and_i16_4: + + ; GP32: andi $2, $4, 4 + + ; GP64: andi $2, $4, 4 + + ; MM: andi16 $2, $4, 4 + + %r = and i16 4, %b + ret i16 %r +} + +define signext i32 @and_i32_4(i32 signext %b) { +entry: +; ALL-LABEL: and_i32_4: + + ; GP32: andi $2, $4, 4 + + ; GP64: andi $2, $4, 4 + + ; MM: andi16 $2, $4, 4 + + %r = and i32 4, %b + ret i32 %r +} + +define signext i64 @and_i64_4(i64 signext %b) { +entry: +; ALL-LABEL: and_i64_4: + + ; GP32: andi $3, $5, 4 + ; GP32: addiu $2, $zero, 0 + + ; GP64: andi $2, $4, 4 + + ; MM32: andi16 $3, $5, 4 + ; MM32: lui $2, 0 + + ; MM64: andi $2, $4, 4 + + %r = and i64 4, %b + ret i64 %r +} + +define signext i128 @and_i128_4(i128 signext %b) { +entry: +; ALL-LABEL: and_i128_4: + + ; GP32: andi $5, $7, 4 + ; GP32: addiu $2, $zero, 0 + ; GP32: addiu $3, $zero, 0 + ; GP32: addiu $4, $zero, 0 + + ; GP64: andi $3, $5, 4 + ; GP64: daddiu $2, $zero, 0 + + ; MM32: andi16 $5, $7, 4 + ; MM32: lui $2, 0 + ; MM32: lui $3, 0 + ; MM32: lui $4, 0 + + ; MM64: andi $3, $5, 4 + ; MM64: daddiu $2, $zero, 0 + + %r = and i128 4, %b + ret i128 %r +} + +define signext i1 @and_i1_31(i1 signext %b) { +entry: +; ALL-LABEL: and_i1_31: + + ; ALL: move $2, $4 + + %r = and i1 31, %b + ret i1 %r +} + +define signext i8 @and_i8_31(i8 signext %b) { +entry: +; ALL-LABEL: and_i8_31: + + ; GP32: andi $2, $4, 31 + + ; GP64: andi $2, $4, 31 + + ; MM: andi16 $2, $4, 31 + + %r = and i8 31, %b + ret i8 %r +} + +define signext i16 @and_i16_31(i16 signext %b) { +entry: +; ALL-LABEL: and_i16_31: + + ; GP32: andi $2, $4, 31 + + ; GP64: andi $2, $4, 31 + + ; MM: andi16 $2, $4, 31 + + %r = and i16 31, %b + ret i16 %r +} + +define signext i32 @and_i32_31(i32 signext %b) { +entry: +; ALL-LABEL: and_i32_31: + + ; GP32: andi $2, $4, 31 + + ; GP64: andi $2, $4, 31 + + ; MM: andi16 $2, $4, 31 + + %r = and i32 31, %b + ret i32 %r +} + +define signext i64 @and_i64_31(i64 signext %b) { +entry: +; ALL-LABEL: and_i64_31: + + ; GP32: andi $3, $5, 31 + ; GP32: addiu $2, $zero, 0 + + ; GP64: andi $2, $4, 31 + + ; MM32: andi16 $3, $5, 31 + ; MM32: lui $2, 0 + + ; MM64: andi $2, $4, 31 + + %r = and i64 31, %b + ret i64 %r +} + +define signext i128 @and_i128_31(i128 signext %b) { +entry: +; ALL-LABEL: and_i128_31: + + ; GP32: andi $5, $7, 31 + ; GP32: addiu $2, $zero, 0 + ; GP32: addiu $3, $zero, 0 + ; GP32: addiu $4, $zero, 0 + + ; GP64: andi $3, $5, 31 + ; GP64: daddiu $2, $zero, 0 + + ; MM32: andi16 $5, $7, 31 + ; MM32: lui $2, 0 + ; MM32: lui $3, 0 + ; MM32: lui $4, 0 + + ; MM64: andi $3, $5, 31 + ; MM64: daddiu $2, $zero, 0 + + %r = and i128 31, %b + ret i128 %r +} + +define signext i1 @and_i1_255(i1 signext %b) { +entry: +; ALL-LABEL: and_i1_255: + + ; ALL: move $2, $4 + + %r = and i1 255, %b + ret i1 %r +} + +define signext i8 @and_i8_255(i8 signext %b) { +entry: +; ALL-LABEL: and_i8_255: + + ; ALL: move $2, $4 + + %r = and i8 255, %b + ret i8 %r +} + +define signext i16 @and_i16_255(i16 signext %b) { +entry: +; ALL-LABEL: and_i16_255: + + ; GP32: andi $2, $4, 255 + + ; GP64: andi $2, $4, 255 + + ; MM: andi16 $2, $4, 255 + + %r = and i16 255, %b + ret i16 %r +} + +define signext i32 @and_i32_255(i32 signext %b) { +entry: +; ALL-LABEL: and_i32_255: + + ; GP32: andi $2, $4, 255 + + ; GP64: andi $2, $4, 255 + + ; MM: andi16 $2, $4, 255 + + %r = and i32 255, %b + ret i32 %r +} + +define signext i64 @and_i64_255(i64 signext %b) { +entry: +; ALL-LABEL: and_i64_255: + + ; GP32: andi $3, $5, 255 + ; GP32: addiu $2, $zero, 0 + + ; GP64: andi $2, $4, 255 + + ; MM32: andi16 $3, $5, 255 + ; MM32: lui $2, 0 + + ; MM64: andi $2, $4, 255 + + %r = and i64 255, %b + ret i64 %r +} + +define signext i128 @and_i128_255(i128 signext %b) { +entry: +; ALL-LABEL: and_i128_255: + + ; GP32: andi $5, $7, 255 + ; GP32: addiu $2, $zero, 0 + ; GP32: addiu $3, $zero, 0 + ; GP32: addiu $4, $zero, 0 + + ; GP64: andi $3, $5, 255 + ; GP64: daddiu $2, $zero, 0 + + ; MM32: andi16 $5, $7, 255 + ; MM32: lui $2, 0 + ; MM32: lui $3, 0 + ; MM32: lui $4, 0 + + ; MM64: andi $3, $5, 255 + ; MM64: daddiu $2, $zero, 0 + + %r = and i128 255, %b + ret i128 %r +} + +define signext i1 @and_i1_32768(i1 signext %b) { +entry: +; ALL-LABEL: and_i1_32768: + + ; GP32: addiu $2, $zero, 0 + + ; GP64: addiu $2, $zero, 0 + + ; MM: lui $2, 0 + + %r = and i1 32768, %b + ret i1 %r +} + +define signext i8 @and_i8_32768(i8 signext %b) { +entry: +; ALL-LABEL: and_i8_32768: + + ; GP32: addiu $2, $zero, 0 + + ; GP64: addiu $2, $zero, 0 + + ; MM: lui $2, 0 + + %r = and i8 32768, %b + ret i8 %r +} + +define signext i16 @and_i16_32768(i16 signext %b) { +entry: +; ALL-LABEL: and_i16_32768: + + ; GP32: addiu $[[T0:[0-9]+]], $zero, -32768 + ; GP32: and $2, $4, $[[T0]] + + ; GP64: addiu $[[T0:[0-9]+]], $zero, -32768 + ; GP64: and $2, $4, $[[T0]] + + ; MM: addiu $2, $zero, -32768 + ; MM: and16 $2, $4 + + %r = and i16 32768, %b + ret i16 %r +} + +define signext i32 @and_i32_32768(i32 signext %b) { +entry: +; ALL-LABEL: and_i32_32768: + + ; GP32: andi $2, $4, 32768 + + ; GP64: andi $2, $4, 32768 + + ; MM: andi16 $2, $4, 32768 + + %r = and i32 32768, %b + ret i32 %r +} + +define signext i64 @and_i64_32768(i64 signext %b) { +entry: +; ALL-LABEL: and_i64_32768: + + ; GP32: andi $3, $5, 32768 + ; GP32: addiu $2, $zero, 0 + + ; GP64: andi $2, $4, 32768 + + ; MM32: andi16 $3, $5, 32768 + ; MM32: lui $2, 0 + + ; MM64: andi $2, $4, 32768 + + %r = and i64 32768, %b + ret i64 %r +} + +define signext i128 @and_i128_32768(i128 signext %b) { +entry: +; ALL-LABEL: and_i128_32768: + + ; GP32: andi $5, $7, 32768 + ; GP32: addiu $2, $zero, 0 + ; GP32: addiu $3, $zero, 0 + ; GP32: addiu $4, $zero, 0 + + ; GP64: andi $3, $5, 32768 + ; GP64: daddiu $2, $zero, 0 + + ; MM32: andi16 $5, $7, 32768 + ; MM32: lui $2, 0 + ; MM32: lui $3, 0 + ; MM32: lui $4, 0 + + ; MM64: andi $3, $5, 32768 + ; MM64: daddiu $2, $zero, 0 + + %r = and i128 32768, %b + ret i128 %r +} + +define signext i1 @and_i1_65(i1 signext %b) { +entry: +; ALL-LABEL: and_i1_65: + + ; ALL: move $2, $4 + + %r = and i1 65, %b + ret i1 %r +} + +define signext i8 @and_i8_65(i8 signext %b) { +entry: +; ALL-LABEL: and_i8_65: + + ; ALL: andi $2, $4, 65 + + %r = and i8 65, %b + ret i8 %r +} + +define signext i16 @and_i16_65(i16 signext %b) { +entry: +; ALL-LABEL: and_i16_65: + + ; ALL: andi $2, $4, 65 + + %r = and i16 65, %b + ret i16 %r +} + +define signext i32 @and_i32_65(i32 signext %b) { +entry: +; ALL-LABEL: and_i32_65: + + ; ALL: andi $2, $4, 65 + + %r = and i32 65, %b + ret i32 %r +} + +define signext i64 @and_i64_65(i64 signext %b) { +entry: +; ALL-LABEL: and_i64_65: + + ; GP32: andi $3, $5, 65 + ; GP32: addiu $2, $zero, 0 + + ; GP64: andi $2, $4, 65 + + ; MM32: andi $3, $5, 65 + ; MM32: lui $2, 0 + + ; MM64: andi $2, $4, 65 + + %r = and i64 65, %b + ret i64 %r +} + +define signext i128 @and_i128_65(i128 signext %b) { +entry: +; ALL-LABEL: and_i128_65: + + ; GP32: andi $5, $7, 65 + ; GP32: addiu $2, $zero, 0 + ; GP32: addiu $3, $zero, 0 + ; GP32: addiu $4, $zero, 0 + + ; GP64: andi $3, $5, 65 + ; GP64: daddiu $2, $zero, 0 + + ; MM32: andi $5, $7, 65 + ; MM32: lui $2, 0 + ; MM32: lui $3, 0 + ; MM32: lui $4, 0 + + ; MM64: andi $3, $5, 65 + ; MM64: daddiu $2, $zero, 0 + + %r = and i128 65, %b + ret i128 %r +} + +define signext i1 @and_i1_256(i1 signext %b) { +entry: +; ALL-LABEL: and_i1_256: + + ; GP32: addiu $2, $zero, 0 + + ; GP64: addiu $2, $zero, 0 + + ; MM: lui $2, 0 + + %r = and i1 256, %b + ret i1 %r +} + +define signext i8 @and_i8_256(i8 signext %b) { +entry: +; ALL-LABEL: and_i8_256: + + ; GP32: addiu $2, $zero, 0 + + ; GP64: addiu $2, $zero, 0 + + ; MM: lui $2, 0 + + %r = and i8 256, %b + ret i8 %r +} + +define signext i16 @and_i16_256(i16 signext %b) { +entry: +; ALL-LABEL: and_i16_256: + + ; ALL: andi $2, $4, 256 + + %r = and i16 256, %b + ret i16 %r +} + +define signext i32 @and_i32_256(i32 signext %b) { +entry: +; ALL-LABEL: and_i32_256: + + ; ALL: andi $2, $4, 256 + + %r = and i32 256, %b + ret i32 %r +} + +define signext i64 @and_i64_256(i64 signext %b) { +entry: +; ALL-LABEL: and_i64_256: + + ; GP32: andi $3, $5, 256 + ; GP32: addiu $2, $zero, 0 + + ; GP64: andi $2, $4, 256 + + ; MM32: andi $3, $5, 256 + ; MM32: lui $2, 0 + + ; MM64: andi $2, $4, 256 + + %r = and i64 256, %b + ret i64 %r +} + +define signext i128 @and_i128_256(i128 signext %b) { +entry: +; ALL-LABEL: and_i128_256: + + ; GP32: andi $5, $7, 256 + ; GP32: addiu $2, $zero, 0 + ; GP32: addiu $3, $zero, 0 + ; GP32: addiu $4, $zero, 0 + + ; GP64: andi $3, $5, 256 + ; GP64: daddiu $2, $zero, 0 + + ; MM32: andi $5, $7, 256 + ; MM32: lui $2, 0 + ; MM32: lui $3, 0 + ; MM32: lui $4, 0 + + ; MM64: andi $3, $5, 256 + ; MM64: daddiu $2, $zero, 0 + + %r = and i128 256, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/ashr.ll b/test/CodeGen/Mips/llvm-ir/ashr.ll index cad4a39d7743..af9b81f9203f 100644 --- a/test/CodeGen/Mips/llvm-ir/ashr.ll +++ b/test/CodeGen/Mips/llvm-ir/ashr.ll @@ -1,42 +1,33 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=M2 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R6 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=M3 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=64R6 +; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,M2 +; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R6 +; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,M3 +; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,64R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MMR3 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MMR6 define signext i1 @ashr_i1(i1 signext %a, i1 signext %b) { entry: @@ -53,7 +44,9 @@ entry: ; ALL-LABEL: ashr_i8: ; FIXME: The andi instruction is redundant. - ; ALL: andi $[[T0:[0-9]+]], $5, 255 + ; GP32: andi $[[T0:[0-9]+]], $5, 255 + ; GP64: andi $[[T0:[0-9]+]], $5, 255 + ; MM: andi16 $[[T0:[0-9]+]], $5, 255 ; ALL: srav $2, $4, $[[T0]] %r = ashr i8 %a, %b @@ -65,7 +58,9 @@ entry: ; ALL-LABEL: ashr_i16: ; FIXME: The andi instruction is redundant. - ; ALL: andi $[[T0:[0-9]+]], $5, 65535 + ; GP32: andi $[[T0:[0-9]+]], $5, 65535 + ; GP64: andi $[[T0:[0-9]+]], $5, 65535 + ; MM: andi16 $[[T0:[0-9]+]], $5, 65535 ; ALL: srav $2, $4, $[[T0]] %r = ashr i16 %a, %b @@ -133,6 +128,32 @@ entry: ; GP64: dsrav $2, $4, $5 + ; MMR3: srlv $[[T0:[0-9]+]], $5, $7 + ; MMR3: sll16 $[[T1:[0-9]+]], $4, 1 + ; MMR3: not16 $[[T2:[0-9]+]], $7 + ; MMR3: sllv $[[T3:[0-9]+]], $[[T1]], $[[T2]] + ; MMR3: or16 $[[T4:[0-9]+]], $[[T0]] + ; MMR3: srav $[[T5:[0-9]+]], $4, $7 + ; MMR3: andi16 $[[T6:[0-9]+]], $7, 32 + ; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]] + ; MMR3: sra $[[T8:[0-9]+]], $4, 31 + ; MMR3: movn $2, $[[T8]], $[[T6]] + + ; MMR6: srav $[[T0:[0-9]+]], $4, $7 + ; MMR6: andi16 $[[T1:[0-9]+]], $7, 32 + ; MMR6: seleqz $[[T2:[0-9]+]], $[[T0]], $[[T1]] + ; MMR6: sra $[[T3:[0-9]+]], $4, 31 + ; MMR6: selnez $[[T4:[0-9]+]], $[[T3]], $[[T1]] + ; MMR6: or $[[T5:[0-9]+]], $[[T4]], $[[T2]] + ; MMR6: srlv $[[T6:[0-9]+]], $5, $7 + ; MMR6: sll16 $[[T7:[0-9]+]], $4, 1 + ; MMR6: not16 $[[T8:[0-9]+]], $7 + ; MMR6: sllv $[[T9:[0-9]+]], $[[T7]], $[[T8]] + ; MMR6: or16 $[[T10:[0-9]+]], $[[T6]] + ; MMR6: seleqz $[[T11:[0-9]+]], $[[T10]], $[[T1]] + ; MMR6: selnez $[[T12:[0-9]+]], $[[T0]], $[[T1]] + ; MMR6: or $3, $[[T12]], $[[T11]] + %r = ashr i64 %a, %b ret i64 %r } @@ -192,6 +213,8 @@ entry: ; 64R6: jr $ra ; 64R6: or $3, $[[T13]], $[[T12]] + ; MM: lw $25, %call16(__ashrti3)($2) + %r = ashr i128 %a, %b ret i128 %r } diff --git a/test/CodeGen/Mips/llvm-ir/call.ll b/test/CodeGen/Mips/llvm-ir/call.ll index a4b03405f72b..0d524d439600 100644 --- a/test/CodeGen/Mips/llvm-ir/call.ll +++ b/test/CodeGen/Mips/llvm-ir/call.ll @@ -1,18 +1,18 @@ ; Test the 'call' instruction and the tailcall variant. ; FIXME: We should remove the need for -enable-mips-tail-calls -; RUN: llc -march=mips -mcpu=mips32 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -; RUN: llc -march=mips -mcpu=mips32r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -; RUN: llc -march=mips -mcpu=mips32r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -; RUN: llc -march=mips -mcpu=mips32r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -; RUN: llc -march=mips -mcpu=mips32r6 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+fp64,+nooddspreg -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -; RUN: llc -march=mips64 -mcpu=mips4 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -; RUN: llc -march=mips64 -mcpu=mips64 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -; RUN: llc -march=mips64 -mcpu=mips64r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -; RUN: llc -march=mips64 -mcpu=mips64r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -; RUN: llc -march=mips64 -mcpu=mips64r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -; RUN: llc -march=mips64 -mcpu=mips64r6 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 +; RUN: llc -march=mips -mcpu=mips32 -relocation-model=pic -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C +; RUN: llc -march=mips -mcpu=mips32r2 -relocation-model=pic -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C +; RUN: llc -march=mips -mcpu=mips32r3 -relocation-model=pic -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C +; RUN: llc -march=mips -mcpu=mips32r5 -relocation-model=pic -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C +; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -disable-mips-delay-filler -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,O32,R6C +; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -mattr=+fp64,+nooddspreg -disable-mips-delay-filler -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,O32,R6C +; RUN: llc -march=mips64 -mcpu=mips4 -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C +; RUN: llc -march=mips64 -mcpu=mips64 -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C +; RUN: llc -march=mips64 -mcpu=mips64r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C +; RUN: llc -march=mips64 -mcpu=mips64r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C +; RUN: llc -march=mips64 -mcpu=mips64r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C +; RUN: llc -march=mips64 -mcpu=mips64r6 -disable-mips-delay-filler -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,N64,R6C declare void @extern_void_void() declare i32 @extern_i32_void() @@ -25,9 +25,11 @@ define i32 @call_void_void() { ; N64: ld $[[TGT:[0-9]+]], %call16(extern_void_void)($gp) -; ALL: jalr $[[TGT]] +; NOT-R6C: jalr $[[TGT]] +; R6C: jalrc $[[TGT]] call void @extern_void_void() +; R6C: jrc $ra ret i32 0 } @@ -38,10 +40,12 @@ define i32 @call_i32_void() { ; N64: ld $[[TGT:[0-9]+]], %call16(extern_i32_void)($gp) -; ALL: jalr $[[TGT]] +; NOT-R6C: jalr $[[TGT]] +; R6C: jalrc $[[TGT]] %1 = call i32 @extern_i32_void() %2 = add i32 %1, 1 +; R6C: jrc $ra ret i32 %2 } @@ -55,12 +59,13 @@ define float @call_float_void() { ; N64: ld $[[TGT:[0-9]+]], %call16(extern_float_void)($gp) -; ALL: jalr $[[TGT]] +; NOT-R6C: jalr $[[TGT]] +; R6C: jalrc $[[TGT]] -; O32: move $gp, $[[GP]] %1 = call float @extern_float_void() %2 = fadd float %1, 1.0 +; R6C: jrc $ra ret float %2 } @@ -71,8 +76,7 @@ define void @musttail_call_void_void() { ; N64: ld $[[TGT:[0-9]+]], %call16(extern_void_void)($gp) -; NOT-R6: jr $[[TGT]] -; R6: r6.jr $[[TGT]] +; ALL: jr $[[TGT]] musttail call void @extern_void_void() ret void @@ -85,8 +89,7 @@ define i32 @musttail_call_i32_void() { ; N64: ld $[[TGT:[0-9]+]], %call16(extern_i32_void)($gp) -; NOT-R6: jr $[[TGT]] -; R6: r6.jr $[[TGT]] +; ALL: jr $[[TGT]] %1 = musttail call i32 @extern_i32_void() ret i32 %1 @@ -99,8 +102,7 @@ define float @musttail_call_float_void() { ; N64: ld $[[TGT:[0-9]+]], %call16(extern_float_void)($gp) -; NOT-R6: jr $[[TGT]] -; R6: r6.jr $[[TGT]] +; ALL: jr $[[TGT]] %1 = musttail call float @extern_float_void() ret float %1 @@ -110,9 +112,11 @@ define i32 @indirect_call_void_void(void ()* %addr) { ; ALL-LABEL: indirect_call_void_void: ; ALL: move $25, $4 -; ALL: jalr $25 +; NOT-R6C: jalr $25 +; R6C: jalrc $25 call void %addr() +; R6C: jrc $ra ret i32 0 } @@ -120,10 +124,13 @@ define i32 @indirect_call_i32_void(i32 ()* %addr) { ; ALL-LABEL: indirect_call_i32_void: ; ALL: move $25, $4 -; ALL: jalr $25 +; NOT-R6C: jalr $25 +; R6C: jalrc $25 + %1 = call i32 %addr() %2 = add i32 %1, 1 +; R6C: jrc $ra ret i32 %2 } @@ -131,10 +138,13 @@ define float @indirect_call_float_void(float ()* %addr) { ; ALL-LABEL: indirect_call_float_void: ; ALL: move $25, $4 -; ALL: jalr $25 +; NOT-R6C: jalr $25 +; R6C: jalrc $25 + %1 = call float %addr() %2 = fadd float %1, 1.0 +; R6C: jrc $ra ret float %2 } @@ -178,7 +188,8 @@ define hidden void @thunk_undef_double(i32 %this, double %volume) unnamed_addr a ; ALL-LABEL: thunk_undef_double: ; O32: # implicit-def: %A2 ; O32: # implicit-def: %A3 -; ALL: jr $25 +; ALL: jr $25 + tail call void @undef_double(i32 undef, double undef) #8 ret void } @@ -190,10 +201,12 @@ define i32 @jal_only_allows_symbols() { ; ALL-NOT: {{jal }} ; ALL: addiu $[[TGT:[0-9]+]], $zero, 1234 ; ALL-NOT: {{jal }} -; ALL: jalr $[[TGT]] +; NOT-R6C: jalr $[[TGT]] +; R6C: jalrc $[[TGT]] ; ALL-NOT: {{jal }} call void () inttoptr (i32 1234 to void ()*)() +; R6C: jrc $ra ret i32 0 } diff --git a/test/CodeGen/Mips/llvm-ir/indirectbr.ll b/test/CodeGen/Mips/llvm-ir/indirectbr.ll index debfeb35b213..d982b570d7c2 100644 --- a/test/CodeGen/Mips/llvm-ir/indirectbr.ll +++ b/test/CodeGen/Mips/llvm-ir/indirectbr.ll @@ -1,30 +1,33 @@ ; Test all important variants of the unconditional 'br' instruction. -; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6 -; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6 +; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,R6C +; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,R6 define i32 @br(i8 *%addr) { ; ALL-LABEL: br: ; NOT-R6: jr $4 # <MCInst #{{[0-9]+}} JR -; R6: jr $4 # <MCInst #{{[0-9]+}} JALR +; R6C: jrc $4 # <MCInst #{{[0-9]+}} JIC + ; ALL: $BB0_1: # %L1 ; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR +; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR ; ALL: addiu $2, $zero, 0 ; ALL: $BB0_2: # %L2 ; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR +; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR ; ALL: addiu $2, $zero, 1 entry: diff --git a/test/CodeGen/Mips/llvm-ir/lh_lhu.ll b/test/CodeGen/Mips/llvm-ir/lh_lhu.ll new file mode 100644 index 000000000000..fadcfdb0fb4f --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/lh_lhu.ll @@ -0,0 +1,32 @@ +; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips -relocation-model=pic | FileCheck %s +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s +; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s + +@us = global i16 0, align 2 + +define i32 @lhfunc() { +entry: +; CHECK-LABEL: lhfunc +; CHECK: lh $[[REG1:[0-9]+]], 0(${{[0-9]+}}) + %0 = load i16, i16* @us, align 2 + %conv = sext i16 %0 to i32 + ret i32 %conv +} + +define i16 @lhfunc_atomic() { +entry: +; CHECK-LABEL: lhfunc_atomic +; CHECK: lh $[[REG1:[0-9]+]], 0(${{[0-9]+}}) + %0 = load atomic i16, i16* @us acquire, align 2 + ret i16 %0 +} + +define i32 @lhufunc() { +entry: +; CHECK-LABEL: lhufunc +; CHECK: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) + %0 = load i16, i16* @us, align 2 + %conv = zext i16 %0 to i32 + ret i32 %conv +} diff --git a/test/CodeGen/Mips/llvm-ir/load-atomic.ll b/test/CodeGen/Mips/llvm-ir/load-atomic.ll index a44b00bff586..baf9a74a2c54 100644 --- a/test/CodeGen/Mips/llvm-ir/load-atomic.ll +++ b/test/CodeGen/Mips/llvm-ir/load-atomic.ll @@ -1,9 +1,9 @@ ; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL ; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL ; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=M64 +; RUN: FileCheck %s -check-prefixes=ALL,M64 ; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=M64 +; RUN: FileCheck %s -check-prefixes=ALL,M64 define i8 @load_i8(i8* %ptr) { ; ALL-LABEL: load_i8 diff --git a/test/CodeGen/Mips/llvm-ir/lshr.ll b/test/CodeGen/Mips/llvm-ir/lshr.ll index 3a7029fa5b7a..10748b9c803a 100644 --- a/test/CodeGen/Mips/llvm-ir/lshr.ll +++ b/test/CodeGen/Mips/llvm-ir/lshr.ll @@ -1,42 +1,33 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=M2 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R6 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=M3 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=64R6 +; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,M2 +; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R6 +; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,M3 +; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,64R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MMR3 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MMR6 define signext i1 @lshr_i1(i1 signext %a, i1 signext %b) { entry: @@ -53,7 +44,9 @@ entry: ; ALL-LABEL: lshr_i8: ; ALL: srlv $[[T0:[0-9]+]], $4, $5 - ; ALL: andi $2, $[[T0]], 255 + ; GP32: andi $2, $[[T0]], 255 + ; GP64: andi $2, $[[T0]], 255 + ; MM: andi16 $2, $[[T0]], 255 %r = lshr i8 %a, %b ret i8 %r @@ -64,7 +57,9 @@ entry: ; ALL-LABEL: lshr_i16: ; ALL: srlv $[[T0:[0-9]+]], $4, $5 - ; ALL: andi $2, $[[T0]], 65535 + ; GP32: andi $2, $[[T0]], 65535 + ; GP64: andi $2, $[[T0]], 65535 + ; MM: andi16 $2, $[[T0]], 65535 %r = lshr i16 %a, %b ret i16 %r @@ -127,6 +122,29 @@ entry: ; GP64: dsrlv $2, $4, $5 + ; MMR3: srlv $[[T0:[0-9]+]], $5, $7 + ; MMR3: sll16 $[[T1:[0-9]+]], $4, 1 + ; MMR3: not16 $[[T2:[0-9]+]], $7 + ; MMR3: sllv $[[T3:[0-9]+]], $[[T1]], $[[T2]] + ; MMR3: or16 $[[T4:[0-9]+]], $[[T0]] + ; MMR3: srlv $[[T5:[0-9]+]], $4, $7 + ; MMR3: andi16 $[[T6:[0-9]+]], $7, 32 + ; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]] + ; MMR3: lui $[[T8:[0-9]+]], 0 + ; MMR3: movn $2, $[[T8]], $[[T6]] + + ; MMR6: srlv $[[T0:[0-9]+]], $5, $7 + ; MMR6: sll16 $[[T1:[0-9]+]], $4, 1 + ; MMR6: not16 $[[T2:[0-9]+]], $7 + ; MMR6: sllv $[[T3:[0-9]+]], $[[T1]], $[[T2]] + ; MMR6: or16 $[[T4:[0-9]+]], $[[T0]] + ; MMR6: andi16 $[[T5:[0-9]+]], $7, 32 + ; MMR6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T5]] + ; MMR6: srlv $[[T7:[0-9]+]], $4, $7 + ; MMR6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]] + ; MMR6: or $3, $[[T8]], $[[T6]] + ; MMR6: seleqz $2, $[[T7]], $[[T5]] + %r = lshr i64 %a, %b ret i64 %r } @@ -182,6 +200,8 @@ entry: ; 64R6: jr $ra ; 64R6: seleqz $2, $[[T9]], $[[T7]] + ; MM: lw $25, %call16(__lshrti3)($2) + %r = lshr i128 %a, %b ret i128 %r } diff --git a/test/CodeGen/Mips/llvm-ir/mul.ll b/test/CodeGen/Mips/llvm-ir/mul.ll index a7582805dd74..8d63e496806c 100644 --- a/test/CodeGen/Mips/llvm-ir/mul.ll +++ b/test/CodeGen/Mips/llvm-ir/mul.ll @@ -1,27 +1,33 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=M2 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=32R1-R5 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=32R6 -check-prefix=GP32 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=M4 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=64R1-R5 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=64R6 +; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=ALL,M2,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=ALL,32R6,GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=ALL,M4,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=ALL,64R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=MM32,MM32R3 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=MM32,MM32R6 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefix=64R6 define signext i1 @mul_i1(i1 signext %a, i1 signext %b) { entry: @@ -53,6 +59,10 @@ entry: ; 64R6: sll $[[T0]], $[[T0]], 31 ; 64R6: sra $2, $[[T0]], 31 + ; MM32: mul $[[T0:[0-9]+]], $4, $5 + ; MM32: sll $[[T0]], $[[T0]], 31 + ; MM32: sra $2, $[[T0]], 31 + %r = mul i1 %a, %b ret i1 %r } @@ -90,6 +100,10 @@ entry: ; 64R6: mul $[[T0:[0-9]+]], $4, $5 ; 64R6: seb $2, $[[T0]] + + ; MM32: mul $[[T0:[0-9]+]], $4, $5 + ; MM32: seb $2, $[[T0]] + %r = mul i8 %a, %b ret i8 %r } @@ -127,6 +141,10 @@ entry: ; 64R6: mul $[[T0:[0-9]+]], $4, $5 ; 64R6: seh $2, $[[T0]] + + ; MM32: mul $[[T0:[0-9]+]], $4, $5 + ; MM32: seh $2, $[[T0]] + %r = mul i16 %a, %b ret i16 %r } @@ -143,6 +161,9 @@ entry: ; 64R1-R5: mul $2, $4, $5 ; 64R6: mul $2, $4, $5 + + ; MM32: mul $2, $4, $5 + %r = mul i32 %a, %b ret i32 %r } @@ -169,12 +190,12 @@ entry: ; 32R1-R5: addu $[[T0]], $[[T0]], $[[T2:[0-9]+]] ; 32R1-R5: addu $2, $[[T0]], $[[T1]] - ; 32R6: mul $[[T0:[0-9]+]], $5, $6 - ; 32R6: muhu $[[T1:[0-9]+]], $5, $7 - ; 32R6: addu $[[T0]], $[[T1]], $[[T0]] - ; 32R6: mul $[[T2:[0-9]+]], $4, $7 - ; 32R6: addu $2, $[[T0]], $[[T2]] - ; 32R6: mul $3, $5, $7 + ; 32R6-DAG: mul $3, $5, $7 + ; 32R6-DAG: mul $[[T0:[0-9]+]], $4, $7 + ; 32R6-DAG: mul $[[T1:[0-9]+]], $5, $6 + ; 32R6: muhu $[[T2:[0-9]+]], $5, $7 + ; 32R6: addu $[[T1]], $[[T2]], $[[T1]] + ; 32R6: addu $2, $[[T1]], $[[T0]] ; M4: dmult $4, $5 ; M4: mflo $2 @@ -184,6 +205,21 @@ entry: ; 64R6: dmul $2, $4, $5 + ; MM32R3: multu $[[T0:[0-9]+]], $7 + ; MM32R3: mflo $[[T1:[0-9]+]] + ; MM32R3: mfhi $[[T2:[0-9]+]] + ; MM32R3: mul $[[T3:[0-9]+]], $4, $7 + ; MM32R3: mul $[[T0]], $[[T0]], $6 + ; MM32R3: addu16 $[[T2]], $[[T2]], $[[T0]] + ; MM32R3: addu16 $2, $[[T2]], $[[T3]] + + ; MM32R6: mul $[[T0:[0-9]+]], $5, $7 + ; MM32R6: mul $[[T1:[0-9]+]], $4, $7 + ; MM32R6: mul $[[T2:[0-9]+]], $5, $6 + ; MM32R6: muhu $[[T3:[0-9]+]], $5, $7 + ; MM32R6: addu16 $[[T2]], $[[T3]], $[[T2]] + ; MM32R6: addu16 $2, $[[T2]], $[[T1]] + %r = mul i64 %a, %b ret i64 %r } @@ -204,12 +240,14 @@ entry: ; GP64-NOT-R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]] ; GP64-NOT-R6: daddu $2, $[[T3:[0-9]+]], $[[T0]] - ; 64R6: dmul $[[T0:[0-9]+]], $5, $6 - ; 64R6: dmuhu $[[T1:[0-9]+]], $5, $7 - ; 64R6: daddu $[[T2:[0-9]+]], $[[T1]], $[[T0]] - ; 64R6: dmul $[[T3:[0-9]+]], $4, $7 - ; 64R6: daddu $2, $[[T2]], $[[T3]] - ; 64R6: dmul $3, $5, $7 + ; 64R6-DAG: dmul $3, $5, $7 + ; 64R6-DAG: dmul $[[T0:[0-9]+]], $4, $7 + ; 64R6-DAG: dmul $[[T1:[0-9]+]], $5, $6 + ; 64R6: dmuhu $[[T2:[0-9]+]], $5, $7 + ; 64R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]] + ; 64R6: daddu $2, $[[T1]], $[[T0]] + + ; MM32: lw $25, %call16(__multi3)($2) %r = mul i128 %a, %b ret i128 %r diff --git a/test/CodeGen/Mips/llvm-ir/not.ll b/test/CodeGen/Mips/llvm-ir/not.ll new file mode 100644 index 000000000000..5f7374f6dfbb --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/not.ll @@ -0,0 +1,239 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM64 + +define signext i1 @not_i1(i1 signext %a) { +entry: +; ALL-LABEL: not_i1: + + ; GP32: not $2, $4 + + ; GP64: not $2, $4 + + ; MM: not16 $2, $4 + + %r = xor i1 %a, -1 + ret i1 %r +} + +define signext i8 @not_i8(i8 signext %a) { +entry: +; ALL-LABEL: not_i8: + + ; GP32: not $2, $4 + + ; GP64: not $2, $4 + + ; MM: not16 $2, $4 + + %r = xor i8 %a, -1 + ret i8 %r +} + +define signext i16 @not_i16(i16 signext %a) { +entry: +; ALL-LABEL: not_i16: + + ; GP32: not $2, $4 + + ; GP64: not $2, $4 + + ; MM: not16 $2, $4 + + %r = xor i16 %a, -1 + ret i16 %r +} + +define signext i32 @not_i32(i32 signext %a) { +entry: +; ALL-LABEL: not_i32: + + ; GP32: not $2, $4 + + ; GP64: not $2, $4 + + ; MM: not16 $2, $4 + + %r = xor i32 %a, -1 + ret i32 %r +} + +define signext i64 @not_i64(i64 signext %a) { +entry: +; ALL-LABEL: not_i64: + + ; GP32: not $2, $4 + ; GP32: not $3, $5 + + ; GP64: daddiu $[[T0:[0-9]+]], $zero, -1 + ; GP64: xor $2, $4, $[[T0]] + + ; MM32: not16 $2, $4 + ; MM32: not16 $3, $5 + + ; MM64: daddiu $[[T0:[0-9]+]], $zero, -1 + ; MM64: xor $2, $4, $[[T0]] + + %r = xor i64 %a, -1 + ret i64 %r +} + +define signext i128 @not_i128(i128 signext %a) { +entry: +; ALL-LABEL: not_i128: + + ; GP32: not $2, $4 + ; GP32: not $3, $5 + ; GP32: not $4, $6 + ; GP32: not $5, $7 + + ; GP64: daddiu $[[T0:[0-9]+]], $zero, -1 + ; GP64: xor $2, $4, $[[T0]] + ; GP64: xor $3, $5, $[[T0]] + + ; MM32: not16 $2, $4 + ; MM32: not16 $3, $5 + ; MM32: not16 $4, $6 + ; MM32: not16 $5, $7 + + ; MM64: daddiu $[[T0:[0-9]+]], $zero, -1 + ; MM64: xor $2, $4, $[[T0]] + ; MM64: xor $3, $5, $[[T0]] + + %r = xor i128 %a, -1 + ret i128 %r +} + +define signext i1 @nor_i1(i1 signext %a, i1 signext %b) { +entry: +; ALL-LABEL: nor_i1: + + ; ALL: nor $2, $5, $4 + + %or = or i1 %b, %a + %r = xor i1 %or, -1 + ret i1 %r +} + +define signext i8 @nor_i8(i8 signext %a, i8 signext %b) { +entry: +; ALL-LABEL: nor_i8: + + ; ALL: nor $2, $5, $4 + + %or = or i8 %b, %a + %r = xor i8 %or, -1 + ret i8 %r +} + +define signext i16 @nor_i16(i16 signext %a, i16 signext %b) { +entry: +; ALL-LABEL: nor_i16: + + ; ALL: nor $2, $5, $4 + + %or = or i16 %b, %a + %r = xor i16 %or, -1 + ret i16 %r +} + +define signext i32 @nor_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: nor_i32: + + ; GP32: nor $2, $5, $4 + + ; GP64: or $[[T0:[0-9]+]], $5, $4 + ; GP64: sll $[[T1:[0-9]+]], $[[T0]], 0 + ; GP64: not $2, $[[T1]] + + ; MM32: nor $2, $5, $4 + + ; MM64: or $[[T0:[0-9]+]], $5, $4 + ; MM64: sll $[[T1:[0-9]+]], $[[T0]], 0 + ; MM64: not16 $2, $[[T1]] + + %or = or i32 %b, %a + %r = xor i32 %or, -1 + ret i32 %r +} + + +define signext i64 @nor_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: nor_i64: + + ; GP32: nor $2, $6, $4 + ; GP32: nor $3, $7, $5 + + ; GP64: nor $2, $5, $4 + + ; MM32: nor $2, $6, $4 + ; MM32: nor $3, $7, $5 + + ; MM64: nor $2, $5, $4 + + %or = or i64 %b, %a + %r = xor i64 %or, -1 + ret i64 %r +} + +define signext i128 @nor_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: nor_i128: + + ; GP32: lw $[[T0:[0-9]+]], 24($sp) + ; GP32: lw $[[T1:[0-9]+]], 20($sp) + ; GP32: lw $[[T2:[0-9]+]], 16($sp) + ; GP32: nor $2, $[[T2]], $4 + ; GP32: nor $3, $[[T1]], $5 + ; GP32: nor $4, $[[T0]], $6 + ; GP32: lw $[[T3:[0-9]+]], 28($sp) + ; GP32: nor $5, $[[T3]], $7 + + ; GP64: nor $2, $6, $4 + ; GP64: nor $3, $7, $5 + + ; MM32: lw $[[T0:[0-9]+]], 20($sp) + ; MM32: lw $[[T1:[0-9]+]], 16($sp) + ; MM32: nor $2, $[[T1]], $4 + ; MM32: nor $3, $[[T0]], $5 + ; MM32: lw $[[T2:[0-9]+]], 24($sp) + ; MM32: nor $4, $[[T2]], $6 + ; MM32: lw $[[T3:[0-9]+]], 28($sp) + ; MM32: nor $5, $[[T3]], $7 + + ; MM64: nor $2, $6, $4 + ; MM64: nor $3, $7, $5 + + %or = or i128 %b, %a + %r = xor i128 %or, -1 + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/or.ll b/test/CodeGen/Mips/llvm-ir/or.ll index 8509d6ce93f3..192e5de62301 100644 --- a/test/CodeGen/Mips/llvm-ir/or.ll +++ b/test/CodeGen/Mips/llvm-ir/or.ll @@ -1,35 +1,33 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM64 define signext i1 @or_i1(i1 signext %a, i1 signext %b) { entry: ; ALL-LABEL: or_i1: - ; ALL: or $2, $4, $5 + ; GP32: or $2, $4, $5 + + ; GP64: or $2, $4, $5 + + ; MM: or16 $[[T0:[0-9]+]], $5 + ; MM: move $2, $[[T0]] %r = or i1 %a, %b ret i1 %r @@ -39,7 +37,12 @@ define signext i8 @or_i8(i8 signext %a, i8 signext %b) { entry: ; ALL-LABEL: or_i8: - ; ALL: or $2, $4, $5 + ; GP32: or $2, $4, $5 + + ; GP64: or $2, $4, $5 + + ; MM: or16 $[[T0:[0-9]+]], $5 + ; MM: move $2, $[[T0]] %r = or i8 %a, %b ret i8 %r @@ -49,7 +52,12 @@ define signext i16 @or_i16(i16 signext %a, i16 signext %b) { entry: ; ALL-LABEL: or_i16: - ; ALL: or $2, $4, $5 + ; GP32: or $2, $4, $5 + + ; GP64: or $2, $4, $5 + + ; MM: or16 $[[T0:[0-9]+]], $5 + ; MM: move $2, $[[T0]] %r = or i16 %a, %b ret i16 %r @@ -59,12 +67,18 @@ define signext i32 @or_i32(i32 signext %a, i32 signext %b) { entry: ; ALL-LABEL: or_i32: - ; GP32: or $2, $4, $5 + ; GP32: or $2, $4, $5 - ; GP64: or $[[T0:[0-9]+]], $4, $5 + ; GP64: or $[[T0:[0-9]+]], $4, $5 ; FIXME: The sll instruction below is redundant. ; GP64: sll $2, $[[T0]], 0 + ; MM32: or16 $[[T0:[0-9]+]], $5 + ; MM32: move $2, $[[T0]] + + ; MM64: or $[[T0:[0-9]+]], $4, $5 + ; MM64: sll $2, $[[T0]], 0 + %r = or i32 %a, %b ret i32 %r } @@ -73,10 +87,17 @@ define signext i64 @or_i64(i64 signext %a, i64 signext %b) { entry: ; ALL-LABEL: or_i64: - ; GP32: or $2, $4, $6 - ; GP32: or $3, $5, $7 + ; GP32: or $2, $4, $6 + ; GP32: or $3, $5, $7 + + ; GP64: or $2, $4, $5 - ; GP64: or $2, $4, $5 + ; MM32: or16 $[[T0:[0-9]+]], $6 + ; MM32: or16 $[[T1:[0-9]+]], $7 + ; MM32: move $2, $[[T0]] + ; MM32: move $3, $[[T1]] + + ; MM64: or $2, $4, $5 %r = or i64 %a, %b ret i64 %r @@ -86,18 +107,557 @@ define signext i128 @or_i128(i128 signext %a, i128 signext %b) { entry: ; ALL-LABEL: or_i128: - ; GP32: lw $[[T0:[0-9]+]], 24($sp) - ; GP32: lw $[[T1:[0-9]+]], 20($sp) - ; GP32: lw $[[T2:[0-9]+]], 16($sp) - ; GP32: or $2, $4, $[[T2]] - ; GP32: or $3, $5, $[[T1]] - ; GP32: or $4, $6, $[[T0]] - ; GP32: lw $[[T3:[0-9]+]], 28($sp) - ; GP32: or $5, $7, $[[T3]] + ; GP32: lw $[[T0:[0-9]+]], 24($sp) + ; GP32: lw $[[T1:[0-9]+]], 20($sp) + ; GP32: lw $[[T2:[0-9]+]], 16($sp) + ; GP32: or $2, $4, $[[T2]] + ; GP32: or $3, $5, $[[T1]] + ; GP32: or $4, $6, $[[T0]] + ; GP32: lw $[[T3:[0-9]+]], 28($sp) + ; GP32: or $5, $7, $[[T3]] + + ; GP64: or $2, $4, $6 + ; GP64: or $3, $5, $7 + + ; MM32: lw $[[T0:[0-9]+]], 20($sp) + ; MM32: lw $[[T1:[0-9]+]], 16($sp) + ; MM32: or16 $[[T1]], $4 + ; MM32: or16 $[[T0]], $5 + ; MM32: lw $[[T2:[0-9]+]], 24($sp) + ; MM32: or16 $[[T2]], $6 + ; MM32: lw $[[T3:[0-9]+]], 28($sp) + ; MM32: or16 $[[T3]], $7 - ; GP64: or $2, $4, $6 - ; GP64: or $3, $5, $7 + ; MM64: or $2, $4, $6 + ; MM64: or $3, $5, $7 %r = or i128 %a, %b ret i128 %r } + +define signext i1 @or_i1_4(i1 signext %b) { +entry: +; ALL-LABEL: or_i1_4: + + ; ALL: move $2, $4 + + %r = or i1 4, %b + ret i1 %r +} + +define signext i8 @or_i8_4(i8 signext %b) { +entry: +; ALL-LABEL: or_i8_4: + + ; ALL: ori $2, $4, 4 + + %r = or i8 4, %b + ret i8 %r +} + +define signext i16 @or_i16_4(i16 signext %b) { +entry: +; ALL-LABEL: or_i16_4: + + ; ALL: ori $2, $4, 4 + + %r = or i16 4, %b + ret i16 %r +} + +define signext i32 @or_i32_4(i32 signext %b) { +entry: +; ALL-LABEL: or_i32_4: + + ; ALL: ori $2, $4, 4 + + %r = or i32 4, %b + ret i32 %r +} + +define signext i64 @or_i64_4(i64 signext %b) { +entry: +; ALL-LABEL: or_i64_4: + + ; GP32: ori $3, $5, 4 + ; GP32: move $2, $4 + + ; GP64: ori $2, $4, 4 + + ; MM32: ori $3, $5, 4 + ; MM32: move $2, $4 + + ; MM64: ori $2, $4, 4 + + %r = or i64 4, %b + ret i64 %r +} + +define signext i128 @or_i128_4(i128 signext %b) { +entry: +; ALL-LABEL: or_i128_4: + + ; GP32: ori $[[T0:[0-9]+]], $7, 4 + ; GP32: move $2, $4 + ; GP32: move $3, $5 + ; GP32: move $4, $6 + ; GP32: move $5, $[[T0]] + + ; GP64: ori $3, $5, 4 + ; GP64: move $2, $4 + + ; MM32: ori $[[T0:[0-9]+]], $7, 4 + ; MM32: move $2, $4 + ; MM32: move $3, $5 + ; MM32: move $4, $6 + ; MM32: move $5, $[[T0]] + + ; MM64: ori $3, $5, 4 + ; MM64: move $2, $4 + + %r = or i128 4, %b + ret i128 %r +} + +define signext i1 @or_i1_31(i1 signext %b) { +entry: +; ALL-LABEL: or_i1_31: + + ; GP32: addiu $2, $zero, -1 + + ; GP64: addiu $2, $zero, -1 + + ; MM: li16 $2, -1 + + %r = or i1 31, %b + ret i1 %r +} + +define signext i8 @or_i8_31(i8 signext %b) { +entry: +; ALL-LABEL: or_i8_31: + + ; ALL: ori $2, $4, 31 + + %r = or i8 31, %b + ret i8 %r +} + +define signext i16 @or_i16_31(i16 signext %b) { +entry: +; ALL-LABEL: or_i16_31: + + ; ALL: ori $2, $4, 31 + + %r = or i16 31, %b + ret i16 %r +} + +define signext i32 @or_i32_31(i32 signext %b) { +entry: +; ALL-LABEL: or_i32_31: + + ; ALL: ori $2, $4, 31 + + %r = or i32 31, %b + ret i32 %r +} + +define signext i64 @or_i64_31(i64 signext %b) { +entry: +; ALL-LABEL: or_i64_31: + + ; GP32: ori $3, $5, 31 + ; GP32: move $2, $4 + + ; GP64: ori $2, $4, 31 + + ; MM32: ori $3, $5, 31 + ; MM32: move $2, $4 + + ; MM64: ori $2, $4, 31 + + %r = or i64 31, %b + ret i64 %r +} + +define signext i128 @or_i128_31(i128 signext %b) { +entry: +; ALL-LABEL: or_i128_31: + + ; GP32: ori $[[T0:[0-9]+]], $7, 31 + ; GP32: move $2, $4 + ; GP32: move $3, $5 + ; GP32: move $4, $6 + ; GP32: move $5, $[[T0]] + + ; GP64: ori $3, $5, 31 + ; GP64: move $2, $4 + + ; MM32: ori $[[T0:[0-9]+]], $7, 31 + ; MM32: move $2, $4 + ; MM32: move $3, $5 + ; MM32: move $4, $6 + ; MM32: move $5, $[[T0]] + + ; MM64: ori $3, $5, 31 + ; MM64: move $2, $4 + + %r = or i128 31, %b + ret i128 %r +} + +define signext i1 @or_i1_255(i1 signext %b) { +entry: +; ALL-LABEL: or_i1_255: + + ; GP32: addiu $2, $zero, -1 + + ; GP64: addiu $2, $zero, -1 + + ; MM: li16 $2, -1 + + %r = or i1 255, %b + ret i1 %r +} + +define signext i8 @or_i8_255(i8 signext %b) { +entry: +; ALL-LABEL: or_i8_255: + + ; GP32: addiu $2, $zero, -1 + + ; GP64: addiu $2, $zero, -1 + + ; MM: li16 $2, -1 + + %r = or i8 255, %b + ret i8 %r +} + +define signext i16 @or_i16_255(i16 signext %b) { +entry: +; ALL-LABEL: or_i16_255: + + ; ALL: ori $2, $4, 255 + + %r = or i16 255, %b + ret i16 %r +} + +define signext i32 @or_i32_255(i32 signext %b) { +entry: +; ALL-LABEL: or_i32_255: + + ; ALL: ori $2, $4, 255 + + %r = or i32 255, %b + ret i32 %r +} + +define signext i64 @or_i64_255(i64 signext %b) { +entry: +; ALL-LABEL: or_i64_255: + + ; GP32: ori $3, $5, 255 + ; GP32: move $2, $4 + + ; GP64: ori $2, $4, 255 + + ; MM32: ori $3, $5, 255 + ; MM32: move $2, $4 + + ; MM64: ori $2, $4, 255 + + %r = or i64 255, %b + ret i64 %r +} + +define signext i128 @or_i128_255(i128 signext %b) { +entry: +; ALL-LABEL: or_i128_255: + + ; GP32: ori $[[T0:[0-9]+]], $7, 255 + ; GP32: move $2, $4 + ; GP32: move $3, $5 + ; GP32: move $4, $6 + ; GP32: move $5, $[[T0]] + + ; GP64: ori $3, $5, 255 + ; GP64: move $2, $4 + + ; MM32: ori $[[T0:[0-9]+]], $7, 255 + ; MM32: move $2, $4 + ; MM32: move $3, $5 + ; MM32: move $4, $6 + ; MM32: move $5, $[[T0]] + + ; MM64: ori $3, $5, 255 + ; MM64: move $2, $4 + + %r = or i128 255, %b + ret i128 %r +} + +define signext i1 @or_i1_32768(i1 signext %b) { +entry: +; ALL-LABEL: or_i1_32768: + + ; ALL: move $2, $4 + + %r = or i1 32768, %b + ret i1 %r +} + +define signext i8 @or_i8_32768(i8 signext %b) { +entry: +; ALL-LABEL: or_i8_32768: + + ; ALL: move $2, $4 + + %r = or i8 32768, %b + ret i8 %r +} + +define signext i16 @or_i16_32768(i16 signext %b) { +entry: +; ALL-LABEL: or_i16_32768: + + ; GP32: addiu $[[T0:[0-9]+]], $zero, -32768 + ; GP32: or $2, $4, $[[T0]] + + ; GP64: addiu $[[T0:[0-9]+]], $zero, -32768 + ; GP64: or $2, $4, $[[T0]] + + ; MM: addiu $2, $zero, -32768 + ; MM: or16 $2, $4 + + %r = or i16 32768, %b + ret i16 %r +} + +define signext i32 @or_i32_32768(i32 signext %b) { +entry: +; ALL-LABEL: or_i32_32768: + + ; ALL: ori $2, $4, 32768 + + %r = or i32 32768, %b + ret i32 %r +} + +define signext i64 @or_i64_32768(i64 signext %b) { +entry: +; ALL-LABEL: or_i64_32768: + + ; GP32: ori $3, $5, 32768 + ; GP32: move $2, $4 + + ; GP64: ori $2, $4, 32768 + + ; MM32: ori $3, $5, 32768 + ; MM32: move $2, $4 + + ; MM64: ori $2, $4, 32768 + + %r = or i64 32768, %b + ret i64 %r +} + +define signext i128 @or_i128_32768(i128 signext %b) { +entry: +; ALL-LABEL: or_i128_32768: + + ; GP32: ori $[[T0:[0-9]+]], $7, 32768 + ; GP32: move $2, $4 + ; GP32: move $3, $5 + ; GP32: move $4, $6 + ; GP32: move $5, $[[T0]] + + ; GP64: ori $3, $5, 32768 + ; GP64: move $2, $4 + + ; MM32: ori $[[T0:[0-9]+]], $7, 32768 + ; MM32: move $2, $4 + ; MM32: move $3, $5 + ; MM32: move $4, $6 + ; MM32: move $5, $[[T0]] + + ; MM64: ori $3, $5, 32768 + ; MM64: move $2, $4 + + %r = or i128 32768, %b + ret i128 %r +} + +define signext i1 @or_i1_65(i1 signext %b) { +entry: +; ALL-LABEL: or_i1_65: + + ; GP32: addiu $2, $zero, -1 + + ; GP64: addiu $2, $zero, -1 + + ; MM: li16 $2, -1 + + %r = or i1 65, %b + ret i1 %r +} + +define signext i8 @or_i8_65(i8 signext %b) { +entry: +; ALL-LABEL: or_i8_65: + + ; ALL: ori $2, $4, 65 + + %r = or i8 65, %b + ret i8 %r +} + +define signext i16 @or_i16_65(i16 signext %b) { +entry: +; ALL-LABEL: or_i16_65: + + ; ALL: ori $2, $4, 65 + + %r = or i16 65, %b + ret i16 %r +} + +define signext i32 @or_i32_65(i32 signext %b) { +entry: +; ALL-LABEL: or_i32_65: + + ; ALL: ori $2, $4, 65 + + %r = or i32 65, %b + ret i32 %r +} + +define signext i64 @or_i64_65(i64 signext %b) { +entry: +; ALL-LABEL: or_i64_65: + + ; GP32: ori $3, $5, 65 + ; GP32: move $2, $4 + + ; GP64: ori $2, $4, 65 + + ; MM32: ori $3, $5, 65 + ; MM32: move $2, $4 + + ; MM64: ori $2, $4, 65 + + %r = or i64 65, %b + ret i64 %r +} + +define signext i128 @or_i128_65(i128 signext %b) { +entry: +; ALL-LABEL: or_i128_65: + + ; GP32: ori $[[T0:[0-9]+]], $7, 65 + ; GP32: move $2, $4 + ; GP32: move $3, $5 + ; GP32: move $4, $6 + ; GP32: move $5, $[[T0]] + + ; GP64: ori $3, $5, 65 + ; GP64: move $2, $4 + + ; MM32: ori $[[T0:[0-9]+]], $7, 65 + ; MM32: move $2, $4 + ; MM32: move $3, $5 + ; MM32: move $4, $6 + ; MM32: move $5, $[[T0]] + + ; MM64: ori $3, $5, 65 + ; MM64: move $2, $4 + + %r = or i128 65, %b + ret i128 %r +} + +define signext i1 @or_i1_256(i1 signext %b) { +entry: +; ALL-LABEL: or_i1_256: + + ; ALL: move $2, $4 + + %r = or i1 256, %b + ret i1 %r +} + +define signext i8 @or_i8_256(i8 signext %b) { +entry: +; ALL-LABEL: or_i8_256: + + ; ALL: move $2, $4 + + %r = or i8 256, %b + ret i8 %r +} + +define signext i16 @or_i16_256(i16 signext %b) { +entry: +; ALL-LABEL: or_i16_256: + + ; ALL: ori $2, $4, 256 + + %r = or i16 256, %b + ret i16 %r +} + +define signext i32 @or_i32_256(i32 signext %b) { +entry: +; ALL-LABEL: or_i32_256: + + ; ALL: ori $2, $4, 256 + + %r = or i32 256, %b + ret i32 %r +} + +define signext i64 @or_i64_256(i64 signext %b) { +entry: +; ALL-LABEL: or_i64_256: + + ; GP32: ori $3, $5, 256 + ; GP32: move $2, $4 + + ; GP64: ori $2, $4, 256 + + ; MM32: ori $3, $5, 256 + ; MM32: move $2, $4 + + ; MM64: ori $2, $4, 256 + + %r = or i64 256, %b + ret i64 %r +} + +define signext i128 @or_i128_256(i128 signext %b) { +entry: +; ALL-LABEL: or_i128_256: + + ; GP32: ori $[[T0:[0-9]+]], $7, 256 + ; GP32: move $2, $4 + ; GP32: move $3, $5 + ; GP32: move $4, $6 + ; GP32: move $5, $[[T0]] + + ; GP64: ori $3, $5, 256 + ; GP64: move $2, $4 + + ; MM32: ori $[[T0:[0-9]+]], $7, 256 + ; MM32: move $2, $4 + ; MM32: move $3, $5 + ; MM32: move $4, $6 + ; MM32: move $5, $[[T0]] + + ; MM64: ori $3, $5, 256 + ; MM64: move $2, $4 + + %r = or i128 256, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/ret.ll b/test/CodeGen/Mips/llvm-ir/ret.ll index 0561c24219ce..9be80dc200fa 100644 --- a/test/CodeGen/Mips/llvm-ir/ret.ll +++ b/test/CodeGen/Mips/llvm-ir/ret.ll @@ -7,23 +7,30 @@ ; affects it and it's undesirable to repeat the non-pointer returns for each ; relocation model. -; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=NO-MTHC1 -check-prefix=NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=R6 -; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=R6 +; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,NO-MTHC1,NOT-R6 +; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6 +; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6 +; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6 +; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,R6C +; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 + +; FIXME: for the test ret_double_0x0, the delay slot of jr cannot be filled +; as mthc1 has unmodeled side effects. This is an artifact of our backend. +; Force the delay slot filler off to check that the sequence jr $ra; nop is +; turned into jic 0, $ra. + +; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C define void @ret_void() { ; ALL-LABEL: ret_void: ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR +; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC ret void } @@ -173,6 +180,7 @@ define float @ret_float_0x3() { ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR +; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC ; float constants are written as double constants ret float 0x36b8000000000000 @@ -191,6 +199,7 @@ define double @ret_double_0x0() { ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR +; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC ret double 0x0000000000000000 } @@ -204,6 +213,7 @@ define double @ret_double_0x3() { ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR +; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC ret double 0x0000000000000003 } diff --git a/test/CodeGen/Mips/llvm-ir/sdiv.ll b/test/CodeGen/Mips/llvm-ir/sdiv.ll index 929ee88bb7f7..2d2b8ff12c04 100644 --- a/test/CodeGen/Mips/llvm-ir/sdiv.ll +++ b/test/CodeGen/Mips/llvm-ir/sdiv.ll @@ -1,29 +1,37 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=R6 -check-prefix=GP32 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=R6 -check-prefix=64R6 +; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,NOT-R2-R6,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,NOT-R2-R6,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,R6,GP32 + +; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,NOT-R2-R6,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,NOT-R2-R6,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,NOT-R2-R6,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,R6,64R6 + +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR3,MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM64 define signext i1 @sdiv_i1(i1 signext %a, i1 signext %b) { entry: @@ -42,6 +50,17 @@ entry: ; R6: sll $[[T1:[0-9]+]], $[[T0]], 31 ; R6: sra $2, $[[T1]], 31 + ; MMR3: div $zero, $4, $5 + ; MMR3: teq $5, $zero, 7 + ; MMR3: mflo $[[T0:[0-9]+]] + ; MMR3: sll $[[T1:[0-9]+]], $[[T0]], 31 + ; MMR3: sra $2, $[[T1]], 31 + + ; MMR6: div $[[T0:[0-9]+]], $4, $5 + ; MMR6: teq $5, $zero, 7 + ; MMR6: sll $[[T1:[0-9]+]], $[[T0]], 31 + ; MMR6: sra $2, $[[T1]], 31 + %r = sdiv i1 %a, %b ret i1 %r } @@ -68,6 +87,15 @@ entry: ; FIXME: This instruction is redundant. ; R6: seb $2, $[[T0]] + ; MMR3: div $zero, $4, $5 + ; MMR3: teq $5, $zero, 7 + ; MMR3: mflo $[[T0:[0-9]+]] + ; MMR3: seb $2, $[[T0]] + + ; MMR6: div $[[T0:[0-9]+]], $4, $5 + ; MMR6: teq $5, $zero, 7 + ; MMR6: seb $2, $[[T0]] + %r = sdiv i8 %a, %b ret i8 %r } @@ -94,6 +122,15 @@ entry: ; FIXME: This is instruction is redundant since div is signed. ; R6: seh $2, $[[T0]] + ; MMR3: div $zero, $4, $5 + ; MMR3: teq $5, $zero, 7 + ; MMR3: mflo $[[T0:[0-9]+]] + ; MMR3: seh $2, $[[T0]] + + ; MMR6: div $[[T0:[0-9]+]], $4, $5 + ; MMR6: teq $5, $zero, 7 + ; MMR6: seh $2, $[[T0]] + %r = sdiv i16 %a, %b ret i16 %r } @@ -109,6 +146,13 @@ entry: ; R6: div $2, $4, $5 ; R6: teq $5, $zero, 7 + ; MMR3: div $zero, $4, $5 + ; MMR3: teq $5, $zero, 7 + ; MMR3: mflo $2 + + ; MMR6: div $2, $4, $5 + ; MMR6: teq $5, $zero, 7 + %r = sdiv i32 %a, %b ret i32 %r } @@ -126,6 +170,11 @@ entry: ; 64R6: ddiv $2, $4, $5 ; 64R6: teq $5, $zero, 7 + ; MM32: lw $25, %call16(__divdi3)($2) + + ; MM64: ddiv $2, $4, $5 + ; MM64: teq $5, $zero, 7 + %r = sdiv i64 %a, %b ret i64 %r } @@ -134,11 +183,15 @@ define signext i128 @sdiv_i128(i128 signext %a, i128 signext %b) { entry: ; ALL-LABEL: sdiv_i128: - ; GP32: lw $25, %call16(__divti3)($gp) + ; GP32: lw $25, %call16(__divti3)($gp) + + ; GP64-NOT-R6: ld $25, %call16(__divti3)($gp) + ; 64R6: ld $25, %call16(__divti3)($gp) + + ; MM32: lw $25, %call16(__divti3)($2) - ; GP64-NOT-R6: ld $25, %call16(__divti3)($gp) - ; 64R6: ld $25, %call16(__divti3)($gp) + ; MM64: ld $25, %call16(__divti3)($2) - %r = sdiv i128 %a, %b - ret i128 %r + %r = sdiv i128 %a, %b + ret i128 %r } diff --git a/test/CodeGen/Mips/llvm-ir/select-dbl.ll b/test/CodeGen/Mips/llvm-ir/select-dbl.ll new file mode 100644 index 000000000000..1ca5b4e054ba --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/select-dbl.ll @@ -0,0 +1,358 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,M2,M2-M3 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R1 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefixes=ALL,SEL-32,32R6 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefixes=ALL,M3,M2-M3 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefixes=ALL,SEL-64,64R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM32R3 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM32R6,SEL-32 + +define double @tst_select_i1_double(i1 signext %s, double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_i1_double: + + ; M2: andi $[[T0:[0-9]+]], $4, 1 + ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: ldc1 $f0, 16($sp) + ; M2: jr $ra + ; M2: nop + ; M2: $[[BB0]]: + ; M2: mtc1 $7, $f0 + ; M2: jr $ra + ; M2: mtc1 $6, $f1 + + ; CMOV-32: mtc1 $7, $[[F0:f[0-9]+]] + ; CMOV-32R1: mtc1 $6, $f{{[0-9]+}} + ; CMOV-32R2-R5: mthc1 $6, $[[F0]] + ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-32: ldc1 $f0, 16($sp) + ; CMOV-32: movn.d $f0, $[[F0]], $[[T0]] + + ; SEL-32: mtc1 $7, $[[F0:f[0-9]+]] + ; SEL-32: mthc1 $6, $[[F0]] + ; SEL-32: ldc1 $[[F1:f[0-9]+]], 16($sp) + ; SEL-32: mtc1 $4, $f0 + ; SEL-32: sel.d $f0, $[[F1]], $[[F0]] + + ; M3: andi $[[T0:[0-9]+]], $4, 1 + ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M3: nop + ; M3: mov.d $f13, $f14 + ; M3: $[[BB0]]: + ; M3: jr $ra + ; M3: mov.d $f0, $f13 + + ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-64: movn.d $f14, $f13, $[[T0]] + ; CMOV-64: mov.d $f0, $f14 + + ; SEL-64: mtc1 $4, $f0 + ; SEL-64: sel.d $f0, $f14, $f13 + + ; MM32R3: mtc1 $7, $[[F0:f[0-9]+]] + ; MM32R3: mthc1 $6, $[[F0]] + ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1 + ; MM32R3: ldc1 $f0, 16($sp) + ; MM32R3: movn.d $f0, $[[F0]], $[[T0]] + + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_i1_double_reordered(double %x, double %y, + i1 signext %s) { +entry: + ; ALL-LABEL: tst_select_i1_double_reordered: + + ; M2: lw $[[T0:[0-9]+]], 16($sp) + ; M2: andi $[[T1:[0-9]+]], $[[T0]], 1 + ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: mov.d $f12, $f14 + ; M2: $[[BB0]]: + ; M2: jr $ra + ; M2: mov.d $f0, $f12 + + ; CMOV-32: lw $[[T0:[0-9]+]], 16($sp) + ; CMOV-32: andi $[[T1:[0-9]+]], $[[T0]], 1 + ; CMOV-32: movn.d $f14, $f12, $[[T1]] + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: lw $[[T0:[0-9]+]], 16($sp) + ; SEL-32: mtc1 $[[T0]], $f0 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; M3: andi $[[T0:[0-9]+]], $6, 1 + ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M3: nop + ; M3: mov.d $f12, $f13 + ; M3: $[[BB0]]: + ; M3: jr $ra + ; M3: mov.d $f0, $f12 + + ; CMOV-64: andi $[[T0:[0-9]+]], $6, 1 + ; CMOV-64: movn.d $f13, $f12, $[[T0]] + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: mtc1 $6, $f0 + ; SEL-64: sel.d $f0, $f13, $f12 + + ; MM32R3: lw $[[T0:[0-9]+]], 16($sp) + ; MM32R3: andi16 $[[T1:[0-9]+]], $[[T0:[0-9]+]], 1 + ; MM32R3: movn.d $f14, $f12, $[[T1]] + ; MM32R3: mov.d $f0, $f14 + + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_fcmp_olt_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_olt_double: + + ; M2: c.olt.d $f12, $f14 + ; M3: c.olt.d $f12, $f13 + ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.d $f12, $f14 + ; M3: mov.d $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.d $f0, $f12 + + ; CMOV-32: c.olt.d $f12, $f14 + ; CMOV-32: movt.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.lt.d $f0, $f12, $f14 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.olt.d $f12, $f13 + ; CMOV-64: movt.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.lt.d $f0, $f12, $f13 + ; SEL-64: sel.d $f0, $f13, $f12 + + ; MM32R3: c.olt.d $f12, $f14 + ; MM32R3: movt.d $f14, $f12, $fcc0 + ; MM32R3: mov.d $f0, $f14 + + %s = fcmp olt double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_fcmp_ole_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_ole_double: + + ; M2: c.ole.d $f12, $f14 + ; M3: c.ole.d $f12, $f13 + ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.d $f12, $f14 + ; M3: mov.d $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.d $f0, $f12 + + ; CMOV-32: c.ole.d $f12, $f14 + ; CMOV-32: movt.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.le.d $f0, $f12, $f14 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.ole.d $f12, $f13 + ; CMOV-64: movt.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.le.d $f0, $f12, $f13 + ; SEL-64: sel.d $f0, $f13, $f12 + + ; MM32R3: c.ole.d $f12, $f14 + ; MM32R3: movt.d $f14, $f12, $fcc0 + ; MM32R3: mov.d $f0, $f14 + + %s = fcmp ole double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_fcmp_ogt_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_ogt_double: + + ; M2: c.ule.d $f12, $f14 + ; M3: c.ule.d $f12, $f13 + ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.d $f12, $f14 + ; M3: mov.d $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.d $f0, $f12 + + ; CMOV-32: c.ule.d $f12, $f14 + ; CMOV-32: movf.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.lt.d $f0, $f14, $f12 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.ule.d $f12, $f13 + ; CMOV-64: movf.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.lt.d $f0, $f13, $f12 + ; SEL-64: sel.d $f0, $f13, $f12 + + ; MM32R3: c.ule.d $f12, $f14 + ; MM32R3: movf.d $f14, $f12, $fcc0 + ; MM32R3: mov.d $f0, $f14 + + %s = fcmp ogt double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_fcmp_oge_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_oge_double: + + ; M2: c.ult.d $f12, $f14 + ; M3: c.ult.d $f12, $f13 + ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.d $f12, $f14 + ; M3: mov.d $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.d $f0, $f12 + + ; CMOV-32: c.ult.d $f12, $f14 + ; CMOV-32: movf.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.le.d $f0, $f14, $f12 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.ult.d $f12, $f13 + ; CMOV-64: movf.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.le.d $f0, $f13, $f12 + ; SEL-64: sel.d $f0, $f13, $f12 + + ; MM32R3: c.ult.d $f12, $f14 + ; MM32R3: movf.d $f14, $f12, $fcc0 + ; MM32R3: mov.d $f0, $f14 + + %s = fcmp oge double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_fcmp_oeq_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_oeq_double: + + ; M2: c.eq.d $f12, $f14 + ; M3: c.eq.d $f12, $f13 + ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.d $f12, $f14 + ; M3: mov.d $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.d $f0, $f12 + + ; CMOV-32: c.eq.d $f12, $f14 + ; CMOV-32: movt.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.eq.d $f0, $f12, $f14 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.eq.d $f12, $f13 + ; CMOV-64: movt.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.eq.d $f0, $f12, $f13 + ; SEL-64: sel.d $f0, $f13, $f12 + + ; MM32R3: c.eq.d $f12, $f14 + ; MM32R3: movt.d $f14, $f12, $fcc0 + ; MM32R3: mov.d $f0, $f14 + + %s = fcmp oeq double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_fcmp_one_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_one_double: + + ; M2: c.ueq.d $f12, $f14 + ; M3: c.ueq.d $f12, $f13 + ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.d $f12, $f14 + ; M3: mov.d $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.d $f0, $f12 + + ; CMOV-32: c.ueq.d $f12, $f14 + ; CMOV-32: movf.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.ueq.d $f0, $f12, $f14 + ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0 + ; SEL-32: not $[[T0]], $[[T0]] + ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.ueq.d $f12, $f13 + ; CMOV-64: movf.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.ueq.d $f0, $f12, $f13 + ; SEL-64: mfc1 $[[T0:[0-9]+]], $f0 + ; SEL-64: not $[[T0]], $[[T0]] + ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0 + ; SEL-64: sel.d $f0, $f13, $f12 + + ; MM32R3: c.ueq.d $f12, $f14 + ; MM32R3: movf.d $f14, $f12, $fcc0 + ; MM32R3: mov.d $f0, $f14 + + %s = fcmp one double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} diff --git a/test/CodeGen/Mips/llvm-ir/select-flt.ll b/test/CodeGen/Mips/llvm-ir/select-flt.ll new file mode 100644 index 000000000000..6a0334da4833 --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/select-flt.ll @@ -0,0 +1,335 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,M2,M2-M3 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R1 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefixes=ALL,SEL-32,32R6 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefixes=ALL,M3,M2-M3 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefixes=ALL,SEL-64,64R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM32R3 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM32R6,SEL-32 + +define float @tst_select_i1_float(i1 signext %s, float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_i1_float: + + ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 + ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: jr $ra + ; M2: mtc1 $6, $f0 + ; M3: mov.s $f13, $f14 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2: mtc1 $5, $f0 + ; M3: mov.s $f0, $f13 + + ; CMOV-32: mtc1 $6, $f0 + ; CMOV-32: mtc1 $5, $f1 + ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-32: movn.s $f0, $f1, $[[T0]] + + ; SEL-32: mtc1 $5, $[[F0:f[0-9]+]] + ; SEL-32: mtc1 $6, $[[F1:f[0-9]+]] + ; SEL-32: mtc1 $4, $f0 + ; SEL-32: sel.s $f0, $[[F1]], $[[F0]] + + ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-64: movn.s $f14, $f13, $[[T0]] + ; CMOV-64: mov.s $f0, $f14 + + ; SEL-64: mtc1 $4, $f0 + ; SEL-64: sel.s $f0, $f14, $f13 + + ; MM32R3: mtc1 $6, $[[F0:f[0-9]+]] + ; MM32R3: mtc1 $5, $[[F1:f[0-9]+]] + ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1 + ; MM32R3: movn.s $f0, $[[F1]], $[[T0]] + + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_i1_float_reordered(float %x, float %y, + i1 signext %s) { +entry: + ; ALL-LABEL: tst_select_i1_float_reordered: + + ; M2-M3: andi $[[T0:[0-9]+]], $6, 1 + ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: andi $[[T0:[0-9]+]], $6, 1 + ; CMOV-32: movn.s $f14, $f12, $[[T0]] + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: mtc1 $6, $f0 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: andi $[[T0:[0-9]+]], $6, 1 + ; CMOV-64: movn.s $f13, $f12, $[[T0]] + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: mtc1 $6, $f0 + ; SEL-64: sel.s $f0, $f13, $f12 + + ; MM32R3: andi16 $[[T0:[0-9]+]], $6, 1 + ; MM32R3: movn.s $[[F0:f[0-9]+]], $f12, $[[T0]] + ; MM32R3: mov.s $f0, $[[F0]] + + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_fcmp_olt_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_olt_float: + + ; M2: c.olt.s $f12, $f14 + ; M3: c.olt.s $f12, $f13 + ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: c.olt.s $f12, $f14 + ; CMOV-32: movt.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.lt.s $f0, $f12, $f14 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.olt.s $f12, $f13 + ; CMOV-64: movt.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.lt.s $f0, $f12, $f13 + ; SEL-64: sel.s $f0, $f13, $f12 + + ; MM32R3: c.olt.s $f12, $f14 + ; MM32R3: movt.s $f14, $f12, $fcc0 + ; MM32R3: mov.s $f0, $f14 + + %s = fcmp olt float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_fcmp_ole_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_ole_float: + + ; M2: c.ole.s $f12, $f14 + ; M3: c.ole.s $f12, $f13 + ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: c.ole.s $f12, $f14 + ; CMOV-32: movt.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.le.s $f0, $f12, $f14 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.ole.s $f12, $f13 + ; CMOV-64: movt.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.le.s $f0, $f12, $f13 + ; SEL-64: sel.s $f0, $f13, $f12 + + ; MM32R3: c.ole.s $f12, $f14 + ; MM32R3: movt.s $f14, $f12, $fcc0 + ; MM32R3: mov.s $f0, $f14 + + %s = fcmp ole float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_fcmp_ogt_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_ogt_float: + + ; M2: c.ule.s $f12, $f14 + ; M3: c.ule.s $f12, $f13 + ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: c.ule.s $f12, $f14 + ; CMOV-32: movf.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.lt.s $f0, $f14, $f12 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.ule.s $f12, $f13 + ; CMOV-64: movf.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.lt.s $f0, $f13, $f12 + ; SEL-64: sel.s $f0, $f13, $f12 + + ; MM32R3: c.ule.s $f12, $f14 + ; MM32R3: movf.s $f14, $f12, $fcc0 + ; MM32R3: mov.s $f0, $f14 + + %s = fcmp ogt float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_fcmp_oge_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_oge_float: + + ; M2: c.ult.s $f12, $f14 + ; M3: c.ult.s $f12, $f13 + ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: c.ult.s $f12, $f14 + ; CMOV-32: movf.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.le.s $f0, $f14, $f12 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.ult.s $f12, $f13 + ; CMOV-64: movf.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.le.s $f0, $f13, $f12 + ; SEL-64: sel.s $f0, $f13, $f12 + + ; MM32R3: c.ult.s $f12, $f14 + ; MM32R3: movf.s $f14, $f12, $fcc0 + ; MM32R3: mov.s $f0, $f14 + + %s = fcmp oge float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_fcmp_oeq_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_oeq_float: + + ; M2: c.eq.s $f12, $f14 + ; M3: c.eq.s $f12, $f13 + ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: c.eq.s $f12, $f14 + ; CMOV-32: movt.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.eq.s $f0, $f12, $f14 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.eq.s $f12, $f13 + ; CMOV-64: movt.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.eq.s $f0, $f12, $f13 + ; SEL-64: sel.s $f0, $f13, $f12 + + ; MM32R3: c.eq.s $f12, $f14 + ; MM32R3: movt.s $f14, $f12, $fcc0 + ; MM32R3: mov.s $f0, $f14 + + %s = fcmp oeq float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_fcmp_one_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_one_float: + + ; M2: c.ueq.s $f12, $f14 + ; M3: c.ueq.s $f12, $f13 + ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: c.ueq.s $f12, $f14 + ; CMOV-32: movf.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.ueq.s $f0, $f12, $f14 + ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0 + ; SEL-32: not $[[T0]], $[[T0]] + ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.ueq.s $f12, $f13 + ; CMOV-64: movf.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.ueq.s $f0, $f12, $f13 + ; SEL-64: mfc1 $[[T0:[0-9]+]], $f0 + ; SEL-64: not $[[T0]], $[[T0]] + ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0 + ; SEL-64: sel.s $f0, $f13, $f12 + + ; MM32R3: c.ueq.s $f12, $f14 + ; MM32R3: movf.s $f14, $f12, $fcc0 + ; MM32R3: mov.s $f0, $f14 + + %s = fcmp one float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} diff --git a/test/CodeGen/Mips/llvm-ir/select-int.ll b/test/CodeGen/Mips/llvm-ir/select-int.ll new file mode 100644 index 000000000000..e8f78ffdcb6a --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/select-int.ll @@ -0,0 +1,270 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,M2,M2-M3 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R1 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefixes=ALL,SEL,SEL-32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefixes=ALL,M3,M2-M3 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefixes=ALL,SEL,SEL-64 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM32R3 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM32R6 + +define signext i1 @tst_select_i1_i1(i1 signext %s, + i1 signext %x, i1 signext %y) { +entry: + ; ALL-LABEL: tst_select_i1_i1: + + ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 + ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2-M3: move $5, $6 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: move $2, $5 + + ; CMOV: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV: movn $6, $5, $[[T0]] + ; CMOV: move $2, $6 + + ; SEL: andi $[[T0:[0-9]+]], $4, 1 + ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]] + ; SEL: or $2, $[[T2]], $[[T1]] + + ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1 + ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]] + ; MM32R3: move $2, $[[T1]] + + ; MMR6: andi16 $[[T0:[0-9]+]], $4, 1 + ; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; MMR6: selnez $[[T2:[0-9]+]], $5, $[[T0]] + ; MMR6: or $2, $[[T2]], $[[T1]] + + %r = select i1 %s, i1 %x, i1 %y + ret i1 %r +} + +define signext i8 @tst_select_i1_i8(i1 signext %s, + i8 signext %x, i8 signext %y) { +entry: + ; ALL-LABEL: tst_select_i1_i8: + + ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 + ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2-M3: move $5, $6 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: move $2, $5 + + ; CMOV: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV: movn $6, $5, $[[T0]] + ; CMOV: move $2, $6 + + ; SEL: andi $[[T0:[0-9]+]], $4, 1 + ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]] + ; SEL: or $2, $[[T2]], $[[T1]] + + ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1 + ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]] + ; MM32R3: move $2, $[[T1]] + + ; MMR6: andi16 $[[T0:[0-9]+]], $4, 1 + ; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; MMR6: selnez $[[T2:[0-9]+]], $5, $[[T0]] + ; MMR6: or $2, $[[T2]], $[[T1]] + + %r = select i1 %s, i8 %x, i8 %y + ret i8 %r +} + +define signext i32 @tst_select_i1_i32(i1 signext %s, + i32 signext %x, i32 signext %y) { +entry: + ; ALL-LABEL: tst_select_i1_i32: + + ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 + ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2-M3: move $5, $6 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: move $2, $5 + + ; CMOV: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV: movn $6, $5, $[[T0]] + ; CMOV: move $2, $6 + + ; SEL: andi $[[T0:[0-9]+]], $4, 1 + ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]] + ; SEL: or $2, $[[T2]], $[[T1]] + + ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1 + ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]] + ; MM32R3: move $2, $[[T1]] + + ; MMR6: andi16 $[[T0:[0-9]+]], $4, 1 + ; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; MMR6: selnez $[[T2:[0-9]+]], $5, $[[T0]] + ; MMR6: or $2, $[[T2]], $[[T1]] + + %r = select i1 %s, i32 %x, i32 %y + ret i32 %r +} + +define signext i64 @tst_select_i1_i64(i1 signext %s, + i64 signext %x, i64 signext %y) { +entry: + ; ALL-LABEL: tst_select_i1_i64: + + ; M2: andi $[[T0:[0-9]+]], $4, 1 + ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: lw $[[T1:[0-9]+]], 16($sp) + ; M2: $[[BB0]]: + ; FIXME: This branch is redundant + ; M2: bnez $[[T0]], $[[BB1:BB[0-9_]+]] + ; M2: nop + ; M2: lw $[[T2:[0-9]+]], 20($sp) + ; M2: $[[BB1]]: + ; M2: move $2, $[[T1]] + ; M2: jr $ra + ; M2: move $3, $[[T2]] + + ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-32: lw $2, 16($sp) + ; CMOV-32: movn $2, $6, $[[T0]] + ; CMOV-32: lw $3, 20($sp) + ; CMOV-32: movn $3, $7, $[[T0]] + + ; SEL-32: andi $[[T0:[0-9]+]], $4, 1 + ; SEL-32: selnez $[[T1:[0-9]+]], $6, $[[T0]] + ; SEL-32: lw $[[T2:[0-9]+]], 16($sp) + ; SEL-32: seleqz $[[T3:[0-9]+]], $[[T2]], $[[T0]] + ; SEL-32: or $2, $[[T1]], $[[T3]] + ; SEL-32: selnez $[[T4:[0-9]+]], $7, $[[T0]] + ; SEL-32: lw $[[T5:[0-9]+]], 20($sp) + ; SEL-32: seleqz $[[T6:[0-9]+]], $[[T5]], $[[T0]] + ; SEL-32: or $3, $[[T4]], $[[T6]] + + ; M3: andi $[[T0:[0-9]+]], $4, 1 + ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M3: nop + ; M3: move $5, $6 + ; M3: $[[BB0]]: + ; M3: jr $ra + ; M3: move $2, $5 + + ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-64: movn $6, $5, $[[T0]] + ; CMOV-64: move $2, $6 + + ; SEL-64: andi $[[T0:[0-9]+]], $4, 1 + ; FIXME: This shift is redundant + ; SEL-64: sll $[[T0]], $[[T0]], 0 + ; SEL-64: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; SEL-64: selnez $[[T0]], $5, $[[T0]] + ; SEL-64: or $2, $[[T0]], $[[T1]] + + ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1 + ; MM32R3: lw $2, 16($sp) + ; MM32R3: movn $2, $6, $[[T0]] + ; MM32R3: lw $3, 20($sp) + ; MM32R3: movn $3, $7, $[[T0]] + + ; MM32R6: andi16 $[[T0:[0-9]+]], $4, 1 + ; MM32R6: lw $[[T1:[0-9]+]], 16($sp) + ; MM32R6: seleqz $[[T2:[0-9]+]], $[[T1]], $[[T0]] + ; MM32R6: selnez $[[T3:[0-9]+]], $6, $[[T0]] + ; MM32R6: or $2, $[[T3]], $[[T2]] + ; MM32R6: lw $[[T4:[0-9]+]], 20($sp) + ; MM32R6: seleqz $[[T5:[0-9]+]], $[[T4]], $[[T0]] + ; MM32R6: selnez $[[T6:[0-9]+]], $7, $[[T0]] + ; MM32R6: or $3, $[[T6]], $[[T5]] + + %r = select i1 %s, i64 %x, i64 %y + ret i64 %r +} + +define i8* @tst_select_word_cst(i8* %a, i8* %b) { + ; ALL-LABEL: tst_select_word_cst: + + ; M2: addiu $[[T0:[0-9]+]], $zero, -1 + ; M2: xor $[[T1:[0-9]+]], $5, $[[T0]] + ; M2: sltu $[[T2:[0-9]+]], $zero, $[[T1]] + ; M2: bnez $[[T2]], $[[BB0:BB[0-9_]+]] + ; M2: addiu $2, $zero, 0 + ; M2: move $2, $4 + ; M2: $[[BB0]]: + ; M2: jr $ra + + ; M3: daddiu $[[T0:[0-9]+]], $zero, -1 + ; M3: xor $[[T1:[0-9]+]], $5, $[[T0]] + ; M3: sltu $[[T2:[0-9]+]], $zero, $[[T1]] + ; M3: bnez $[[T2]], $[[BB0:BB[0-9_]+]] + ; M3: daddiu $2, $zero, 0 + ; M3: move $2, $4 + ; M3: $[[BB0]]: + ; M3: jr $ra + + ; CMOV-32: addiu $[[T0:[0-9]+]], $zero, -1 + ; CMOV-32: xor $[[T1:[0-9]+]], $5, $[[T0]] + ; CMOV-32: movn $[[T2:[0-9]+]], $zero, $[[T1]] + ; CMOV-32: jr $ra + ; CMOV-32: move $2, $[[T2]] + + ; SEL-32: addiu $[[T0:[0-9]+]], $zero, -1 + ; SEL-32: xor $[[T1:[0-9]+]], $5, $[[T0]] + ; SEL-32: sltu $[[T2:[0-9]+]], $zero, $[[T1]] + ; SEL-32: jr $ra + ; SEL-32: seleqz $2, $4, $[[T2]] + + ; CMOV-64: daddiu $[[T0:[0-9]+]], $zero, -1 + ; CMOV-64: xor $[[T1:[0-9]+]], $5, $[[T0]] + ; CMOV-64: movn $[[T2:[0-9]+]], $zero, $[[T1]] + ; CMOV-64: move $2, $[[T2]] + + ; SEL-64: daddiu $[[T0:[0-9]+]], $zero, -1 + ; SEL-64: xor $[[T1:[0-9]+]], $5, $[[T0]] + ; SEL-64: sltu $[[T2:[0-9]+]], $zero, $[[T1]] + ; FIXME: This shift is redundant. + ; SEL-64: sll $[[T2]], $[[T2]], 0 + ; SEL-64: seleqz $2, $4, $[[T2]] + + ; MM32R3: li16 $[[T0:[0-9]+]], -1 + ; MM32R3: xor $[[T1:[0-9]+]], $5, $[[T0]] + ; MM32R3: lui $[[T2:[0-9]+]], 0 + ; MM32R3: movn $[[T3:[0-9]+]], $[[T2]], $[[T1]] + ; MM32R3: move $2, $[[T3]] + + ; MM32R6: li16 $[[T0:[0-9]+]], -1 + ; MM32R6: xor $[[T1:[0-9]+]], $5, $[[T0]] + ; MM32R6: sltu $[[T2:[0-9]+]], $zero, $[[T1]] + ; MM32R6: seleqz $2, $4, $[[T2]] + + %cmp = icmp eq i8* %b, inttoptr (i64 -1 to i8*) + %r = select i1 %cmp, i8* %a, i8* null + ret i8* %r +} diff --git a/test/CodeGen/Mips/llvm-ir/select.ll b/test/CodeGen/Mips/llvm-ir/select.ll deleted file mode 100644 index f17670adca33..000000000000 --- a/test/CodeGen/Mips/llvm-ir/select.ll +++ /dev/null @@ -1,712 +0,0 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=M2 -check-prefix=M2-M3 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=CMOV \ -; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R1 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=CMOV \ -; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=CMOV \ -; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=CMOV \ -; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=M3 -check-prefix=M2-M3 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64 - -define signext i1 @tst_select_i1_i1(i1 signext %s, - i1 signext %x, i1 signext %y) { -entry: - ; ALL-LABEL: tst_select_i1_i1: - - ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 - ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2-M3: move $5, $6 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: move $2, $5 - - ; CMOV: andi $[[T0:[0-9]+]], $4, 1 - ; CMOV: movn $6, $5, $[[T0]] - ; CMOV: move $2, $6 - - ; SEL: andi $[[T0:[0-9]+]], $4, 1 - ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]] - ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]] - ; SEL: or $2, $[[T2]], $[[T1]] - %r = select i1 %s, i1 %x, i1 %y - ret i1 %r -} - -define signext i8 @tst_select_i1_i8(i1 signext %s, - i8 signext %x, i8 signext %y) { -entry: - ; ALL-LABEL: tst_select_i1_i8: - - ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 - ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2-M3: move $5, $6 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: move $2, $5 - - ; CMOV: andi $[[T0:[0-9]+]], $4, 1 - ; CMOV: movn $6, $5, $[[T0]] - ; CMOV: move $2, $6 - - ; SEL: andi $[[T0:[0-9]+]], $4, 1 - ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]] - ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]] - ; SEL: or $2, $[[T2]], $[[T1]] - %r = select i1 %s, i8 %x, i8 %y - ret i8 %r -} - -define signext i32 @tst_select_i1_i32(i1 signext %s, - i32 signext %x, i32 signext %y) { -entry: - ; ALL-LABEL: tst_select_i1_i32: - - ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 - ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2-M3: move $5, $6 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: move $2, $5 - - ; CMOV: andi $[[T0:[0-9]+]], $4, 1 - ; CMOV: movn $6, $5, $[[T0]] - ; CMOV: move $2, $6 - - ; SEL: andi $[[T0:[0-9]+]], $4, 1 - ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]] - ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]] - ; SEL: or $2, $[[T2]], $[[T1]] - %r = select i1 %s, i32 %x, i32 %y - ret i32 %r -} - -define signext i64 @tst_select_i1_i64(i1 signext %s, - i64 signext %x, i64 signext %y) { -entry: - ; ALL-LABEL: tst_select_i1_i64: - - ; M2: andi $[[T0:[0-9]+]], $4, 1 - ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]] - ; M2: nop - ; M2: lw $[[T1:[0-9]+]], 16($sp) - ; M2: $[[BB0]]: - ; FIXME: This branch is redundant - ; M2: bnez $[[T0]], $[[BB1:BB[0-9_]+]] - ; M2: nop - ; M2: lw $[[T2:[0-9]+]], 20($sp) - ; M2: $[[BB1]]: - ; M2: move $2, $[[T1]] - ; M2: jr $ra - ; M2: move $3, $[[T2]] - - ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1 - ; CMOV-32: lw $2, 16($sp) - ; CMOV-32: movn $2, $6, $[[T0]] - ; CMOV-32: lw $3, 20($sp) - ; CMOV-32: movn $3, $7, $[[T0]] - - ; SEL-32: andi $[[T0:[0-9]+]], $4, 1 - ; SEL-32: selnez $[[T1:[0-9]+]], $6, $[[T0]] - ; SEL-32: lw $[[T2:[0-9]+]], 16($sp) - ; SEL-32: seleqz $[[T3:[0-9]+]], $[[T2]], $[[T0]] - ; SEL-32: or $2, $[[T1]], $[[T3]] - ; SEL-32: selnez $[[T4:[0-9]+]], $7, $[[T0]] - ; SEL-32: lw $[[T5:[0-9]+]], 20($sp) - ; SEL-32: seleqz $[[T6:[0-9]+]], $[[T5]], $[[T0]] - ; SEL-32: or $3, $[[T4]], $[[T6]] - - ; M3: andi $[[T0:[0-9]+]], $4, 1 - ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] - ; M3: nop - ; M3: move $5, $6 - ; M3: $[[BB0]]: - ; M3: jr $ra - ; M3: move $2, $5 - - ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1 - ; CMOV-64: movn $6, $5, $[[T0]] - ; CMOV-64: move $2, $6 - - ; SEL-64: andi $[[T0:[0-9]+]], $4, 1 - ; FIXME: This shift is redundant - ; SEL-64: sll $[[T0]], $[[T0]], 0 - ; SEL-64: seleqz $[[T1:[0-9]+]], $6, $[[T0]] - ; SEL-64: selnez $[[T0]], $5, $[[T0]] - ; SEL-64: or $2, $[[T0]], $[[T1]] - %r = select i1 %s, i64 %x, i64 %y - ret i64 %r -} - -define float @tst_select_i1_float(i1 signext %s, float %x, float %y) { -entry: - ; ALL-LABEL: tst_select_i1_float: - - ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 - ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: jr $ra - ; M2: mtc1 $6, $f0 - ; M3: mov.s $f13, $f14 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2: mtc1 $5, $f0 - ; M3: mov.s $f0, $f13 - - ; CMOV-32: mtc1 $6, $f0 - ; CMOV-32: mtc1 $5, $f1 - ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1 - ; CMOV-32: movn.s $f0, $f1, $[[T0]] - - ; SEL-32: mtc1 $5, $[[F0:f[0-9]+]] - ; SEL-32: mtc1 $6, $[[F1:f[0-9]+]] - ; SEL-32: mtc1 $4, $f0 - ; SEL-32: sel.s $f0, $[[F1]], $[[F0]] - - ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1 - ; CMOV-64: movn.s $f14, $f13, $[[T0]] - ; CMOV-64: mov.s $f0, $f14 - - ; SEL-64: mtc1 $4, $f0 - ; SEL-64: sel.s $f0, $f14, $f13 - %r = select i1 %s, float %x, float %y - ret float %r -} - -define float @tst_select_i1_float_reordered(float %x, float %y, - i1 signext %s) { -entry: - ; ALL-LABEL: tst_select_i1_float_reordered: - - ; M2-M3: andi $[[T0:[0-9]+]], $6, 1 - ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: mov.s $f12, $f14 - ; M3: mov.s $f12, $f13 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: mov.s $f0, $f12 - - ; CMOV-32: andi $[[T0:[0-9]+]], $6, 1 - ; CMOV-32: movn.s $f14, $f12, $[[T0]] - ; CMOV-32: mov.s $f0, $f14 - - ; SEL-32: mtc1 $6, $f0 - ; SEL-32: sel.s $f0, $f14, $f12 - - ; CMOV-64: andi $[[T0:[0-9]+]], $6, 1 - ; CMOV-64: movn.s $f13, $f12, $[[T0]] - ; CMOV-64: mov.s $f0, $f13 - - ; SEL-64: mtc1 $6, $f0 - ; SEL-64: sel.s $f0, $f13, $f12 - %r = select i1 %s, float %x, float %y - ret float %r -} - -define double @tst_select_i1_double(i1 signext %s, double %x, double %y) { -entry: - ; ALL-LABEL: tst_select_i1_double: - - ; M2: andi $[[T0:[0-9]+]], $4, 1 - ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]] - ; M2: nop - ; M2: ldc1 $f0, 16($sp) - ; M2: jr $ra - ; M2: nop - ; M2: $[[BB0]]: - ; M2: mtc1 $7, $f0 - ; M2: jr $ra - ; M2: mtc1 $6, $f1 - - ; CMOV-32: mtc1 $7, $[[F0:f[0-9]+]] - ; CMOV-32R1: mtc1 $6, $f{{[0-9]+}} - ; CMOV-32R2-R5: mthc1 $6, $[[F0]] - ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1 - ; CMOV-32: ldc1 $f0, 16($sp) - ; CMOV-32: movn.d $f0, $[[F0]], $[[T0]] - - ; SEL-32: mtc1 $7, $[[F0:f[0-9]+]] - ; SEL-32: mthc1 $6, $[[F0]] - ; SEL-32: ldc1 $[[F1:f[0-9]+]], 16($sp) - ; SEL-32: mtc1 $4, $f0 - ; SEL-32: sel.d $f0, $[[F1]], $[[F0]] - - ; M3: andi $[[T0:[0-9]+]], $4, 1 - ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] - ; M3: nop - ; M3: mov.d $f13, $f14 - ; M3: $[[BB0]]: - ; M3: jr $ra - ; M3: mov.d $f0, $f13 - - ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1 - ; CMOV-64: movn.d $f14, $f13, $[[T0]] - ; CMOV-64: mov.d $f0, $f14 - - ; SEL-64: mtc1 $4, $f0 - ; SEL-64: sel.d $f0, $f14, $f13 - %r = select i1 %s, double %x, double %y - ret double %r -} - -define double @tst_select_i1_double_reordered(double %x, double %y, - i1 signext %s) { -entry: - ; ALL-LABEL: tst_select_i1_double_reordered: - - ; M2: lw $[[T0:[0-9]+]], 16($sp) - ; M2: andi $[[T1:[0-9]+]], $[[T0]], 1 - ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]] - ; M2: nop - ; M2: mov.d $f12, $f14 - ; M2: $[[BB0]]: - ; M2: jr $ra - ; M2: mov.d $f0, $f12 - - ; CMOV-32: lw $[[T0:[0-9]+]], 16($sp) - ; CMOV-32: andi $[[T1:[0-9]+]], $[[T0]], 1 - ; CMOV-32: movn.d $f14, $f12, $[[T1]] - ; CMOV-32: mov.d $f0, $f14 - - ; SEL-32: lw $[[T0:[0-9]+]], 16($sp) - ; SEL-32: mtc1 $[[T0]], $f0 - ; SEL-32: sel.d $f0, $f14, $f12 - - ; M3: andi $[[T0:[0-9]+]], $6, 1 - ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] - ; M3: nop - ; M3: mov.d $f12, $f13 - ; M3: $[[BB0]]: - ; M3: jr $ra - ; M3: mov.d $f0, $f12 - - ; CMOV-64: andi $[[T0:[0-9]+]], $6, 1 - ; CMOV-64: movn.d $f13, $f12, $[[T0]] - ; CMOV-64: mov.d $f0, $f13 - - ; SEL-64: mtc1 $6, $f0 - ; SEL-64: sel.d $f0, $f13, $f12 - %r = select i1 %s, double %x, double %y - ret double %r -} - -define float @tst_select_fcmp_olt_float(float %x, float %y) { -entry: - ; ALL-LABEL: tst_select_fcmp_olt_float: - - ; M2: c.olt.s $f12, $f14 - ; M3: c.olt.s $f12, $f13 - ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: mov.s $f12, $f14 - ; M3: mov.s $f12, $f13 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: mov.s $f0, $f12 - - ; CMOV-32: c.olt.s $f12, $f14 - ; CMOV-32: movt.s $f14, $f12, $fcc0 - ; CMOV-32: mov.s $f0, $f14 - - ; SEL-32: cmp.lt.s $f0, $f12, $f14 - ; SEL-32: sel.s $f0, $f14, $f12 - - ; CMOV-64: c.olt.s $f12, $f13 - ; CMOV-64: movt.s $f13, $f12, $fcc0 - ; CMOV-64: mov.s $f0, $f13 - - ; SEL-64: cmp.lt.s $f0, $f12, $f13 - ; SEL-64: sel.s $f0, $f13, $f12 - %s = fcmp olt float %x, %y - %r = select i1 %s, float %x, float %y - ret float %r -} - -define float @tst_select_fcmp_ole_float(float %x, float %y) { -entry: - ; ALL-LABEL: tst_select_fcmp_ole_float: - - ; M2: c.ole.s $f12, $f14 - ; M3: c.ole.s $f12, $f13 - ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: mov.s $f12, $f14 - ; M3: mov.s $f12, $f13 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: mov.s $f0, $f12 - - ; CMOV-32: c.ole.s $f12, $f14 - ; CMOV-32: movt.s $f14, $f12, $fcc0 - ; CMOV-32: mov.s $f0, $f14 - - ; SEL-32: cmp.le.s $f0, $f12, $f14 - ; SEL-32: sel.s $f0, $f14, $f12 - - ; CMOV-64: c.ole.s $f12, $f13 - ; CMOV-64: movt.s $f13, $f12, $fcc0 - ; CMOV-64: mov.s $f0, $f13 - - ; SEL-64: cmp.le.s $f0, $f12, $f13 - ; SEL-64: sel.s $f0, $f13, $f12 - %s = fcmp ole float %x, %y - %r = select i1 %s, float %x, float %y - ret float %r -} - -define float @tst_select_fcmp_ogt_float(float %x, float %y) { -entry: - ; ALL-LABEL: tst_select_fcmp_ogt_float: - - ; M2: c.ule.s $f12, $f14 - ; M3: c.ule.s $f12, $f13 - ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: mov.s $f12, $f14 - ; M3: mov.s $f12, $f13 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: mov.s $f0, $f12 - - ; CMOV-32: c.ule.s $f12, $f14 - ; CMOV-32: movf.s $f14, $f12, $fcc0 - ; CMOV-32: mov.s $f0, $f14 - - ; SEL-32: cmp.lt.s $f0, $f14, $f12 - ; SEL-32: sel.s $f0, $f14, $f12 - - ; CMOV-64: c.ule.s $f12, $f13 - ; CMOV-64: movf.s $f13, $f12, $fcc0 - ; CMOV-64: mov.s $f0, $f13 - - ; SEL-64: cmp.lt.s $f0, $f13, $f12 - ; SEL-64: sel.s $f0, $f13, $f12 - %s = fcmp ogt float %x, %y - %r = select i1 %s, float %x, float %y - ret float %r -} - -define float @tst_select_fcmp_oge_float(float %x, float %y) { -entry: - ; ALL-LABEL: tst_select_fcmp_oge_float: - - ; M2: c.ult.s $f12, $f14 - ; M3: c.ult.s $f12, $f13 - ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: mov.s $f12, $f14 - ; M3: mov.s $f12, $f13 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: mov.s $f0, $f12 - - ; CMOV-32: c.ult.s $f12, $f14 - ; CMOV-32: movf.s $f14, $f12, $fcc0 - ; CMOV-32: mov.s $f0, $f14 - - ; SEL-32: cmp.le.s $f0, $f14, $f12 - ; SEL-32: sel.s $f0, $f14, $f12 - - ; CMOV-64: c.ult.s $f12, $f13 - ; CMOV-64: movf.s $f13, $f12, $fcc0 - ; CMOV-64: mov.s $f0, $f13 - - ; SEL-64: cmp.le.s $f0, $f13, $f12 - ; SEL-64: sel.s $f0, $f13, $f12 - %s = fcmp oge float %x, %y - %r = select i1 %s, float %x, float %y - ret float %r -} - -define float @tst_select_fcmp_oeq_float(float %x, float %y) { -entry: - ; ALL-LABEL: tst_select_fcmp_oeq_float: - - ; M2: c.eq.s $f12, $f14 - ; M3: c.eq.s $f12, $f13 - ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: mov.s $f12, $f14 - ; M3: mov.s $f12, $f13 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: mov.s $f0, $f12 - - ; CMOV-32: c.eq.s $f12, $f14 - ; CMOV-32: movt.s $f14, $f12, $fcc0 - ; CMOV-32: mov.s $f0, $f14 - - ; SEL-32: cmp.eq.s $f0, $f12, $f14 - ; SEL-32: sel.s $f0, $f14, $f12 - - ; CMOV-64: c.eq.s $f12, $f13 - ; CMOV-64: movt.s $f13, $f12, $fcc0 - ; CMOV-64: mov.s $f0, $f13 - - ; SEL-64: cmp.eq.s $f0, $f12, $f13 - ; SEL-64: sel.s $f0, $f13, $f12 - %s = fcmp oeq float %x, %y - %r = select i1 %s, float %x, float %y - ret float %r -} - -define float @tst_select_fcmp_one_float(float %x, float %y) { -entry: - ; ALL-LABEL: tst_select_fcmp_one_float: - - ; M2: c.ueq.s $f12, $f14 - ; M3: c.ueq.s $f12, $f13 - ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: mov.s $f12, $f14 - ; M3: mov.s $f12, $f13 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: mov.s $f0, $f12 - - ; CMOV-32: c.ueq.s $f12, $f14 - ; CMOV-32: movf.s $f14, $f12, $fcc0 - ; CMOV-32: mov.s $f0, $f14 - - ; SEL-32: cmp.ueq.s $f0, $f12, $f14 - ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0 - ; SEL-32: not $[[T0]], $[[T0]] - ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0 - ; SEL-32: sel.s $f0, $f14, $f12 - - ; CMOV-64: c.ueq.s $f12, $f13 - ; CMOV-64: movf.s $f13, $f12, $fcc0 - ; CMOV-64: mov.s $f0, $f13 - - ; SEL-64: cmp.ueq.s $f0, $f12, $f13 - ; SEL-64: mfc1 $[[T0:[0-9]+]], $f0 - ; SEL-64: not $[[T0]], $[[T0]] - ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0 - ; SEL-64: sel.s $f0, $f13, $f12 - - %s = fcmp one float %x, %y - %r = select i1 %s, float %x, float %y - ret float %r -} - -define double @tst_select_fcmp_olt_double(double %x, double %y) { -entry: - ; ALL-LABEL: tst_select_fcmp_olt_double: - - ; M2: c.olt.d $f12, $f14 - ; M3: c.olt.d $f12, $f13 - ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: mov.d $f12, $f14 - ; M3: mov.d $f12, $f13 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: mov.d $f0, $f12 - - ; CMOV-32: c.olt.d $f12, $f14 - ; CMOV-32: movt.d $f14, $f12, $fcc0 - ; CMOV-32: mov.d $f0, $f14 - - ; SEL-32: cmp.lt.d $f0, $f12, $f14 - ; SEL-32: sel.d $f0, $f14, $f12 - - ; CMOV-64: c.olt.d $f12, $f13 - ; CMOV-64: movt.d $f13, $f12, $fcc0 - ; CMOV-64: mov.d $f0, $f13 - - ; SEL-64: cmp.lt.d $f0, $f12, $f13 - ; SEL-64: sel.d $f0, $f13, $f12 - %s = fcmp olt double %x, %y - %r = select i1 %s, double %x, double %y - ret double %r -} - -define double @tst_select_fcmp_ole_double(double %x, double %y) { -entry: - ; ALL-LABEL: tst_select_fcmp_ole_double: - - ; M2: c.ole.d $f12, $f14 - ; M3: c.ole.d $f12, $f13 - ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: mov.d $f12, $f14 - ; M3: mov.d $f12, $f13 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: mov.d $f0, $f12 - - ; CMOV-32: c.ole.d $f12, $f14 - ; CMOV-32: movt.d $f14, $f12, $fcc0 - ; CMOV-32: mov.d $f0, $f14 - - ; SEL-32: cmp.le.d $f0, $f12, $f14 - ; SEL-32: sel.d $f0, $f14, $f12 - - ; CMOV-64: c.ole.d $f12, $f13 - ; CMOV-64: movt.d $f13, $f12, $fcc0 - ; CMOV-64: mov.d $f0, $f13 - - ; SEL-64: cmp.le.d $f0, $f12, $f13 - ; SEL-64: sel.d $f0, $f13, $f12 - %s = fcmp ole double %x, %y - %r = select i1 %s, double %x, double %y - ret double %r -} - -define double @tst_select_fcmp_ogt_double(double %x, double %y) { -entry: - ; ALL-LABEL: tst_select_fcmp_ogt_double: - - ; M2: c.ule.d $f12, $f14 - ; M3: c.ule.d $f12, $f13 - ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: mov.d $f12, $f14 - ; M3: mov.d $f12, $f13 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: mov.d $f0, $f12 - - ; CMOV-32: c.ule.d $f12, $f14 - ; CMOV-32: movf.d $f14, $f12, $fcc0 - ; CMOV-32: mov.d $f0, $f14 - - ; SEL-32: cmp.lt.d $f0, $f14, $f12 - ; SEL-32: sel.d $f0, $f14, $f12 - - ; CMOV-64: c.ule.d $f12, $f13 - ; CMOV-64: movf.d $f13, $f12, $fcc0 - ; CMOV-64: mov.d $f0, $f13 - - ; SEL-64: cmp.lt.d $f0, $f13, $f12 - ; SEL-64: sel.d $f0, $f13, $f12 - %s = fcmp ogt double %x, %y - %r = select i1 %s, double %x, double %y - ret double %r -} - -define double @tst_select_fcmp_oge_double(double %x, double %y) { -entry: - ; ALL-LABEL: tst_select_fcmp_oge_double: - - ; M2: c.ult.d $f12, $f14 - ; M3: c.ult.d $f12, $f13 - ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: mov.d $f12, $f14 - ; M3: mov.d $f12, $f13 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: mov.d $f0, $f12 - - ; CMOV-32: c.ult.d $f12, $f14 - ; CMOV-32: movf.d $f14, $f12, $fcc0 - ; CMOV-32: mov.d $f0, $f14 - - ; SEL-32: cmp.le.d $f0, $f14, $f12 - ; SEL-32: sel.d $f0, $f14, $f12 - - ; CMOV-64: c.ult.d $f12, $f13 - ; CMOV-64: movf.d $f13, $f12, $fcc0 - ; CMOV-64: mov.d $f0, $f13 - - ; SEL-64: cmp.le.d $f0, $f13, $f12 - ; SEL-64: sel.d $f0, $f13, $f12 - %s = fcmp oge double %x, %y - %r = select i1 %s, double %x, double %y - ret double %r -} - -define double @tst_select_fcmp_oeq_double(double %x, double %y) { -entry: - ; ALL-LABEL: tst_select_fcmp_oeq_double: - - ; M2: c.eq.d $f12, $f14 - ; M3: c.eq.d $f12, $f13 - ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: mov.d $f12, $f14 - ; M3: mov.d $f12, $f13 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: mov.d $f0, $f12 - - ; CMOV-32: c.eq.d $f12, $f14 - ; CMOV-32: movt.d $f14, $f12, $fcc0 - ; CMOV-32: mov.d $f0, $f14 - - ; SEL-32: cmp.eq.d $f0, $f12, $f14 - ; SEL-32: sel.d $f0, $f14, $f12 - - ; CMOV-64: c.eq.d $f12, $f13 - ; CMOV-64: movt.d $f13, $f12, $fcc0 - ; CMOV-64: mov.d $f0, $f13 - - ; SEL-64: cmp.eq.d $f0, $f12, $f13 - ; SEL-64: sel.d $f0, $f13, $f12 - %s = fcmp oeq double %x, %y - %r = select i1 %s, double %x, double %y - ret double %r -} - -define double @tst_select_fcmp_one_double(double %x, double %y) { -entry: - ; ALL-LABEL: tst_select_fcmp_one_double: - - ; M2: c.ueq.d $f12, $f14 - ; M3: c.ueq.d $f12, $f13 - ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: mov.d $f12, $f14 - ; M3: mov.d $f12, $f13 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: mov.d $f0, $f12 - - ; CMOV-32: c.ueq.d $f12, $f14 - ; CMOV-32: movf.d $f14, $f12, $fcc0 - ; CMOV-32: mov.d $f0, $f14 - - ; SEL-32: cmp.ueq.d $f0, $f12, $f14 - ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0 - ; SEL-32: not $[[T0]], $[[T0]] - ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0 - ; SEL-32: sel.d $f0, $f14, $f12 - - ; CMOV-64: c.ueq.d $f12, $f13 - ; CMOV-64: movf.d $f13, $f12, $fcc0 - ; CMOV-64: mov.d $f0, $f13 - - ; SEL-64: cmp.ueq.d $f0, $f12, $f13 - ; SEL-64: mfc1 $[[T0:[0-9]+]], $f0 - ; SEL-64: not $[[T0]], $[[T0]] - ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0 - ; SEL-64: sel.d $f0, $f13, $f12 - %s = fcmp one double %x, %y - %r = select i1 %s, double %x, double %y - ret double %r -} diff --git a/test/CodeGen/Mips/llvm-ir/shl.ll b/test/CodeGen/Mips/llvm-ir/shl.ll index bba34c47ea82..fa43840a8b7b 100644 --- a/test/CodeGen/Mips/llvm-ir/shl.ll +++ b/test/CodeGen/Mips/llvm-ir/shl.ll @@ -1,42 +1,33 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=M2 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 -check-prefix=NOT-R2-R6 \ -; RUN: -check-prefix=32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R5 -check-prefix=R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R5 -check-prefix=R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R5 -check-prefix=R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R6 -check-prefix=R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=M3 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=64R6 -check-prefix=R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,M2,NOT-R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,NOT-R2-R6,32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R1-R5,R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R1-R5,R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R1-R5,R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R6,R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,M3,NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6,NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6,NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6,R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6,R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6,R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,64R6,R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MMR3 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MMR6 define signext i1 @shl_i1(i1 signext %a, i1 signext %b) { entry: @@ -61,6 +52,10 @@ entry: ; R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]] ; R2-R6: seb $2, $[[T1]] + ; MM: andi16 $[[T0:[0-9]+]], $5, 255 + ; MM: sllv $[[T1:[0-9]+]], $4, $[[T0]] + ; MM: seb $2, $[[T1]] + %r = shl i8 %a, %b ret i8 %r } @@ -78,6 +73,10 @@ entry: ; R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]] ; R2-R6: seh $2, $[[T1]] + ; MM: andi16 $[[T0:[0-9]+]], $5, 65535 + ; MM: sllv $[[T1:[0-9]+]], $4, $[[T0]] + ; MM: seh $2, $[[T1]] + %r = shl i16 %a, %b ret i16 %r } @@ -139,6 +138,29 @@ entry: ; GP64: dsllv $2, $4, $5 + ; MMR3: sllv $[[T0:[0-9]+]], $4, $7 + ; MMR3: srl16 $[[T1:[0-9]+]], $5, 1 + ; MMR3: not16 $[[T2:[0-9]+]], $7 + ; MMR3: srlv $[[T3:[0-9]+]], $[[T1]], $[[T2]] + ; MMR3: or16 $[[T4:[0-9]+]], $[[T0]] + ; MMR3: sllv $[[T5:[0-9]+]], $5, $7 + ; MMR3: andi16 $[[T6:[0-9]+]], $7, 32 + ; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]] + ; MMR3: lui $[[T8:[0-9]+]], 0 + ; MMR3: movn $3, $[[T8]], $[[T6]] + + ; MMR6: sllv $[[T0:[0-9]+]], $4, $7 + ; MMR6: srl16 $[[T1:[0-9]+]], $5, 1 + ; MMR6: not16 $[[T2:[0-9]+]], $7 + ; MMR6: srlv $[[T3:[0-9]+]], $[[T1]], $[[T2]] + ; MMR6: or16 $[[T4:[0-9]+]], $[[T0]] + ; MMR6: andi16 $[[T5:[0-9]+]], $7, 32 + ; MMR6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T5]] + ; MMR6: sllv $[[T7:[0-9]+]], $5, $7 + ; MMR6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]] + ; MMR6: or $2, $[[T8]], $[[T6]] + ; MMR6: seleqz $3, $[[T7]], $[[T5]] + %r = shl i64 %a, %b ret i64 %r } @@ -194,6 +216,8 @@ entry: ; 64R6: jr $ra ; 64R6: seleqz $3, $[[T9]], $[[T7]] + ; MM: lw $25, %call16(__ashlti3)($2) + %r = shl i128 %a, %b ret i128 %r } diff --git a/test/CodeGen/Mips/llvm-ir/srem.ll b/test/CodeGen/Mips/llvm-ir/srem.ll index ceb53ee7033a..3431922b6c58 100644 --- a/test/CodeGen/Mips/llvm-ir/srem.ll +++ b/test/CodeGen/Mips/llvm-ir/srem.ll @@ -1,32 +1,37 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=GP32 \ -; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=GP32 \ -; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=GP32 \ -; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=GP32 -check-prefix=R6 -check-prefix=R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=64R6 -check-prefix=R6 -check-prefix=R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,NOT-R6,NOT-R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,NOT-R6,NOT-R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,R6,R2-R6 + +; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64-NOT-R6,NOT-R6,NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64-NOT-R6,NOT-R6,NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64-NOT-R6,NOT-R6,NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,64R6,R6,R2-R6 + +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR3,MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM64 define signext i1 @srem_i1(i1 signext %a, i1 signext %b) { entry: @@ -43,6 +48,17 @@ entry: ; R6: sll $[[T3:[0-9]+]], $[[T0]], 31 ; R6: sra $2, $[[T3]], 31 + ; MMR3: div $zero, $4, $5 + ; MMR3: teq $5, $zero, 7 + ; MMR3: mfhi $[[T0:[0-9]+]] + ; MMR3: sll $[[T1:[0-9]+]], $[[T0]], 31 + ; MMR3: sra $2, $[[T1]], 31 + + ; MMR6: mod $[[T0:[0-9]+]], $4, $5 + ; MMR6: teq $5, $zero, 7 + ; MMR6: sll $[[T1:[0-9]+]], $[[T0]], 31 + ; MMR6: sra $2, $[[T1]], 31 + %r = srem i1 %a, %b ret i1 %r } @@ -66,6 +82,15 @@ entry: ; R6: teq $5, $zero, 7 ; R6: seb $2, $[[T0]] + ; MMR3: div $zero, $4, $5 + ; MMR3: teq $5, $zero, 7 + ; MMR3: mfhi $[[T0:[0-9]+]] + ; MMR3: seb $2, $[[T0]] + + ; MMR6: mod $[[T0:[0-9]+]], $4, $5 + ; MMR6: teq $5, $zero, 7 + ; MMR6: seb $2, $[[T0]] + %r = srem i8 %a, %b ret i8 %r } @@ -83,12 +108,21 @@ entry: ; R2-R5: div $zero, $4, $5 ; R2-R5: teq $5, $zero, 7 ; R2-R5: mfhi $[[T0:[0-9]+]] - ; R2-R5: seh $2, $[[T1]] + ; R2-R5: seh $2, $[[T0]] ; R6: mod $[[T0:[0-9]+]], $4, $5 ; R6: teq $5, $zero, 7 ; R6: seh $2, $[[T0]] + ; MMR3: div $zero, $4, $5 + ; MMR3: teq $5, $zero, 7 + ; MMR3: mfhi $[[T0:[0-9]+]] + ; MMR3: seh $2, $[[T0]] + + ; MMR6: mod $[[T0:[0-9]+]], $4, $5 + ; MMR6: teq $5, $zero, 7 + ; MMR6: seh $2, $[[T0]] + %r = srem i16 %a, %b ret i16 %r } @@ -104,6 +138,13 @@ entry: ; R6: mod $2, $4, $5 ; R6: teq $5, $zero, 7 + ; MMR3: div $zero, $4, $5 + ; MMR3: teq $5, $zero, 7 + ; MMR3: mfhi $2 + + ; MMR6: mod $2, $4, $5 + ; MMR6: teq $5, $zero, 7 + %r = srem i32 %a, %b ret i32 %r } @@ -121,6 +162,11 @@ entry: ; 64R6: dmod $2, $4, $5 ; 64R6: teq $5, $zero, 7 + ; MM32: lw $25, %call16(__moddi3)($2) + + ; MM64: dmod $2, $4, $5 + ; MM64: teq $5, $zero, 7 + %r = srem i64 %a, %b ret i64 %r } @@ -132,7 +178,11 @@ entry: ; GP32: lw $25, %call16(__modti3)($gp) ; GP64-NOT-R6: ld $25, %call16(__modti3)($gp) - ; 64-R6: ld $25, %call16(__modti3)($gp) + ; 64R6: ld $25, %call16(__modti3)($gp) + + ; MM32: lw $25, %call16(__modti3)($2) + + ; MM64: ld $25, %call16(__modti3)($2) %r = srem i128 %a, %b ret i128 %r diff --git a/test/CodeGen/Mips/llvm-ir/store-atomic.ll b/test/CodeGen/Mips/llvm-ir/store-atomic.ll index 6b33f2685d17..8624cf6c1c66 100644 --- a/test/CodeGen/Mips/llvm-ir/store-atomic.ll +++ b/test/CodeGen/Mips/llvm-ir/store-atomic.ll @@ -1,9 +1,9 @@ ; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL ; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL ; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=M64 +; RUN: FileCheck %s -check-prefixes=ALL,M64 ; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=M64 +; RUN: FileCheck %s -check-prefixes=ALL,M64 define void @store_i8(i8* %ptr, i8 signext %v) { ; ALL-LABEL: store_i8 diff --git a/test/CodeGen/Mips/llvm-ir/sub.ll b/test/CodeGen/Mips/llvm-ir/sub.ll index 164975844d73..33757657ad91 100644 --- a/test/CodeGen/Mips/llvm-ir/sub.ll +++ b/test/CodeGen/Mips/llvm-ir/sub.ll @@ -1,37 +1,47 @@ ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=NOT-R2-R6,GP32,GP32-NOT-MM,NOT-MM ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=NOT-R2-R6,GP32,GP32-NOT-MM,NOT-MM ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=GP32-MM,GP32,MM +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=GP32-MM,GP32,MM ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=R2-R6,GP64,NOT-MM ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=R2-R6,GP64,NOT-MM ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=R2-R6,GP64,NOT-MM ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=R2-R6,GP64,NOT-MM +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=GP64,MM define signext i1 @sub_i1(i1 signext %a, i1 signext %b) { entry: ; ALL-LABEL: sub_i1: - ; ALL: subu $[[T0:[0-9]+]], $4, $5 - ; ALL: sll $[[T0]], $[[T0]], 31 - ; ALL: sra $2, $[[T0]], 31 + ; NOT-MM: subu $[[T0:[0-9]+]], $4, $5 + ; NOT-MM: sll $[[T0]], $[[T0]], 31 + ; NOT-MM: sra $2, $[[T0]], 31 + + ; MM: subu16 $[[T0:[0-9]+]], $4, $5 + ; MM: sll $[[T1:[0-9]+]], $[[T0]], 31 + ; MM: sra $[[T0]], $[[T1]], 31 %r = sub i1 %a, %b ret i1 %r @@ -48,6 +58,9 @@ entry: ; R2-R6: subu $[[T0:[0-9]+]], $4, $5 ; R2-R6: seb $2, $[[T0:[0-9]+]] + ; MM: subu16 $[[T0:[0-9]+]], $4, $5 + ; MM: seb $[[T0]], $[[T0]] + %r = sub i8 %a, %b ret i8 %r } @@ -63,6 +76,9 @@ entry: ; R2-R6: subu $[[T0:[0-9]+]], $4, $5 ; R2-R6: seh $2, $[[T0:[0-9]+]] + ; MM: subu16 $[[T0:[0-9]+]], $4, $5 + ; MM: seh $[[T0]], $[[T0]] + %r = sub i16 %a, %b ret i16 %r } @@ -71,7 +87,9 @@ define signext i32 @sub_i32(i32 signext %a, i32 signext %b) { entry: ; ALL-LABEL: sub_i32: - ; ALL: subu $2, $4, $5 + ; NOT-MM: subu $2, $4, $5 + + ; MM: subu16 $2, $4, $5 %r = sub i32 %a, %b ret i32 %r @@ -96,26 +114,42 @@ define signext i128 @sub_i128(i128 signext %a, i128 signext %b) { entry: ; ALL-LABEL: sub_i128: - ; GP32: lw $[[T0:[0-9]+]], 20($sp) - ; GP32: sltu $[[T1:[0-9]+]], $5, $[[T0]] - ; GP32: lw $[[T2:[0-9]+]], 16($sp) - ; GP32: addu $[[T3:[0-9]+]], $[[T1]], $[[T2]] - ; GP32: lw $[[T4:[0-9]+]], 24($sp) - ; GP32: lw $[[T5:[0-9]+]], 28($sp) - ; GP32: subu $[[T6:[0-9]+]], $7, $[[T5]] - ; GP32: subu $2, $4, $[[T3]] - ; GP32: sltu $[[T8:[0-9]+]], $6, $[[T4]] - ; GP32: addu $[[T9:[0-9]+]], $[[T8]], $[[T0]] - ; GP32: subu $3, $5, $[[T9]] - ; GP32: sltu $[[T10:[0-9]+]], $7, $[[T5]] - ; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T4]] - ; GP32: subu $4, $6, $[[T11]] - ; GP32: move $5, $[[T6]] - - ; GP64: dsubu $3, $5, $7 - ; GP64: sltu $[[T0:[0-9]+]], $5, $7 - ; GP64: daddu $[[T1:[0-9]+]], $[[T0]], $6 - ; GP64: dsubu $2, $4, $[[T1]] + ; GP32-NOT-MM: lw $[[T0:[0-9]+]], 20($sp) + ; GP32-NOT-MM: sltu $[[T1:[0-9]+]], $5, $[[T0]] + ; GP32-NOT-MM: lw $[[T2:[0-9]+]], 16($sp) + ; GP32-NOT-MM: addu $[[T3:[0-9]+]], $[[T1]], $[[T2]] + ; GP32-NOT-MM: lw $[[T4:[0-9]+]], 24($sp) + ; GP32-NOT-MM: lw $[[T5:[0-9]+]], 28($sp) + ; GP32-NOT-MM: subu $[[T6:[0-9]+]], $7, $[[T5]] + ; GP32-NOT-MM: subu $2, $4, $[[T3]] + ; GP32-NOT-MM: sltu $[[T8:[0-9]+]], $6, $[[T4]] + ; GP32-NOT-MM: addu $[[T9:[0-9]+]], $[[T8]], $[[T0]] + ; GP32-NOT-MM: subu $3, $5, $[[T9]] + ; GP32-NOT-MM: sltu $[[T10:[0-9]+]], $7, $[[T5]] + ; GP32-NOT-MM: addu $[[T11:[0-9]+]], $[[T10]], $[[T4]] + ; GP32-NOT-MM: subu $4, $6, $[[T11]] + ; GP32-NOT-MM: move $5, $[[T6]] + + ; GP32-MM: lw $[[T0:[0-9]+]], 20($sp) + ; GP32-MM: sltu $[[T1:[0-9]+]], $[[T2:[0-9]+]], $[[T0]] + ; GP32-MM: lw $[[T3:[0-9]+]], 16($sp) + ; GP32-MM: addu $[[T3]], $[[T1]], $[[T3]] + ; GP32-MM: lw $[[T4:[0-9]+]], 28($sp) + ; GP32-MM: subu $[[T1]], $7, $[[T4]] + ; GP32-MM: subu $[[T3]], $[[T5:[0-9]+]], $[[T3]] + ; GP32-MM: lw $[[T5]], 24($sp) + ; GP32-MM: sltu $[[T6:[0-9]+]], $6, $[[T5]] + ; GP32-MM: addu $[[T0]], $[[T6]], $[[T0]] + ; GP32-MM: subu $[[T0]], $5, $[[T0]] + ; GP32-MM: sltu $[[T2]], $7, $[[T4]] + ; GP32-MM: addu $[[T5]], $[[T2]], $[[T5]] + ; GP32-MM: subu $[[T5]], $6, $[[T5]] + ; GP32-MM: move $[[T2]], $[[T1]] + + ; GP64: dsubu $3, $5, $7 + ; GP64: sltu $[[T0:[0-9]+]], $5, $7 + ; GP64: daddu $[[T1:[0-9]+]], $[[T0]], $6 + ; GP64: dsubu $2, $4, $[[T1]] %r = sub i128 %a, %b ret i128 %r diff --git a/test/CodeGen/Mips/llvm-ir/udiv.ll b/test/CodeGen/Mips/llvm-ir/udiv.ll index a7cafe52d1ac..6f4dcb5d7bb5 100644 --- a/test/CodeGen/Mips/llvm-ir/udiv.ll +++ b/test/CodeGen/Mips/llvm-ir/udiv.ll @@ -1,29 +1,37 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=R6 -check-prefix=GP32 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=R6 -check-prefix=64R6 +; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,R6,GP32 + +; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,R6,64R6 + +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR3,MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM64 define zeroext i1 @udiv_i1(i1 zeroext %a, i1 zeroext %b) { entry: @@ -36,6 +44,13 @@ entry: ; R6: divu $2, $4, $5 ; R6: teq $5, $zero, 7 + ; MMR3: divu $zero, $4, $5 + ; MMR3: teq $5, $zero, 7 + ; MMR3: mflo $2 + + ; MMR6: divu $2, $4, $5 + ; MMR6: teq $5, $zero, 7 + %r = udiv i1 %a, %b ret i1 %r } @@ -51,6 +66,13 @@ entry: ; R6: divu $2, $4, $5 ; R6: teq $5, $zero, 7 + ; MMR3: divu $zero, $4, $5 + ; MMR3: teq $5, $zero, 7 + ; MMR3: mflo $2 + + ; MMR6: divu $2, $4, $5 + ; MMR6: teq $5, $zero, 7 + %r = udiv i8 %a, %b ret i8 %r } @@ -66,6 +88,13 @@ entry: ; R6: divu $2, $4, $5 ; R6: teq $5, $zero, 7 + ; MMR3: divu $zero, $4, $5 + ; MMR3: teq $5, $zero, 7 + ; MMR3: mflo $2 + + ; MMR6: divu $2, $4, $5 + ; MMR6: teq $5, $zero, 7 + %r = udiv i16 %a, %b ret i16 %r } @@ -81,6 +110,13 @@ entry: ; R6: divu $2, $4, $5 ; R6: teq $5, $zero, 7 + ; MMR3: divu $zero, $4, $5 + ; MMR3: teq $5, $zero, 7 + ; MMR3: mflo $2 + + ; MMR6: divu $2, $4, $5 + ; MMR6: teq $5, $zero, 7 + %r = udiv i32 %a, %b ret i32 %r } @@ -98,6 +134,11 @@ entry: ; 64R6: ddivu $2, $4, $5 ; 64R6: teq $5, $zero, 7 + ; MM32: lw $25, %call16(__udivdi3)($2) + + ; MM64: ddivu $2, $4, $5 + ; MM64: teq $5, $zero, 7 + %r = udiv i64 %a, %b ret i64 %r } @@ -111,6 +152,10 @@ entry: ; GP64-NOT-R6: ld $25, %call16(__udivti3)($gp) ; 64-R6: ld $25, %call16(__udivti3)($gp) + ; MM32: lw $25, %call16(__udivti3)($2) + + ; MM64: ld $25, %call16(__udivti3)($2) + %r = udiv i128 %a, %b ret i128 %r } diff --git a/test/CodeGen/Mips/llvm-ir/urem.ll b/test/CodeGen/Mips/llvm-ir/urem.ll index d5a231c8dfca..69b13ba7fee6 100644 --- a/test/CodeGen/Mips/llvm-ir/urem.ll +++ b/test/CodeGen/Mips/llvm-ir/urem.ll @@ -1,32 +1,37 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=GP32 \ -; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=GP32 \ -; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=GP32 \ -; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=GP32 -check-prefix=R6 -check-prefix=R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=64R6 -check-prefix=R6 -check-prefix=R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,NOT-R6,NOT-R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,NOT-R6,NOT-R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,R6,R2-R6 + +; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64-NOT-R6,NOT-R6,NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64-NOT-R6,NOT-R6,NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64-NOT-R6,NOT-R6,NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,64R6,R6,R2-R6 + +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR3,MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM64 define signext i1 @urem_i1(i1 signext %a, i1 signext %b) { entry: @@ -47,6 +52,21 @@ entry: ; R6: sll $[[T3:[0-9]+]], $[[T2]], 31 ; R6: sra $2, $[[T3]], 31 + ; MMR3: andi16 $[[T0:[0-9]+]], $5, 1 + ; MMR3: andi16 $[[T1:[0-9]+]], $4, 1 + ; MMR3: divu $zero, $[[T1]], $[[T0]] + ; MMR3: teq $[[T0]], $zero, 7 + ; MMR3: mfhi $[[T2:[0-9]+]] + ; MMR3: sll $[[T3:[0-9]+]], $[[T2]], 31 + ; MMR3: sra $2, $[[T3]], 31 + + ; MMR6: andi16 $[[T0:[0-9]+]], $5, 1 + ; MMR6: andi16 $[[T1:[0-9]+]], $4, 1 + ; MMR6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] + ; MMR6: teq $[[T0]], $zero, 7 + ; MMR6: sll $[[T3:[0-9]+]], $[[T2]], 31 + ; MMR6: sra $2, $[[T3]], 31 + %r = urem i1 %a, %b ret i1 %r } @@ -76,6 +96,19 @@ entry: ; R6: teq $[[T0]], $zero, 7 ; R6: seb $2, $[[T2]] + ; MMR3: andi16 $[[T0:[0-9]+]], $5, 255 + ; MMR3: andi16 $[[T1:[0-9]+]], $4, 255 + ; MMR3: divu $zero, $[[T1]], $[[T0]] + ; MMR3: teq $[[T0]], $zero, 7 + ; MMR3: mfhi $[[T2:[0-9]+]] + ; MMR3: seb $2, $[[T2]] + + ; MMR6: andi16 $[[T0:[0-9]+]], $5, 255 + ; MMR6: andi16 $[[T1:[0-9]+]], $4, 255 + ; MMR6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] + ; MMR6: teq $[[T0]], $zero, 7 + ; MMR6: seb $2, $[[T2]] + %r = urem i8 %a, %b ret i8 %r } @@ -105,6 +138,19 @@ entry: ; R6: teq $[[T0]], $zero, 7 ; R6: seh $2, $[[T2]] + ; MMR3: andi16 $[[T0:[0-9]+]], $5, 65535 + ; MMR3: andi16 $[[T1:[0-9]+]], $4, 65535 + ; MMR3: divu $zero, $[[T1]], $[[T0]] + ; MMR3: teq $[[T0]], $zero, 7 + ; MMR3: mfhi $[[T2:[0-9]+]] + ; MMR3: seh $2, $[[T2]] + + ; MMR6: andi16 $[[T0:[0-9]+]], $5, 65535 + ; MMR6: andi16 $[[T1:[0-9]+]], $4, 65535 + ; MMR6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] + ; MMR6: teq $[[T0]], $zero, 7 + ; MMR6: seh $2, $[[T2]] + %r = urem i16 %a, %b ret i16 %r } @@ -120,6 +166,13 @@ entry: ; R6: modu $2, $4, $5 ; R6: teq $5, $zero, 7 + ; MMR3: divu $zero, $4, $5 + ; MMR3: teq $5, $zero, 7 + ; MMR3: mfhi $2 + + ; MMR6: modu $2, $4, $5 + ; MMR6: teq $5, $zero, 7 + %r = urem i32 %a, %b ret i32 %r } @@ -137,6 +190,11 @@ entry: ; 64R6: dmodu $2, $4, $5 ; 64R6: teq $5, $zero, 7 + ; MM32: lw $25, %call16(__umoddi3)($2) + + ; MM64: dmodu $2, $4, $5 + ; MM64: teq $5, $zero, 7 + %r = urem i64 %a, %b ret i64 %r } @@ -145,10 +203,14 @@ define signext i128 @urem_i128(i128 signext %a, i128 signext %b) { entry: ; ALL-LABEL: urem_i128: - ; GP32: lw $25, %call16(__umodti3)($gp) + ; GP32: lw $25, %call16(__umodti3)($gp) + + ; GP64-NOT-R6: ld $25, %call16(__umodti3)($gp) + ; 64R6: ld $25, %call16(__umodti3)($gp) + + ; MM32: lw $25, %call16(__umodti3)($2) - ; GP64-NOT-R6: ld $25, %call16(__umodti3)($gp) - ; 64-R6: ld $25, %call16(__umodti3)($gp) + ; MM64: ld $25, %call16(__umodti3)($2) %r = urem i128 %a, %b ret i128 %r diff --git a/test/CodeGen/Mips/llvm-ir/xor.ll b/test/CodeGen/Mips/llvm-ir/xor.ll index d3cc57484895..0ba696fbc339 100644 --- a/test/CodeGen/Mips/llvm-ir/xor.ll +++ b/test/CodeGen/Mips/llvm-ir/xor.ll @@ -1,35 +1,44 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM64 define signext i1 @xor_i1(i1 signext %a, i1 signext %b) { entry: ; ALL-LABEL: xor_i1: - ; ALL: xor $2, $4, $5 + ; GP32: xor $2, $4, $5 + + ; GP64: xor $2, $4, $5 + + ; MM: xor16 $[[T0:[0-9]+]], $5 + ; MM: move $2, $[[T0]] %r = xor i1 %a, %b ret i1 %r @@ -39,7 +48,12 @@ define signext i8 @xor_i8(i8 signext %a, i8 signext %b) { entry: ; ALL-LABEL: xor_i8: - ; ALL: xor $2, $4, $5 + ; GP32: xor $2, $4, $5 + + ; GP64: xor $2, $4, $5 + + ; MM: xor16 $[[T0:[0-9]+]], $5 + ; MM: move $2, $[[T0]] %r = xor i8 %a, %b ret i8 %r @@ -49,7 +63,12 @@ define signext i16 @xor_i16(i16 signext %a, i16 signext %b) { entry: ; ALL-LABEL: xor_i16: - ; ALL: xor $2, $4, $5 + ; GP32: xor $2, $4, $5 + + ; GP64: xor $2, $4, $5 + + ; MM: xor16 $[[T0:[0-9]+]], $5 + ; MM: move $2, $[[T0]] %r = xor i16 %a, %b ret i16 %r @@ -64,6 +83,12 @@ entry: ; GP64: xor $[[T0:[0-9]+]], $4, $5 ; GP64: sll $2, $[[T0]], 0 + ; MM32: xor16 $[[T0:[0-9]+]], $5 + ; MM32: move $2, $[[T0]] + + ; MM64: xor $[[T0:[0-9]+]], $4, $5 + ; MM64: sll $2, $[[T0]], 0 + %r = xor i32 %a, %b ret i32 %r } @@ -77,6 +102,13 @@ entry: ; GP64: xor $2, $4, $5 + ; MM32: xor16 $[[T0:[0-9]+]], $6 + ; MM32: xor16 $[[T1:[0-9]+]], $7 + ; MM32: move $2, $[[T0]] + ; MM32: move $3, $[[T1]] + + ; MM64: xor $2, $4, $5 + %r = xor i64 %a, %b ret i64 %r } @@ -97,6 +129,102 @@ entry: ; GP64: xor $2, $4, $6 ; GP64: xor $3, $5, $7 + ; MM32: lw $[[T0:[0-9]+]], 20($sp) + ; MM32: lw $[[T1:[0-9]+]], 16($sp) + ; MM32: xor16 $[[T1]], $4 + ; MM32: xor16 $[[T0]], $5 + ; MM32: lw $[[T2:[0-9]+]], 24($sp) + ; MM32: xor16 $[[T2]], $6 + ; MM32: lw $[[T3:[0-9]+]], 28($sp) + ; MM32: xor16 $[[T3]], $7 + + ; MM64: xor $2, $4, $6 + ; MM64: xor $3, $5, $7 + %r = xor i128 %a, %b ret i128 %r } + +define signext i1 @xor_i1_4(i1 signext %b) { +entry: +; ALL-LABEL: xor_i1_4: + + ; ALL: move $2, $4 + + %r = xor i1 4, %b + ret i1 %r +} + +define signext i8 @xor_i8_4(i8 signext %b) { +entry: +; ALL-LABEL: xor_i8_4: + + ; ALL: xori $2, $4, 4 + + %r = xor i8 4, %b + ret i8 %r +} + +define signext i16 @xor_i16_4(i16 signext %b) { +entry: +; ALL-LABEL: xor_i16_4: + + ; ALL: xori $2, $4, 4 + + %r = xor i16 4, %b + ret i16 %r +} + +define signext i32 @xor_i32_4(i32 signext %b) { +entry: +; ALL-LABEL: xor_i32_4: + + ; ALL: xori $2, $4, 4 + + %r = xor i32 4, %b + ret i32 %r +} + +define signext i64 @xor_i64_4(i64 signext %b) { +entry: +; ALL-LABEL: xor_i64_4: + + ; GP32: xori $3, $5, 4 + ; GP32: move $2, $4 + + ; GP64: xori $2, $4, 4 + + ; MM32: xori $3, $5, 4 + ; MM32: move $2, $4 + + ; MM64: xori $2, $4, 4 + + %r = xor i64 4, %b + ret i64 %r +} + +define signext i128 @xor_i128_4(i128 signext %b) { +entry: +; ALL-LABEL: xor_i128_4: + + ; GP32: xori $[[T0:[0-9]+]], $7, 4 + ; GP32: move $2, $4 + ; GP32: move $3, $5 + ; GP32: move $4, $6 + ; GP32: move $5, $[[T0]] + + ; GP64: xori $3, $5, 4 + ; GP64: move $2, $4 + + ; MM32: xori $[[T0:[0-9]+]], $7, 4 + ; MM32: move $2, $4 + ; MM32: move $3, $5 + ; MM32: move $4, $6 + ; MM32: move $5, $[[T0]] + + ; MM64: xori $3, $5, 4 + ; MM64: move $2, $4 + + %r = xor i128 4, %b + ret i128 %r +} |