diff options
Diffstat (limited to 'test/CodeGen/Mips')
59 files changed, 1253 insertions, 280 deletions
diff --git a/test/CodeGen/Mips/2008-06-05-Carry.ll b/test/CodeGen/Mips/2008-06-05-Carry.ll index 9d8e391f874e..c61e1cdedea7 100644 --- a/test/CodeGen/Mips/2008-06-05-Carry.ll +++ b/test/CodeGen/Mips/2008-06-05-Carry.ll @@ -1,19 +1,22 @@ -; RUN: llc < %s -march=mips -o %t -; RUN: grep subu %t | count 2 -; RUN: grep addu %t | count 4 - -target datalayout = -"e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-unknown-psp-elf" +; RUN: llc -march=mips < %s | FileCheck %s define i64 @add64(i64 %u, i64 %v) nounwind { entry: - %tmp2 = add i64 %u, %v +; CHECK: addu +; CHECK: sltu +; CHECK: addu +; CHECK: addu + %tmp2 = add i64 %u, %v ret i64 %tmp2 } define i64 @sub64(i64 %u, i64 %v) nounwind { entry: +; CHECK: sub64 +; CHECK: subu +; CHECK: sltu +; CHECK: addu +; CHECK: subu %tmp2 = sub i64 %u, %v ret i64 %tmp2 } diff --git a/test/CodeGen/Mips/2008-07-03-SRet.ll b/test/CodeGen/Mips/2008-07-03-SRet.ll index b1d20d93f187..afec7f65d607 100644 --- a/test/CodeGen/Mips/2008-07-03-SRet.ll +++ b/test/CodeGen/Mips/2008-07-03-SRet.ll @@ -1,17 +1,18 @@ -; RUN: llc < %s -march=mips | grep {sw.*(\$4)} | count 3 +; RUN: llc -march=mips < %s | FileCheck %s -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-unknown-psp-elf" - %struct.sret0 = type { i32, i32, i32 } +%struct.sret0 = type { i32, i32, i32 } define void @test0(%struct.sret0* noalias sret %agg.result, i32 %dummy) nounwind { entry: - getelementptr %struct.sret0* %agg.result, i32 0, i32 0 ; <i32*>:0 [#uses=1] - store i32 %dummy, i32* %0, align 4 - getelementptr %struct.sret0* %agg.result, i32 0, i32 1 ; <i32*>:1 [#uses=1] - store i32 %dummy, i32* %1, align 4 - getelementptr %struct.sret0* %agg.result, i32 0, i32 2 ; <i32*>:2 [#uses=1] - store i32 %dummy, i32* %2, align 4 - ret void +; CHECK: sw ${{[0-9]+}}, {{[0-9]+}}($4) +; CHECK: sw ${{[0-9]+}}, {{[0-9]+}}($4) +; CHECK: sw ${{[0-9]+}}, {{[0-9]+}}($4) + getelementptr %struct.sret0* %agg.result, i32 0, i32 0 ; <i32*>:0 [#uses=1] + store i32 %dummy, i32* %0, align 4 + getelementptr %struct.sret0* %agg.result, i32 0, i32 1 ; <i32*>:1 [#uses=1] + store i32 %dummy, i32* %1, align 4 + getelementptr %struct.sret0* %agg.result, i32 0, i32 2 ; <i32*>:2 [#uses=1] + store i32 %dummy, i32* %2, align 4 + ret void } diff --git a/test/CodeGen/Mips/2008-07-07-Float2Int.ll b/test/CodeGen/Mips/2008-07-07-Float2Int.ll index d804c7dcf317..4c552361d9da 100644 --- a/test/CodeGen/Mips/2008-07-07-Float2Int.ll +++ b/test/CodeGen/Mips/2008-07-07-Float2Int.ll @@ -1,16 +1,17 @@ -; RUN: llc < %s -march=mips | grep trunc.w.s | count 3 - -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-unknown-psp-elf" +; RUN: llc -march=mips < %s | FileCheck %s define i32 @fptoint(float %a) nounwind { entry: - fptosi float %a to i32 ; <i32>:0 [#uses=1] - ret i32 %0 +; CHECK: trunc.w.s + fptosi float %a to i32 ; <i32>:0 [#uses=1] + ret i32 %0 } define i32 @fptouint(float %a) nounwind { entry: - fptoui float %a to i32 ; <i32>:0 [#uses=1] - ret i32 %0 +; CHECK: fptouint +; CHECK: trunc.w.s +; CHECK: trunc.w.s + fptoui float %a to i32 ; <i32>:0 [#uses=1] + ret i32 %0 } diff --git a/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll b/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll index e0c745f34917..8479ad222d30 100644 --- a/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll +++ b/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll @@ -1,20 +1,16 @@ -; DISABLED: llc < %s -march=mips -o %t -; DISABLED: grep seh %t | count 1 -; DISABLED: grep seb %t | count 1 -; RUN: false -; XFAIL: * - -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-unknown-psp-elf" +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s define signext i8 @A(i8 %e.0, i8 signext %sum) nounwind { entry: +; CHECK: seb add i8 %sum, %e.0 ; <i8>:0 [#uses=1] ret i8 %0 } define signext i16 @B(i16 %e.0, i16 signext %sum) nounwind { entry: +; CHECK: seh add i16 %sum, %e.0 ; <i16>:0 [#uses=1] ret i16 %0 } diff --git a/test/CodeGen/Mips/2008-07-22-Cstpool.ll b/test/CodeGen/Mips/2008-07-22-Cstpool.ll index 94dfe35faba1..a8e54707ddb2 100644 --- a/test/CodeGen/Mips/2008-07-22-Cstpool.ll +++ b/test/CodeGen/Mips/2008-07-22-Cstpool.ll @@ -1,12 +1,13 @@ -; RUN: llc < %s -march=mips -o %t -; RUN: grep {CPI\[01\]_\[01\]:} %t | count 2 -; RUN: grep {.rodata.cst4,"aM",@progbits} %t | count 1 -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-unknown-psp-elf" +; RUN: llc -march=mips < %s | FileCheck %s define float @F(float %a) nounwind { +; CHECK: .rodata.cst4,"aM",@progbits entry: - fadd float %a, 0x4011333340000000 ; <float>:0 [#uses=1] - fadd float %0, 0x4010666660000000 ; <float>:1 [#uses=1] - ret float %1 +; CHECK: ($CPI0_{{[0-1]}}) +; CHECK: ($CPI0_{{[0,1]}}) +; CHECK: ($CPI0_{{[0,1]}}) +; CHECK: ($CPI0_{{[0,1]}}) + fadd float %a, 0x4011333340000000 ; <float>:0 [#uses=1] + fadd float %0, 0x4010666660000000 ; <float>:1 [#uses=1] + ret float %1 } diff --git a/test/CodeGen/Mips/2008-08-01-AsmInline.ll b/test/CodeGen/Mips/2008-08-01-AsmInline.ll index 23ed64a96d8e..dbde742ad3fe 100644 --- a/test/CodeGen/Mips/2008-08-01-AsmInline.ll +++ b/test/CodeGen/Mips/2008-08-01-AsmInline.ll @@ -1,17 +1,53 @@ -; RUN: llc < %s -march=mips -o %t -; RUN: grep mfhi %t | count 1 -; RUN: grep mflo %t | count 1 -; RUN: grep multu %t | count 1 +; RUN: llc -march=mips < %s | FileCheck %s +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-unknown-psp-elf" - %struct.DWstruct = type { i32, i32 } +%struct.DWstruct = type { i32, i32 } define i32 @A0(i32 %u, i32 %v) nounwind { entry: - %asmtmp = tail call %struct.DWstruct asm "multu $2,$3", "={lo},={hi},d,d"( i32 %u, i32 %v ) nounwind - %asmresult = extractvalue %struct.DWstruct %asmtmp, 0 - %asmresult1 = extractvalue %struct.DWstruct %asmtmp, 1 ; <i32> [#uses=1] +; CHECK: multu +; CHECK: mflo +; CHECK: mfhi + %asmtmp = tail call %struct.DWstruct asm "multu $2,$3", "={lo},={hi},d,d"( i32 %u, i32 %v ) nounwind + %asmresult = extractvalue %struct.DWstruct %asmtmp, 0 + %asmresult1 = extractvalue %struct.DWstruct %asmtmp, 1 ; <i32> [#uses=1] %res = add i32 %asmresult, %asmresult1 - ret i32 %res + ret i32 %res } + +@gi2 = external global i32 +@gi1 = external global i32 +@gi0 = external global i32 +@gf0 = external global float +@gf1 = external global float +@gd0 = external global double +@gd1 = external global double + +define void @foo0() nounwind { +entry: +; CHECK: addu + %0 = load i32* @gi1, align 4 + %1 = load i32* @gi0, align 4 + %2 = tail call i32 asm "addu $0, $1, $2", "=r,r,r"(i32 %0, i32 %1) nounwind + store i32 %2, i32* @gi2, align 4 + ret void +} + +define void @foo2() nounwind { +entry: +; CHECK: neg.s + %0 = load float* @gf1, align 4 + %1 = tail call float asm "neg.s $0, $1", "=f,f"(float %0) nounwind + store float %1, float* @gf0, align 4 + ret void +} + +define void @foo3() nounwind { +entry: +; CHECK: neg.d + %0 = load double* @gd1, align 8 + %1 = tail call double asm "neg.d $0, $1", "=f,f"(double %0) nounwind + store double %1, double* @gd0, align 8 + ret void +} + diff --git a/test/CodeGen/Mips/2008-08-04-Bitconvert.ll b/test/CodeGen/Mips/2008-08-04-Bitconvert.ll index f8eb02855979..78a49ffbe444 100644 --- a/test/CodeGen/Mips/2008-08-04-Bitconvert.ll +++ b/test/CodeGen/Mips/2008-08-04-Bitconvert.ll @@ -1,18 +1,15 @@ -; RUN: llc < %s -march=mips -o %t -; RUN: grep mtc1 %t | count 1 -; RUN: grep mfc1 %t | count 1 - -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-unknown-psp-elf" +; RUN: llc -march=mips < %s | FileCheck %s define float @A(i32 %u) nounwind { entry: - bitcast i32 %u to float - ret float %0 +; CHECK: mtc1 + bitcast i32 %u to float + ret float %0 } define i32 @B(float %u) nounwind { entry: - bitcast float %u to i32 - ret i32 %0 +; CHECK: mfc1 + bitcast float %u to i32 + ret i32 %0 } diff --git a/test/CodeGen/Mips/2008-08-06-Alloca.ll b/test/CodeGen/Mips/2008-08-06-Alloca.ll index 6dd4af111cd9..0d94b19e4629 100644 --- a/test/CodeGen/Mips/2008-08-06-Alloca.ll +++ b/test/CodeGen/Mips/2008-08-06-Alloca.ll @@ -1,17 +1,15 @@ -; RUN: llc < %s -march=mips | grep {subu.*sp} | count 2 -; RUN: llc < %s -march=mips -regalloc=basic | grep {subu.*sp} | count 2 - -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-unknown-psp-elf" +; RUN: llc -march=mips < %s | FileCheck %s define i32 @twoalloca(i32 %size) nounwind { entry: - alloca i8, i32 %size ; <i8*>:0 [#uses=1] - alloca i8, i32 %size ; <i8*>:1 [#uses=1] - call i32 @foo( i8* %0 ) nounwind ; <i32>:2 [#uses=1] - call i32 @foo( i8* %1 ) nounwind ; <i32>:3 [#uses=1] - add i32 %3, %2 ; <i32>:4 [#uses=1] - ret i32 %4 +; CHECK: subu ${{[0-9]+}}, $sp +; CHECK: subu ${{[0-9]+}}, $sp + alloca i8, i32 %size ; <i8*>:0 [#uses=1] + alloca i8, i32 %size ; <i8*>:1 [#uses=1] + call i32 @foo( i8* %0 ) nounwind ; <i32>:2 [#uses=1] + call i32 @foo( i8* %1 ) nounwind ; <i32>:3 [#uses=1] + add i32 %3, %2 ; <i32>:4 [#uses=1] + ret i32 %4 } declare i32 @foo(i8*) diff --git a/test/CodeGen/Mips/2008-08-08-ctlz.ll b/test/CodeGen/Mips/2008-08-08-ctlz.ll index fb3332329d6c..abd61de5a8d8 100644 --- a/test/CodeGen/Mips/2008-08-08-ctlz.ll +++ b/test/CodeGen/Mips/2008-08-08-ctlz.ll @@ -1,12 +1,10 @@ -; RUN: llc < %s -march=mips | grep clz | count 1 - -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-unknown-psp-elf" +; RUN: llc -march=mips < %s | FileCheck %s define i32 @A0(i32 %u) nounwind { entry: - call i32 @llvm.ctlz.i32( i32 %u ) +; CHECK: clz + call i32 @llvm.ctlz.i32( i32 %u, i1 true ) ret i32 %0 } -declare i32 @llvm.ctlz.i32(i32) nounwind readnone +declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone diff --git a/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll b/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll index f5188434670b..9c4838a87e51 100644 --- a/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll +++ b/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll @@ -1,7 +1,6 @@ -; RUN: llc < %s +; RUN: llc -march=mips -soft-float < %s ; PR2667 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "psp" %struct._Bigint = type { %struct._Bigint*, i32, i32, i32, i32, [1 x i32] } %struct.__FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*, i8*, i32)*, i32 (i8*, i8*, i32)*, i32 (i8*, i32, i32)*, i32 (i8*)*, %struct.__sbuf, i8*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i32, %struct._reent*, i32 } %struct.__sbuf = type { i8*, i32 } diff --git a/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll b/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll index b8d68269af42..2b2ee0fd7ad8 100644 --- a/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll +++ b/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll @@ -1,10 +1,23 @@ -; RUN: llc < %s | FileCheck %s -target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-n32" -target triple = "mips-unknown-linux" +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-O32 +; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-O32 +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n32 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N32 +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n32 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-N32 +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N64 +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-N64 define float @h() nounwind readnone { entry: -; CHECK: lw $2, %got($CPI0_0)($gp) -; CHECK: lwc1 $f0, %lo($CPI0_0)($2) +; PIC-O32: lw $[[R0:[0-9]+]], %got($CPI0_0) +; PIC-O32: lwc1 $f0, %lo($CPI0_0)($[[R0]]) +; STATIC-O32: lui $[[R0:[0-9]+]], %hi($CPI0_0) +; STATIC-O32: lwc1 $f0, %lo($CPI0_0)($[[R0]]) +; PIC-N32: lw $[[R0:[0-9]+]], %got_page($CPI0_0) +; PIC-N32: lwc1 $f0, %got_ofst($CPI0_0)($[[R0]]) +; STATIC-N32: lui $[[R0:[0-9]+]], %hi($CPI0_0) +; STATIC-N32: lwc1 $f0, %lo($CPI0_0)($[[R0]]) +; PIC-N64: ld $[[R0:[0-9]+]], %got_page($CPI0_0) +; PIC-N64: lwc1 $f0, %got_ofst($CPI0_0)($[[R0]]) +; STATIC-N64: ld $[[R0:[0-9]+]], %got_page($CPI0_0) +; STATIC-N64: lwc1 $f0, %got_ofst($CPI0_0)($[[R0]]) ret float 0x400B333340000000 } diff --git a/test/CodeGen/Mips/2010-07-20-Switch.ll b/test/CodeGen/Mips/2010-07-20-Switch.ll index 07fc10cae180..aaf6767a3bda 100644 --- a/test/CodeGen/Mips/2010-07-20-Switch.ll +++ b/test/CodeGen/Mips/2010-07-20-Switch.ll @@ -1,13 +1,25 @@ -; RUN: llc < %s -march=mips -relocation-model=static | FileCheck %s +; RUN: llc < %s -march=mips -relocation-model=static | FileCheck %s -check-prefix=STATIC-O32 +; RUN: llc < %s -march=mips -relocation-model=pic | FileCheck %s -check-prefix=PIC-O32 +; RUN: llc < %s -march=mips64 -relocation-model=pic -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=PIC-N64 define i32 @main() nounwind readnone { entry: %x = alloca i32, align 4 ; <i32*> [#uses=2] - volatile store i32 2, i32* %x, align 4 - %0 = volatile load i32* %x, align 4 ; <i32> [#uses=1] -; CHECK: lui $3, %hi($JTI0_0) -; CHECK: sll $2, $2, 2 -; CHECK: addiu $3, $3, %lo($JTI0_0) + store volatile i32 2, i32* %x, align 4 + %0 = load volatile i32* %x, align 4 ; <i32> [#uses=1] +; STATIC-O32: lui $[[R0:[0-9]+]], %hi($JTI0_0) +; STATIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo($JTI0_0) +; STATIC-O32: sll ${{[0-9]+}}, ${{[0-9]+}}, 2 +; PIC-O32: lw $[[R0:[0-9]+]], %got($JTI0_0) +; PIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo($JTI0_0) +; PIC-O32: sll ${{[0-9]+}}, ${{[0-9]+}}, 2 +; PIC-O32: addu $[[R1:[0-9]+]], ${{[0-9]+}}, $gp +; PIC-O32: jr $[[R1]] +; PIC-N64: ld $[[R0:[0-9]+]], %got_page($JTI0_0) +; PIC-N64: daddiu ${{[0-9]+}}, $[[R0]], %got_ofst($JTI0_0) +; PIC-N64: dsll ${{[0-9]+}}, ${{[0-9]+}}, 3 +; PIC-N64: daddu $[[R1:[0-9]+]], ${{[0-9]+}}, $gp +; PIC-N64: jr $[[R1]] switch i32 %0, label %bb4 [ i32 0, label %bb5 i32 1, label %bb1 @@ -18,7 +30,7 @@ entry: bb1: ; preds = %entry ret i32 2 -; CHECK: $BB0_2 +; CHECK: STATIC-O32: $BB0_2 bb2: ; preds = %entry ret i32 0 @@ -31,3 +43,23 @@ bb4: ; preds = %entry bb5: ; preds = %entry ret i32 1 } + +; STATIC-O32: .align 2 +; STATIC-O32: $JTI0_0: +; STATIC-O32: .4byte +; STATIC-O32: .4byte +; STATIC-O32: .4byte +; STATIC-O32: .4byte +; PIC-O32: .align 2 +; PIC-O32: $JTI0_0: +; PIC-O32: .gpword +; PIC-O32: .gpword +; PIC-O32: .gpword +; PIC-O32: .gpword +; PIC-N64: .align 3 +; PIC-N64: $JTI0_0: +; PIC-N64: .gpdword +; PIC-N64: .gpdword +; PIC-N64: .gpdword +; PIC-N64: .gpdword + diff --git a/test/CodeGen/Mips/2010-11-09-CountLeading.ll b/test/CodeGen/Mips/2010-11-09-CountLeading.ll index c592b311782f..6174500d3e0b 100644 --- a/test/CodeGen/Mips/2010-11-09-CountLeading.ll +++ b/test/CodeGen/Mips/2010-11-09-CountLeading.ll @@ -3,16 +3,16 @@ ; CHECK: clz $2, $4 define i32 @t1(i32 %X) nounwind readnone { entry: - %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X) + %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X, i1 true) ret i32 %tmp1 } -declare i32 @llvm.ctlz.i32(i32) nounwind readnone +declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone ; CHECK: clz $2, $4 define i32 @t2(i32 %X) nounwind readnone { entry: - %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X) + %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X, i1 true) ret i32 %tmp1 } @@ -20,7 +20,7 @@ entry: define i32 @t3(i32 %X) nounwind readnone { entry: %neg = xor i32 %X, -1 - %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg) + %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg, i1 true) ret i32 %tmp1 } @@ -28,6 +28,6 @@ entry: define i32 @t4(i32 %X) nounwind readnone { entry: %neg = xor i32 %X, -1 - %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg) + %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg, i1 true) ret i32 %tmp1 } diff --git a/test/CodeGen/Mips/blockaddr.ll b/test/CodeGen/Mips/blockaddr.ll index 6de6b7781b24..7de7fa6f6bdb 100644 --- a/test/CodeGen/Mips/blockaddr.ll +++ b/test/CodeGen/Mips/blockaddr.ll @@ -1,5 +1,9 @@ -; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=CHECK-PIC -; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-O32 +; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-O32 +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n32 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N32 +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n32 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-N32 +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N64 +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-N64 @reg = common global i8* null, align 4 @@ -8,14 +12,30 @@ entry: ret i8* %x } -; CHECK-PIC: lw $[[R0:[0-9]+]], %got($tmp[[T0:[0-9]+]])($gp) -; CHECK-PIC: addiu ${{[0-9]+}}, $[[R0]], %lo($tmp[[T0]]) -; CHECK-PIC: lw $[[R1:[0-9]+]], %got($tmp[[T1:[0-9]+]])($gp) -; CHECK-PIC: addiu ${{[0-9]+}}, $[[R1]], %lo($tmp[[T1]]) -; CHECK-STATIC: lui $[[R2:[0-9]+]], %hi($tmp[[T0:[0-9]+]]) -; CHECK-STATIC: addiu ${{[0-9]+}}, $[[R2]], %lo($tmp[[T0]]) -; CHECK-STATIC: lui $[[R3:[0-9]+]], %hi($tmp[[T1:[0-9]+]]) -; CHECK-STATIC: addiu ${{[0-9]+}}, $[[R3]], %lo($tmp[[T1]]) +; PIC-O32: lw $[[R0:[0-9]+]], %got($tmp[[T0:[0-9]+]]) +; PIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo($tmp[[T0]]) +; PIC-O32: lw $[[R1:[0-9]+]], %got($tmp[[T1:[0-9]+]]) +; PIC-O32: addiu ${{[0-9]+}}, $[[R1]], %lo($tmp[[T1]]) +; STATIC-O32: lui $[[R2:[0-9]+]], %hi($tmp[[T2:[0-9]+]]) +; STATIC-O32: addiu ${{[0-9]+}}, $[[R2]], %lo($tmp[[T2]]) +; STATIC-O32: lui $[[R3:[0-9]+]], %hi($tmp[[T3:[0-9]+]]) +; STATIC-O32: addiu ${{[0-9]+}}, $[[R3]], %lo($tmp[[T3]]) +; PIC-N32: lw $[[R0:[0-9]+]], %got_page($tmp[[T0:[0-9]+]]) +; PIC-N32: addiu ${{[0-9]+}}, $[[R0]], %got_ofst($tmp[[T0]]) +; PIC-N32: lw $[[R1:[0-9]+]], %got_page($tmp[[T1:[0-9]+]]) +; PIC-N32: addiu ${{[0-9]+}}, $[[R1]], %got_ofst($tmp[[T1]]) +; STATIC-N32: lui $[[R2:[0-9]+]], %hi($tmp[[T2:[0-9]+]]) +; STATIC-N32: addiu ${{[0-9]+}}, $[[R2]], %lo($tmp[[T2]]) +; STATIC-N32: lui $[[R3:[0-9]+]], %hi($tmp[[T3:[0-9]+]]) +; STATIC-N32: addiu ${{[0-9]+}}, $[[R3]], %lo($tmp[[T3]]) +; PIC-N64: ld $[[R0:[0-9]+]], %got_page($tmp[[T0:[0-9]+]]) +; PIC-N64: daddiu ${{[0-9]+}}, $[[R0]], %got_ofst($tmp[[T0]]) +; PIC-N64: ld $[[R1:[0-9]+]], %got_page($tmp[[T1:[0-9]+]]) +; PIC-N64: daddiu ${{[0-9]+}}, $[[R1]], %got_ofst($tmp[[T1]]) +; STATIC-N64: ld $[[R2:[0-9]+]], %got_page($tmp[[T2:[0-9]+]]) +; STATIC-N64: daddiu ${{[0-9]+}}, $[[R2]], %got_ofst($tmp[[T2]]) +; STATIC-N64: ld $[[R3:[0-9]+]], %got_page($tmp[[T3:[0-9]+]]) +; STATIC-N64: daddiu ${{[0-9]+}}, $[[R3]], %got_ofst($tmp[[T3]]) define void @f() nounwind { entry: %call = tail call i8* @dummy(i8* blockaddress(@f, %baz)) diff --git a/test/CodeGen/Mips/br-jmp.ll b/test/CodeGen/Mips/br-jmp.ll new file mode 100644 index 000000000000..1b5513ab394d --- /dev/null +++ b/test/CodeGen/Mips/br-jmp.ll @@ -0,0 +1,13 @@ +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=CHECK-PIC +; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC + +define void @count(i32 %x, i32 %y, i32 %z) noreturn nounwind readnone { +entry: + br label %bosco + +bosco: ; preds = %bosco, %entry + br label %bosco +} + +; CHECK-PIC: b $BB0_1 +; CHECK-STATIC: j $BB0_1 diff --git a/test/CodeGen/Mips/bswap.ll b/test/CodeGen/Mips/bswap.ll new file mode 100644 index 000000000000..a8fc2cdc7431 --- /dev/null +++ b/test/CodeGen/Mips/bswap.ll @@ -0,0 +1,25 @@ +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=MIPS32 +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64 + +define i32 @bswap32(i32 %x) nounwind readnone { +entry: +; MIPS32: bswap32: +; MIPS32: wsbh $[[R0:[0-9]+]] +; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16 + %or.3 = call i32 @llvm.bswap.i32(i32 %x) + ret i32 %or.3 +} + +define i64 @bswap64(i64 %x) nounwind readnone { +entry: +; MIPS64: bswap64: +; MIPS64: dsbh $[[R0:[0-9]+]] +; MIPS64: dshd ${{[0-9]+}}, $[[R0]] + %or.7 = call i64 @llvm.bswap.i64(i64 %x) + ret i64 %or.7 +} + +declare i32 @llvm.bswap.i32(i32) nounwind readnone + +declare i64 @llvm.bswap.i64(i64) nounwind readnone + diff --git a/test/CodeGen/Mips/cmov.ll b/test/CodeGen/Mips/cmov.ll index 7851ba90d6b1..03254a9a799a 100755 --- a/test/CodeGen/Mips/cmov.ll +++ b/test/CodeGen/Mips/cmov.ll @@ -1,11 +1,14 @@ -; RUN: llc -march=mips < %s | FileCheck %s -; RUN: llc -march=mips -regalloc=basic < %s | FileCheck %s +; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=O32 +; RUN: llc -march=mips -regalloc=basic < %s | FileCheck %s -check-prefix=O32 +; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64 < %s | FileCheck %s -check-prefix=N64 @i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4 @i3 = common global i32* null, align 4 -; CHECK: addiu ${{[0-9]+}}, $gp, %got(i1) -; CHECK: lw ${{[0-9]+}}, %got(i3)($gp) +; O32: lw ${{[0-9]+}}, %got(i3)($gp) +; O32: addiu ${{[0-9]+}}, $gp, %got(i1) +; N64: ld ${{[0-9]+}}, %got_disp(i3)($gp) +; N64: daddiu ${{[0-9]+}}, $gp, %got_disp(i1) define i32* @cmov1(i32 %s) nounwind readonly { entry: %tobool = icmp ne i32 %s, 0 @@ -17,10 +20,14 @@ entry: @c = global i32 1, align 4 @d = global i32 0, align 4 -; CHECK: cmov2: -; CHECK: addiu $[[R0:[0-9]+]], $gp, %got(c) -; CHECK: addiu $[[R1:[0-9]+]], $gp, %got(d) -; CHECK: movn $[[R1]], $[[R0]], ${{[0-9]+}} +; O32: cmov2: +; O32: addiu $[[R1:[0-9]+]], $gp, %got(d) +; O32: addiu $[[R0:[0-9]+]], $gp, %got(c) +; O32: movn $[[R1]], $[[R0]], ${{[0-9]+}} +; N64: cmov2: +; N64: daddiu $[[R1:[0-9]+]], $gp, %got_disp(d) +; N64: daddiu $[[R0:[0-9]+]], $gp, %got_disp(c) +; N64: movn $[[R1]], $[[R0]], ${{[0-9]+}} define i32 @cmov2(i32 %s) nounwind readonly { entry: %tobool = icmp ne i32 %s, 0 diff --git a/test/CodeGen/Mips/cprestore.ll b/test/CodeGen/Mips/cprestore.ll index 391f5c714dbb..57d022f47c82 100644 --- a/test/CodeGen/Mips/cprestore.ll +++ b/test/CodeGen/Mips/cprestore.ll @@ -1,11 +1,9 @@ -; DISABLED: llc -march=mipsel < %s | FileCheck %s -; RUN: false - -; byval is currently unsupported. -; XFAIL: * +; RUN: llc -march=mipsel < %s | FileCheck %s ; CHECK: .set macro +; CHECK: .set at ; CHECK-NEXT: .cprestore +; CHECK: .set noat ; CHECK-NEXT: .set nomacro %struct.S = type { [16384 x i32] } diff --git a/test/CodeGen/Mips/dg.exp b/test/CodeGen/Mips/dg.exp deleted file mode 100644 index adb2cac9a6b0..000000000000 --- a/test/CodeGen/Mips/dg.exp +++ /dev/null @@ -1,5 +0,0 @@ -load_lib llvm.exp - -if { [llvm_supports_target Mips] } { - RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]] -} diff --git a/test/CodeGen/Mips/eh.ll b/test/CodeGen/Mips/eh.ll index 9cd34131a131..c3facdbc5556 100644 --- a/test/CodeGen/Mips/eh.ll +++ b/test/CodeGen/Mips/eh.ll @@ -10,15 +10,11 @@ entry: ; CHECK-EL: .cfi_def_cfa_offset ; CHECK-EL: sdc1 $f20 ; CHECK-EL: sw $ra -; CHECK-EL: sw $17 -; CHECK-EL: sw $16 ; CHECK-EL: .cfi_offset 52, -8 ; CHECK-EL: .cfi_offset 53, -4 ; CHECK-EB: .cfi_offset 53, -8 ; CHECK-EB: .cfi_offset 52, -4 ; CHECK-EL: .cfi_offset 31, -12 -; CHECK-EL: .cfi_offset 17, -16 -; CHECK-EL: .cfi_offset 16, -20 ; CHECK-EL: .cprestore %exception = tail call i8* @__cxa_allocate_exception(i32 8) nounwind @@ -58,16 +54,10 @@ unreachable: ; preds = %entry declare i8* @__cxa_allocate_exception(i32) -declare i8* @llvm.eh.exception() nounwind readonly - declare i32 @__gxx_personality_v0(...) -declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind - declare i32 @llvm.eh.typeid.for(i8*) nounwind -declare void @llvm.eh.resume(i8*, i32) - declare void @__cxa_throw(i8*, i8*, i8*) declare i8* @__cxa_begin_catch(i8*) diff --git a/test/CodeGen/Mips/extins.ll b/test/CodeGen/Mips/extins.ll index 69f53e503f6d..a164f7047b5c 100644 --- a/test/CodeGen/Mips/extins.ll +++ b/test/CodeGen/Mips/extins.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s +; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s define i32 @ext0_5_9(i32 %s, i32 %pos, i32 %sz) nounwind readnone { entry: diff --git a/test/CodeGen/Mips/fabs.ll b/test/CodeGen/Mips/fabs.ll new file mode 100644 index 000000000000..b296ab390d56 --- /dev/null +++ b/test/CodeGen/Mips/fabs.ll @@ -0,0 +1,52 @@ +; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=32 +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2 +; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=64 +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 | FileCheck %s -check-prefix=64R2 +; RUN: llc < %s -march=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefix=NO-NAN + +define float @foo0(float %a) nounwind readnone { +entry: + +; 32: lui $[[T0:[0-9]+]], 32767 +; 32: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 +; 32: and $[[AND:[0-9]+]], ${{[0-9]+}}, $[[MSK0]] +; 32: mtc1 $[[AND]], $f0 + +; 32R2: ins $[[INS:[0-9]+]], $zero, 31, 1 +; 32R2: mtc1 $[[INS]], $f0 + +; NO-NAN: abs.s + + %call = tail call float @fabsf(float %a) nounwind readnone + ret float %call +} + +declare float @fabsf(float) nounwind readnone + +define double @foo1(double %a) nounwind readnone { +entry: + +; 32: lui $[[T0:[0-9]+]], 32767 +; 32: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 +; 32: and $[[AND:[0-9]+]], ${{[0-9]+}}, $[[MSK0]] +; 32: mtc1 $[[AND]], $f1 + +; 32R2: ins $[[INS:[0-9]+]], $zero, 31, 1 +; 32R2: mtc1 $[[INS]], $f1 + +; 64: daddiu $[[T0:[0-9]+]], $zero, 1 +; 64: dsll $[[T1:[0-9]+]], ${{[0-9]+}}, 63 +; 64: daddiu $[[MSK0:[0-9]+]], $[[T1]], -1 +; 64: and $[[AND:[0-9]+]], ${{[0-9]+}}, $[[MSK0]] +; 64: dmtc1 $[[AND]], $f0 + +; 64R2: dins $[[INS:[0-9]+]], $zero, 63, 1 +; 64R2: dmtc1 $[[INS]], $f0 + +; NO-NAN: abs.d + + %call = tail call double @fabs(double %a) nounwind readnone + ret double %call +} + +declare double @fabs(double) nounwind readnone diff --git a/test/CodeGen/Mips/fcopysign-f32-f64.ll b/test/CodeGen/Mips/fcopysign-f32-f64.ll new file mode 100644 index 000000000000..b36473d6f57a --- /dev/null +++ b/test/CodeGen/Mips/fcopysign-f32-f64.ll @@ -0,0 +1,50 @@ +; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=64 +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 | FileCheck %s -check-prefix=64R2 + +declare double @copysign(double, double) nounwind readnone + +declare float @copysignf(float, float) nounwind readnone + +define float @func2(float %d, double %f) nounwind readnone { +entry: +; 64: func2 +; 64: lui $[[T0:[0-9]+]], 32767 +; 64: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 +; 64: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]] +; 64: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 63 +; 64: sll $[[SLL:[0-9]+]], ${{[0-9]+}}, 31 +; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[SLL]] +; 64: mtc1 $[[OR]], $f0 + +; 64R2: dext ${{[0-9]+}}, ${{[0-9]+}}, 63, 1 +; 64R2: ins $[[INS:[0-9]+]], ${{[0-9]+}}, 31, 1 +; 64R2: mtc1 $[[INS]], $f0 + + %add = fadd float %d, 1.000000e+00 + %conv = fptrunc double %f to float + %call = tail call float @copysignf(float %add, float %conv) nounwind readnone + ret float %call +} + +define double @func3(double %d, float %f) nounwind readnone { +entry: + +; 64: daddiu $[[T0:[0-9]+]], $zero, 1 +; 64: dsll $[[T1:[0-9]+]], $[[T0]], 63 +; 64: daddiu $[[MSK0:[0-9]+]], $[[T1]], -1 +; 64: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]] +; 64: srl ${{[0-9]+}}, ${{[0-9]+}}, 31 +; 64: dsll $[[DSLL:[0-9]+]], ${{[0-9]+}}, 63 +; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]] +; 64: dmtc1 $[[OR]], $f0 + +; 64R2: ext ${{[0-9]+}}, ${{[0-9]+}}, 31, 1 +; 64R2: dins $[[INS:[0-9]+]], ${{[0-9]+}}, 63, 1 +; 64R2: dmtc1 $[[INS]], $f0 + + %add = fadd double %d, 1.000000e+00 + %conv = fpext float %f to double + %call = tail call double @copysign(double %add, double %conv) nounwind readnone + ret double %call +} + diff --git a/test/CodeGen/Mips/fcopysign.ll b/test/CodeGen/Mips/fcopysign.ll index 79f956d719c5..1c57eca3c9ec 100644 --- a/test/CodeGen/Mips/fcopysign.ll +++ b/test/CodeGen/Mips/fcopysign.ll @@ -1,34 +1,35 @@ -; RUN: llc < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-EL -; RUN: llc < %s -march=mips | FileCheck %s -check-prefix=CHECK-EB +; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=32 +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2 +; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=64 +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 | FileCheck %s -check-prefix=64R2 define double @func0(double %d0, double %d1) nounwind readnone { entry: -; CHECK-EL: func0: -; CHECK-EL: lui $[[T0:[0-9]+]], 32767 -; CHECK-EL: lui $[[T1:[0-9]+]], 32768 -; CHECK-EL: mfc1 $[[HI0:[0-9]+]], $f13 -; CHECK-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 -; CHECK-EL: mfc1 $[[HI1:[0-9]+]], $f15 -; CHECK-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0 -; CHECK-EL: and $[[AND0:[0-9]+]], $[[HI0]], $[[MSK0]] -; CHECK-EL: and $[[AND1:[0-9]+]], $[[HI1]], $[[MSK1]] -; CHECK-EL: mfc1 $[[LO0:[0-9]+]], $f12 -; CHECK-EL: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]] -; CHECK-EL: mtc1 $[[LO0]], $f0 -; CHECK-EL: mtc1 $[[OR]], $f1 ; -; CHECK-EB: lui $[[T0:[0-9]+]], 32767 -; CHECK-EB: lui $[[T1:[0-9]+]], 32768 -; CHECK-EB: mfc1 $[[HI0:[0-9]+]], $f12 -; CHECK-EB: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 -; CHECK-EB: mfc1 $[[HI1:[0-9]+]], $f14 -; CHECK-EB: ori $[[MSK1:[0-9]+]], $[[T1]], 0 -; CHECK-EB: and $[[AND0:[0-9]+]], $[[HI0]], $[[MSK0]] -; CHECK-EB: and $[[AND1:[0-9]+]], $[[HI1]], $[[MSK1]] -; CHECK-EB: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]] -; CHECK-EB: mfc1 $[[LO0:[0-9]+]], $f13 -; CHECK-EB: mtc1 $[[OR]], $f0 -; CHECK-EB: mtc1 $[[LO0]], $f1 +; 32: lui $[[MSK1:[0-9]+]], 32768 +; 32: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]] +; 32: lui $[[T0:[0-9]+]], 32767 +; 32: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 +; 32: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]] +; 32: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]] +; 32: mtc1 $[[OR]], $f1 + +; 32R2: ext $[[EXT:[0-9]+]], ${{[0-9]+}}, 31, 1 +; 32R2: ins $[[INS:[0-9]+]], $[[EXT]], 31, 1 +; 32R2: mtc1 $[[INS]], $f1 + +; 64: daddiu $[[T0:[0-9]+]], $zero, 1 +; 64: dsll $[[MSK1:[0-9]+]], $[[T0]], 63 +; 64: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]] +; 64: daddiu $[[MSK0:[0-9]+]], $[[MSK1]], -1 +; 64: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]] +; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]] +; 64: dmtc1 $[[OR]], $f0 + +; 64R2: dext $[[EXT:[0-9]+]], ${{[0-9]+}}, 63, 1 +; 64R2: dins $[[INS:[0-9]+]], $[[EXT]], 63, 1 +; 64R2: dmtc1 $[[INS]], $f0 + %call = tail call double @copysign(double %d0, double %d1) nounwind readnone ret double %call } @@ -37,19 +38,22 @@ declare double @copysign(double, double) nounwind readnone define float @func1(float %f0, float %f1) nounwind readnone { entry: -; CHECK-EL: func1: -; CHECK-EL: lui $[[T0:[0-9]+]], 32767 -; CHECK-EL: lui $[[T1:[0-9]+]], 32768 -; CHECK-EL: mfc1 $[[ARG0:[0-9]+]], $f12 -; CHECK-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 -; CHECK-EL: mfc1 $[[ARG1:[0-9]+]], $f14 -; CHECK-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0 -; CHECK-EL: and $[[T2:[0-9]+]], $[[ARG0]], $[[MSK0]] -; CHECK-EL: and $[[T3:[0-9]+]], $[[ARG1]], $[[MSK1]] -; CHECK-EL: or $[[T4:[0-9]+]], $[[T2]], $[[T3]] -; CHECK-EL: mtc1 $[[T4]], $f0 + +; 32: lui $[[MSK1:[0-9]+]], 32768 +; 32: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]] +; 32: lui $[[T0:[0-9]+]], 32767 +; 32: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 +; 32: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]] +; 32: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]] +; 32: mtc1 $[[OR]], $f0 + +; 32R2: ext $[[EXT:[0-9]+]], ${{[0-9]+}}, 31, 1 +; 32R2: ins $[[INS:[0-9]+]], $[[EXT]], 31, 1 +; 32R2: mtc1 $[[INS]], $f0 + %call = tail call float @copysignf(float %f0, float %f1) nounwind readnone ret float %call } declare float @copysignf(float, float) nounwind readnone + diff --git a/test/CodeGen/Mips/fmadd1.ll b/test/CodeGen/Mips/fmadd1.ll new file mode 100644 index 000000000000..435b419368b3 --- /dev/null +++ b/test/CodeGen/Mips/fmadd1.ll @@ -0,0 +1,88 @@ +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math | FileCheck %s -check-prefix=32R2 +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefix=64R2 +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2NAN +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 | FileCheck %s -check-prefix=64R2NAN + +define float @FOO0float(float %a, float %b, float %c) nounwind readnone { +entry: +; CHECK: madd.s + %mul = fmul float %a, %b + %add = fadd float %mul, %c + %add1 = fadd float %add, 0.000000e+00 + ret float %add1 +} + +define float @FOO1float(float %a, float %b, float %c) nounwind readnone { +entry: +; CHECK: msub.s + %mul = fmul float %a, %b + %sub = fsub float %mul, %c + %add = fadd float %sub, 0.000000e+00 + ret float %add +} + +define float @FOO2float(float %a, float %b, float %c) nounwind readnone { +entry: +; 32R2: nmadd.s +; 64R2: nmadd.s +; 32R2NAN: madd.s +; 64R2NAN: madd.s + %mul = fmul float %a, %b + %add = fadd float %mul, %c + %sub = fsub float 0.000000e+00, %add + ret float %sub +} + +define float @FOO3float(float %a, float %b, float %c) nounwind readnone { +entry: +; 32R2: nmsub.s +; 64R2: nmsub.s +; 32R2NAN: msub.s +; 64R2NAN: msub.s + %mul = fmul float %a, %b + %sub = fsub float %mul, %c + %sub1 = fsub float 0.000000e+00, %sub + ret float %sub1 +} + +define double @FOO10double(double %a, double %b, double %c) nounwind readnone { +entry: +; CHECK: madd.d + %mul = fmul double %a, %b + %add = fadd double %mul, %c + %add1 = fadd double %add, 0.000000e+00 + ret double %add1 +} + +define double @FOO11double(double %a, double %b, double %c) nounwind readnone { +entry: +; CHECK: msub.d + %mul = fmul double %a, %b + %sub = fsub double %mul, %c + %add = fadd double %sub, 0.000000e+00 + ret double %add +} + +define double @FOO12double(double %a, double %b, double %c) nounwind readnone { +entry: +; 32R2: nmadd.d +; 64R2: nmadd.d +; 32R2NAN: madd.d +; 64R2NAN: madd.d + %mul = fmul double %a, %b + %add = fadd double %mul, %c + %sub = fsub double 0.000000e+00, %add + ret double %sub +} + +define double @FOO13double(double %a, double %b, double %c) nounwind readnone { +entry: +; 32R2: nmsub.d +; 64R2: nmsub.d +; 32R2NAN: msub.d +; 64R2NAN: msub.d + %mul = fmul double %a, %b + %sub = fsub double %mul, %c + %sub1 = fsub double 0.000000e+00, %sub + ret double %sub1 +} diff --git a/test/CodeGen/Mips/fneg.ll b/test/CodeGen/Mips/fneg.ll new file mode 100644 index 000000000000..b322abdaa23c --- /dev/null +++ b/test/CodeGen/Mips/fneg.ll @@ -0,0 +1,17 @@ +; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s + +define float @foo0(i32 %a, float %d) nounwind readnone { +entry: +; CHECK-NOT: neg.s + %sub = fsub float -0.000000e+00, %d + ret float %sub +} + +define double @foo1(i32 %a, double %d) nounwind readnone { +entry: +; CHECK: foo1 +; CHECK-NOT: neg.d +; CHECK: jr + %sub = fsub double -0.000000e+00, %d + ret double %sub +} diff --git a/test/CodeGen/Mips/fp-indexed-ls.ll b/test/CodeGen/Mips/fp-indexed-ls.ll new file mode 100644 index 000000000000..08bd6e72ae77 --- /dev/null +++ b/test/CodeGen/Mips/fp-indexed-ls.ll @@ -0,0 +1,98 @@ +; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s + +%struct.S = type <{ [4 x float] }> +%struct.S2 = type <{ [4 x double] }> +%struct.S3 = type <{ i8, float }> + +@s = external global [4 x %struct.S] +@gf = external global float +@gd = external global double +@s2 = external global [4 x %struct.S2] +@s3 = external global %struct.S3 + +define float @foo0(float* nocapture %b, i32 %o) nounwind readonly { +entry: +; CHECK: lwxc1 + %arrayidx = getelementptr inbounds float* %b, i32 %o + %0 = load float* %arrayidx, align 4 + ret float %0 +} + +define double @foo1(double* nocapture %b, i32 %o) nounwind readonly { +entry: +; CHECK: ldxc1 + %arrayidx = getelementptr inbounds double* %b, i32 %o + %0 = load double* %arrayidx, align 8 + ret double %0 +} + +define float @foo2(i32 %b, i32 %c) nounwind readonly { +entry: +; CHECK: luxc1 + %arrayidx1 = getelementptr inbounds [4 x %struct.S]* @s, i32 0, i32 %b, i32 0, i32 %c + %0 = load float* %arrayidx1, align 1 + ret float %0 +} + +define void @foo3(float* nocapture %b, i32 %o) nounwind { +entry: +; CHECK: swxc1 + %0 = load float* @gf, align 4 + %arrayidx = getelementptr inbounds float* %b, i32 %o + store float %0, float* %arrayidx, align 4 + ret void +} + +define void @foo4(double* nocapture %b, i32 %o) nounwind { +entry: +; CHECK: sdxc1 + %0 = load double* @gd, align 8 + %arrayidx = getelementptr inbounds double* %b, i32 %o + store double %0, double* %arrayidx, align 8 + ret void +} + +define void @foo5(i32 %b, i32 %c) nounwind { +entry: +; CHECK: suxc1 + %0 = load float* @gf, align 4 + %arrayidx1 = getelementptr inbounds [4 x %struct.S]* @s, i32 0, i32 %b, i32 0, i32 %c + store float %0, float* %arrayidx1, align 1 + ret void +} + +define double @foo6(i32 %b, i32 %c) nounwind readonly { +entry: +; CHECK: foo6 +; CHECK-NOT: ldxc1 + %arrayidx1 = getelementptr inbounds [4 x %struct.S2]* @s2, i32 0, i32 %b, i32 0, i32 %c + %0 = load double* %arrayidx1, align 1 + ret double %0 +} + +define void @foo7(i32 %b, i32 %c) nounwind { +entry: +; CHECK: foo7 +; CHECK-NOT: sdxc1 + %0 = load double* @gd, align 8 + %arrayidx1 = getelementptr inbounds [4 x %struct.S2]* @s2, i32 0, i32 %b, i32 0, i32 %c + store double %0, double* %arrayidx1, align 1 + ret void +} + +define float @foo8() nounwind readonly { +entry: +; CHECK: foo8 +; CHECK: luxc1 + %0 = load float* getelementptr inbounds (%struct.S3* @s3, i32 0, i32 1), align 1 + ret float %0 +} + +define void @foo9(float %f) nounwind { +entry: +; CHECK: foo9 +; CHECK: suxc1 + store float %f, float* getelementptr inbounds (%struct.S3* @s3, i32 0, i32 1), align 1 + ret void +} + diff --git a/test/CodeGen/Mips/fpcmp.ll b/test/CodeGen/Mips/fpcmp.ll deleted file mode 100644 index 86545e347c14..000000000000 --- a/test/CodeGen/Mips/fpcmp.ll +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: llc < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-MIPS32 - -@g1 = external global i32 - -define i32 @f(float %f0, float %f1) nounwind { -entry: -; CHECK-MIPS32: c.olt.s -; CHECK-MIPS32: movt -; CHECK-MIPS32: c.olt.s -; CHECK-MIPS32: movt - %cmp = fcmp olt float %f0, %f1 - %conv = zext i1 %cmp to i32 - %tmp2 = load i32* @g1, align 4 - %add = add nsw i32 %tmp2, %conv - store i32 %add, i32* @g1, align 4 - %cond = select i1 %cmp, i32 10, i32 20 - ret i32 %cond -} diff --git a/test/CodeGen/Mips/frem.ll b/test/CodeGen/Mips/frem.ll new file mode 100644 index 000000000000..be222b2d9172 --- /dev/null +++ b/test/CodeGen/Mips/frem.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=mipsel + +define float @fmods(float %x, float %y) { +entry: + %r = frem float %x, %y + ret float %r +} + +define double @fmodd(double %x, double %y) { +entry: + %r = frem double %x, %y + ret double %r +} diff --git a/test/CodeGen/Mips/global-address.ll b/test/CodeGen/Mips/global-address.ll new file mode 100644 index 000000000000..0d49a7424ad6 --- /dev/null +++ b/test/CodeGen/Mips/global-address.ll @@ -0,0 +1,46 @@ +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-O32 +; RUN: llc -march=mipsel -relocation-model=static -mtriple=mipsel-linux-gnu < %s | FileCheck %s -check-prefix=STATIC-O32 +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n32 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N32 +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n32 -relocation-model=static -mtriple=mipsel-linux-gnu < %s | FileCheck %s -check-prefix=STATIC-N32 +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N64 +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-N64 + +@s1 = internal unnamed_addr global i32 8, align 4 +@g1 = external global i32 + +define void @foo() nounwind { +entry: +; PIC-O32: lw $[[R0:[0-9]+]], %got(s1) +; PIC-O32: lw ${{[0-9]+}}, %lo(s1)($[[R0]]) +; PIC-O32: lw ${{[0-9]+}}, %got(g1) +; STATIC-O32: lui $[[R1:[0-9]+]], %hi(s1) +; STATIC-O32: lw ${{[0-9]+}}, %lo(s1)($[[R1]]) +; STATIC-O32: lui $[[R2:[0-9]+]], %hi(g1) +; STATIC-O32: lw ${{[0-9]+}}, %lo(g1)($[[R2]]) + +; PIC-N32: lw $[[R0:[0-9]+]], %got_page(s1) +; PIC-N32: lw ${{[0-9]+}}, %got_ofst(s1)($[[R0]]) +; PIC-N32: lw ${{[0-9]+}}, %got_disp(g1) +; STATIC-N32: lui $[[R1:[0-9]+]], %hi(s1) +; STATIC-N32: lw ${{[0-9]+}}, %lo(s1)($[[R1]]) +; STATIC-N32: lui $[[R2:[0-9]+]], %hi(g1) +; STATIC-N32: lw ${{[0-9]+}}, %lo(g1)($[[R2]]) + +; PIC-N64: ld $[[R0:[0-9]+]], %got_page(s1) +; PIC-N64: lw ${{[0-9]+}}, %got_ofst(s1)($[[R0]]) +; PIC-N64: ld ${{[0-9]+}}, %got_disp(g1) +; STATIC-N64: ld $[[R1:[0-9]+]], %got_page(s1) +; STATIC-N64: lw ${{[0-9]+}}, %got_ofst(s1)($[[R1]]) +; STATIC-N64: ld ${{[0-9]+}}, %got_disp(g1) + + %0 = load i32* @s1, align 4 + tail call void @foo1(i32 %0) nounwind + %1 = load i32* @g1, align 4 + store i32 %1, i32* @s1, align 4 + %add = add nsw i32 %1, 2 + store i32 %add, i32* @g1, align 4 + ret void +} + +declare void @foo1(i32) + diff --git a/test/CodeGen/Mips/global-pointer-reg.ll b/test/CodeGen/Mips/global-pointer-reg.ll new file mode 100644 index 000000000000..174d1f9cbe90 --- /dev/null +++ b/test/CodeGen/Mips/global-pointer-reg.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s -march=mipsel -mips-fix-global-base-reg=false | FileCheck %s + +@g0 = external global i32 +@g1 = external global i32 +@g2 = external global i32 + +define void @foo1() nounwind { +entry: +; CHECK-NOT: .cpload +; CHECK-NOT: .cprestore +; CHECK: lui $[[R0:[0-9]+]], %hi(_gp_disp) +; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp) +; CHECK: addu $[[GP:[0-9]+]], $[[R1]], $25 +; CHECK: lw ${{[0-9]+}}, %call16(foo2)($[[GP]]) + + tail call void @foo2(i32* @g0) nounwind + tail call void @foo2(i32* @g1) nounwind + tail call void @foo2(i32* @g2) nounwind + ret void +} + +declare void @foo2(i32*) diff --git a/test/CodeGen/Mips/i64arg.ll b/test/CodeGen/Mips/i64arg.ll index 87cf2a63c5b5..8b1f71b69f19 100644 --- a/test/CodeGen/Mips/i64arg.ll +++ b/test/CodeGen/Mips/i64arg.ll @@ -4,21 +4,21 @@ define void @f1(i64 %ll1, float %f, i64 %ll, i32 %i, float %f2) nounwind { entry: ; CHECK: addu $[[R1:[0-9]+]], $zero, $5 ; CHECK: addu $[[R0:[0-9]+]], $zero, $4 -; CHECK: lw $25, %call16(ff1) ; CHECK: ori $6, ${{[0-9]+}}, 3855 ; CHECK: ori $7, ${{[0-9]+}}, 22136 +; CHECK: lw $25, %call16(ff1) ; CHECK: jalr tail call void @ff1(i32 %i, i64 1085102592623924856) nounwind ; CHECK: lw $25, %call16(ff2) -; CHECK: lw $[[R2:[0-9]+]], 88($sp) -; CHECK: lw $[[R3:[0-9]+]], 92($sp) +; CHECK: lw $[[R2:[0-9]+]], 80($sp) +; CHECK: lw $[[R3:[0-9]+]], 84($sp) ; CHECK: addu $4, $zero, $[[R2]] ; CHECK: addu $5, $zero, $[[R3]] ; CHECK: jalr $25 tail call void @ff2(i64 %ll, double 3.000000e+00) nounwind %sub = add nsw i32 %i, -1 -; CHECK: sw $[[R0]], 24($sp) ; CHECK: sw $[[R1]], 28($sp) +; CHECK: sw $[[R0]], 24($sp) ; CHECK: lw $25, %call16(ff3) ; CHECK: addu $6, $zero, $[[R2]] ; CHECK: addu $7, $zero, $[[R3]] diff --git a/test/CodeGen/Mips/imm.ll b/test/CodeGen/Mips/imm.ll new file mode 100644 index 000000000000..eea391e8707e --- /dev/null +++ b/test/CodeGen/Mips/imm.ll @@ -0,0 +1,38 @@ +; RUN: llc -march=mipsel < %s | FileCheck %s + +define i32 @foo0() nounwind readnone { +entry: +; CHECK: foo0 +; CHECK: lui $[[R0:[0-9]+]], 4660 +; CHECK: ori ${{[0-9]+}}, $[[R0]], 22136 + ret i32 305419896 +} + +define i32 @foo1() nounwind readnone { +entry: +; CHECK: foo1 +; CHECK: lui ${{[0-9]+}}, 4660 +; CHECK-NOT: ori + ret i32 305397760 +} + +define i32 @foo2() nounwind readnone { +entry: +; CHECK: foo2 +; CHECK: addiu ${{[0-9]+}}, $zero, 4660 + ret i32 4660 +} + +define i32 @foo17() nounwind readnone { +entry: +; CHECK: foo17 +; CHECK: addiu ${{[0-9]+}}, $zero, -32204 + ret i32 -32204 +} + +define i32 @foo18() nounwind readnone { +entry: +; CHECK: foo18 +; CHECK: ori ${{[0-9]+}}, $zero, 33332 + ret i32 33332 +} diff --git a/test/CodeGen/Mips/indirectcall.ll b/test/CodeGen/Mips/indirectcall.ll new file mode 100644 index 000000000000..ac565d646674 --- /dev/null +++ b/test/CodeGen/Mips/indirectcall.ll @@ -0,0 +1,8 @@ +; RUN: llc < %s -march=mipsel -relocation-model=static | FileCheck %s + +define void @foo0(void (i32)* nocapture %f1) nounwind { +entry: +; CHECK: jalr $25 + tail call void %f1(i32 13) nounwind + ret void +} diff --git a/test/CodeGen/Mips/inlineasm64.ll b/test/CodeGen/Mips/inlineasm64.ll new file mode 100644 index 000000000000..dbce3c394e96 --- /dev/null +++ b/test/CodeGen/Mips/inlineasm64.ll @@ -0,0 +1,17 @@ +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s + +@gl2 = external global i64 +@gl1 = external global i64 +@gl0 = external global i64 + +define void @foo1() nounwind { +entry: +; CHECK: foo1 +; CHECK: daddu + %0 = load i64* @gl1, align 8 + %1 = load i64* @gl0, align 8 + %2 = tail call i64 asm "daddu $0, $1, $2", "=r,r,r"(i64 %0, i64 %1) nounwind + store i64 %2, i64* @gl2, align 8 + ret void +} + diff --git a/test/CodeGen/Mips/inlineasmmemop.ll b/test/CodeGen/Mips/inlineasmmemop.ll index b5db58a57e38..4b31a88b418a 100644 --- a/test/CodeGen/Mips/inlineasmmemop.ll +++ b/test/CodeGen/Mips/inlineasmmemop.ll @@ -8,10 +8,10 @@ entry: ; CHECK: #APP ; CHECK: sw $4, 0($[[T0]]) ; CHECK: #NO_APP -; CHECK: lw $[[T1:[0-9]+]], %got(g1)($gp) ; CHECK: #APP ; CHECK: lw $[[T3:[0-9]+]], 0($[[T0]]) ; CHECK: #NO_APP +; CHECK: lw $[[T1:[0-9]+]], %got(g1)($gp) ; CHECK: sw $[[T3]], 0($[[T1]]) %l1 = alloca i32, align 4 diff --git a/test/CodeGen/Mips/largeimmprinting.ll b/test/CodeGen/Mips/largeimmprinting.ll index 579a319d5f7a..b7c9a9ccbb58 100644 --- a/test/CodeGen/Mips/largeimmprinting.ll +++ b/test/CodeGen/Mips/largeimmprinting.ll @@ -1,8 +1,4 @@ -; DISABLED: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s -; RUN: false - -; byval is currently unsupported. -; XFAIL: * +; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s %struct.S1 = type { [65536 x i8] } @@ -11,8 +7,8 @@ define void @f() nounwind { entry: ; CHECK: lui $at, 65534 -; CHECK: addu $at, $sp, $at -; CHECK: addiu $sp, $at, -24 +; CHECK: addiu $at, $at, -24 +; CHECK: addu $sp, $sp, $at ; CHECK: .cprestore 65536 %agg.tmp = alloca %struct.S1, align 1 diff --git a/test/CodeGen/Mips/lit.local.cfg b/test/CodeGen/Mips/lit.local.cfg new file mode 100644 index 000000000000..0587d3243e6b --- /dev/null +++ b/test/CodeGen/Mips/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.ll', '.c', '.cpp'] + +targets = set(config.root.targets_to_build.split()) +if not 'Mips' in targets: + config.unsupported = True + diff --git a/test/CodeGen/Mips/mips64-fp-indexed-ls.ll b/test/CodeGen/Mips/mips64-fp-indexed-ls.ll new file mode 100644 index 000000000000..09745fb8f61c --- /dev/null +++ b/test/CodeGen/Mips/mips64-fp-indexed-ls.ll @@ -0,0 +1,110 @@ +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s + +%struct.S = type <{ [4 x float] }> +%struct.S2 = type <{ [4 x double] }> +%struct.S3 = type <{ i8, float }> + +@s = external global [4 x %struct.S] +@gf = external global float +@gd = external global double +@s2 = external global [4 x %struct.S2] +@s3 = external global %struct.S3 + +define float @foo0(float* nocapture %b, i32 %o) nounwind readonly { +entry: +; CHECK: lwxc1 + %idxprom = zext i32 %o to i64 + %arrayidx = getelementptr inbounds float* %b, i64 %idxprom + %0 = load float* %arrayidx, align 4 + ret float %0 +} + +define double @foo1(double* nocapture %b, i32 %o) nounwind readonly { +entry: +; CHECK: ldxc1 + %idxprom = zext i32 %o to i64 + %arrayidx = getelementptr inbounds double* %b, i64 %idxprom + %0 = load double* %arrayidx, align 8 + ret double %0 +} + +define float @foo2(i32 %b, i32 %c) nounwind readonly { +entry: +; CHECK: luxc1 + %idxprom = zext i32 %c to i64 + %idxprom1 = zext i32 %b to i64 + %arrayidx2 = getelementptr inbounds [4 x %struct.S]* @s, i64 0, i64 %idxprom1, i32 0, i64 %idxprom + %0 = load float* %arrayidx2, align 1 + ret float %0 +} + +define void @foo3(float* nocapture %b, i32 %o) nounwind { +entry: +; CHECK: swxc1 + %0 = load float* @gf, align 4 + %idxprom = zext i32 %o to i64 + %arrayidx = getelementptr inbounds float* %b, i64 %idxprom + store float %0, float* %arrayidx, align 4 + ret void +} + +define void @foo4(double* nocapture %b, i32 %o) nounwind { +entry: +; CHECK: sdxc1 + %0 = load double* @gd, align 8 + %idxprom = zext i32 %o to i64 + %arrayidx = getelementptr inbounds double* %b, i64 %idxprom + store double %0, double* %arrayidx, align 8 + ret void +} + +define void @foo5(i32 %b, i32 %c) nounwind { +entry: +; CHECK: suxc1 + %0 = load float* @gf, align 4 + %idxprom = zext i32 %c to i64 + %idxprom1 = zext i32 %b to i64 + %arrayidx2 = getelementptr inbounds [4 x %struct.S]* @s, i64 0, i64 %idxprom1, i32 0, i64 %idxprom + store float %0, float* %arrayidx2, align 1 + ret void +} + +define double @foo6(i32 %b, i32 %c) nounwind readonly { +entry: +; CHECK: foo6 +; CHECK-NOT: ldxc1 + %idxprom = zext i32 %c to i64 + %idxprom1 = zext i32 %b to i64 + %arrayidx2 = getelementptr inbounds [4 x %struct.S2]* @s2, i64 0, i64 %idxprom1, i32 0, i64 %idxprom + %0 = load double* %arrayidx2, align 1 + ret double %0 +} + +define void @foo7(i32 %b, i32 %c) nounwind { +entry: +; CHECK: foo7 +; CHECK-NOT: sdxc1 + %0 = load double* @gd, align 8 + %idxprom = zext i32 %c to i64 + %idxprom1 = zext i32 %b to i64 + %arrayidx2 = getelementptr inbounds [4 x %struct.S2]* @s2, i64 0, i64 %idxprom1, i32 0, i64 %idxprom + store double %0, double* %arrayidx2, align 1 + ret void +} + +define float @foo8() nounwind readonly { +entry: +; CHECK: foo8 +; CHECK: luxc1 + %0 = load float* getelementptr inbounds (%struct.S3* @s3, i64 0, i32 1), align 1 + ret float %0 +} + +define void @foo9(float %f) nounwind { +entry: +; CHECK: foo9 +; CHECK: suxc1 + store float %f, float* getelementptr inbounds (%struct.S3* @s3, i64 0, i32 1), align 1 + ret void +} + diff --git a/test/CodeGen/Mips/mips64countleading.ll b/test/CodeGen/Mips/mips64countleading.ll new file mode 100644 index 000000000000..b2b67e51ade0 --- /dev/null +++ b/test/CodeGen/Mips/mips64countleading.ll @@ -0,0 +1,19 @@ +; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s + +define i64 @t1(i64 %X) nounwind readnone { +entry: +; CHECK: dclz + %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true) + ret i64 %tmp1 +} + +declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone + +define i64 @t3(i64 %X) nounwind readnone { +entry: +; CHECK: dclo + %neg = xor i64 %X, -1 + %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true) + ret i64 %tmp1 +} + diff --git a/test/CodeGen/Mips/mips64directive.ll b/test/CodeGen/Mips/mips64directive.ll new file mode 100644 index 000000000000..fa81b729e9c8 --- /dev/null +++ b/test/CodeGen/Mips/mips64directive.ll @@ -0,0 +1,11 @@ +; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s + +@gl = global i64 1250999896321, align 8 + +; CHECK: 8byte +define i64 @foo1() nounwind readonly { +entry: + %0 = load i64* @gl, align 8 + ret i64 %0 +} + diff --git a/test/CodeGen/Mips/mips64ext.ll b/test/CodeGen/Mips/mips64ext.ll new file mode 100644 index 000000000000..02a35f8e6ed7 --- /dev/null +++ b/test/CodeGen/Mips/mips64ext.ll @@ -0,0 +1,26 @@ +; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s + +define i64 @zext64_32(i32 %a) nounwind readnone { +entry: +; CHECK: addiu $[[R0:[0-9]+]], ${{[0-9]+}}, 2 +; CHECK: dsll $[[R1:[0-9]+]], $[[R0]], 32 +; CHECK: dsrl ${{[0-9]+}}, $[[R1]], 32 + %add = add i32 %a, 2 + %conv = zext i32 %add to i64 + ret i64 %conv +} + +define i64 @sext64_32(i32 %a) nounwind readnone { +entry: +; CHECK: sll ${{[0-9]+}}, ${{[0-9]+}}, 0 + %conv = sext i32 %a to i64 + ret i64 %conv +} + +define i64 @i64_float(float %f) nounwind readnone { +entry: +; CHECK: trunc.l.s + %conv = fptosi float %f to i64 + ret i64 %conv +} + diff --git a/test/CodeGen/Mips/mips64extins.ll b/test/CodeGen/Mips/mips64extins.ll new file mode 100644 index 000000000000..14f92ca86947 --- /dev/null +++ b/test/CodeGen/Mips/mips64extins.ll @@ -0,0 +1,55 @@ +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 | FileCheck %s + +define i64 @dext(i64 %i) nounwind readnone { +entry: +; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10 + %shr = lshr i64 %i, 5 + %and = and i64 %shr, 1023 + ret i64 %and +} + +define i64 @dextm(i64 %i) nounwind readnone { +entry: +; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 34 + %shr = lshr i64 %i, 5 + %and = and i64 %shr, 17179869183 + ret i64 %and +} + +define i64 @dextu(i64 %i) nounwind readnone { +entry: +; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 34, 6 + %shr = lshr i64 %i, 34 + %and = and i64 %shr, 63 + ret i64 %and +} + +define i64 @dins(i64 %i, i64 %j) nounwind readnone { +entry: +; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 8, 10 + %shl2 = shl i64 %j, 8 + %and = and i64 %shl2, 261888 + %and3 = and i64 %i, -261889 + %or = or i64 %and3, %and + ret i64 %or +} + +define i64 @dinsm(i64 %i, i64 %j) nounwind readnone { +entry: +; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 10, 33 + %shl4 = shl i64 %j, 10 + %and = and i64 %shl4, 8796093021184 + %and5 = and i64 %i, -8796093021185 + %or = or i64 %and5, %and + ret i64 %or +} + +define i64 @dinsu(i64 %i, i64 %j) nounwind readnone { +entry: +; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 40, 13 + %shl4 = shl i64 %j, 40 + %and = and i64 %shl4, 9006099743113216 + %and5 = and i64 %i, -9006099743113217 + %or = or i64 %and5, %and + ret i64 %or +} diff --git a/test/CodeGen/Mips/mips64fpimm0.ll b/test/CodeGen/Mips/mips64fpimm0.ll new file mode 100644 index 000000000000..17716da0c670 --- /dev/null +++ b/test/CodeGen/Mips/mips64fpimm0.ll @@ -0,0 +1,7 @@ +; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s + +define double @foo1() nounwind readnone { +entry: +; CHECK: dmtc1 $zero + ret double 0.000000e+00 +} diff --git a/test/CodeGen/Mips/mips64fpldst.ll b/test/CodeGen/Mips/mips64fpldst.ll index b8f3ca9d7985..24647b20bf2e 100644 --- a/test/CodeGen/Mips/mips64fpldst.ll +++ b/test/CodeGen/Mips/mips64fpldst.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=mips64el -mcpu=mips64r1 -mattr=n64 | FileCheck %s -check-prefix=CHECK-N64 -; RUN: llc < %s -march=mips64el -mcpu=mips64r1 -mattr=n32 | FileCheck %s -check-prefix=CHECK-N32 +; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=CHECK-N64 +; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n32 | FileCheck %s -check-prefix=CHECK-N32 @f0 = common global float 0.000000e+00, align 4 @d0 = common global double 0.000000e+00, align 8 @@ -12,7 +12,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(f0) ; CHECK-N64: lwc1 $f{{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: funcfl1 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(f0) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(f0) ; CHECK-N32: lwc1 $f{{[0-9]+}}, 0($[[R0]]) %0 = load float* @f0, align 4 ret float %0 @@ -24,7 +24,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(d0) ; CHECK-N64: ldc1 $f{{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: funcfl2 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(d0) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(d0) ; CHECK-N32: ldc1 $f{{[0-9]+}}, 0($[[R0]]) %0 = load double* @d0, align 8 ret double %0 @@ -36,7 +36,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(f0) ; CHECK-N64: swc1 $f{{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: funcfs1 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(f0) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(f0) ; CHECK-N32: swc1 $f{{[0-9]+}}, 0($[[R0]]) %0 = load float* @f1, align 4 store float %0, float* @f0, align 4 @@ -49,7 +49,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(d0) ; CHECK-N64: sdc1 $f{{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: funcfs2 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(d0) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(d0) ; CHECK-N32: sdc1 $f{{[0-9]+}}, 0($[[R0]]) %0 = load double* @d1, align 8 store double %0, double* @d0, align 8 diff --git a/test/CodeGen/Mips/mips64imm.ll b/test/CodeGen/Mips/mips64imm.ll new file mode 100644 index 000000000000..1fc8636c480b --- /dev/null +++ b/test/CodeGen/Mips/mips64imm.ll @@ -0,0 +1,52 @@ +; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s + +define i32 @foo1() nounwind readnone { +entry: +; CHECK: foo1 +; CHECK: lui ${{[0-9]+}}, 4660 +; CHECK-NOT: ori + ret i32 305397760 +} + +define i64 @foo3() nounwind readnone { +entry: +; CHECK: foo3 +; CHECK: lui $[[R0:[0-9]+]], 4660 +; CHECK: daddiu ${{[0-9]+}}, $[[R0]], 22136 + ret i64 305419896 +} + +define i64 @foo6() nounwind readnone { +entry: +; CHECK: foo6 +; CHECK: ori ${{[0-9]+}}, $zero, 33332 + ret i64 33332 +} + +define i64 @foo7() nounwind readnone { +entry: +; CHECK: foo7 +; CHECK: daddiu ${{[0-9]+}}, $zero, -32204 + ret i64 -32204 +} + +define i64 @foo9() nounwind readnone { +entry: +; CHECK: foo9 +; CHECK: lui $[[R0:[0-9]+]], 583 +; CHECK: daddiu $[[R1:[0-9]+]], $[[R0]], -30001 +; CHECK: dsll $[[R2:[0-9]+]], $[[R1]], 18 +; CHECK: daddiu $[[R3:[0-9]+]], $[[R2]], 18441 +; CHECK: dsll $[[R4:[0-9]+]], $[[R3]], 17 +; CHECK: daddiu ${{[0-9]+}}, $[[R4]], 13398 + ret i64 1311768467284833366 +} + +define i64 @foo10() nounwind readnone { +entry: +; CHECK: foo10 +; CHECK: lui $[[R0:[0-9]+]], 34661 +; CHECK: daddiu ${{[0-9]+}}, $[[R0]], 17185 + ret i64 -8690466096928522240 +} + diff --git a/test/CodeGen/Mips/mips64instrs.ll b/test/CodeGen/Mips/mips64instrs.ll index c9812a276992..041831149057 100644 --- a/test/CodeGen/Mips/mips64instrs.ll +++ b/test/CodeGen/Mips/mips64instrs.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips64el -mcpu=mips64r1 < %s | FileCheck %s +; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s define i64 @f0(i64 %a0, i64 %a1) nounwind readnone { entry: @@ -116,12 +116,12 @@ entry: ret i64 %rem } -declare i64 @llvm.ctlz.i64(i64) nounwind readnone +declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone define i64 @f18(i64 %X) nounwind readnone { entry: ; CHECK: dclz $2, $4 - %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X) + %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true) ret i64 %tmp1 } @@ -129,7 +129,7 @@ define i64 @f19(i64 %X) nounwind readnone { entry: ; CHECK: dclo $2, $4 %neg = xor i64 %X, -1 - %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg) + %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true) ret i64 %tmp1 } diff --git a/test/CodeGen/Mips/mips64intldst.ll b/test/CodeGen/Mips/mips64intldst.ll index fdf496b19189..0e310a8670f9 100644 --- a/test/CodeGen/Mips/mips64intldst.ll +++ b/test/CodeGen/Mips/mips64intldst.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=mips64el -mcpu=mips64r1 -mattr=n64 | FileCheck %s -check-prefix=CHECK-N64 -; RUN: llc < %s -march=mips64el -mcpu=mips64r1 -mattr=n32 | FileCheck %s -check-prefix=CHECK-N32 +; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=CHECK-N64 +; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n32 | FileCheck %s -check-prefix=CHECK-N32 @c = common global i8 0, align 4 @s = common global i16 0, align 4 @@ -16,7 +16,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(c) ; CHECK-N64: lb ${{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: func1 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(c) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(c) ; CHECK-N32: lb ${{[0-9]+}}, 0($[[R0]]) %0 = load i8* @c, align 4 %conv = sext i8 %0 to i64 @@ -29,7 +29,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(s) ; CHECK-N64: lh ${{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: func2 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(s) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(s) ; CHECK-N32: lh ${{[0-9]+}}, 0($[[R0]]) %0 = load i16* @s, align 4 %conv = sext i16 %0 to i64 @@ -42,7 +42,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(i) ; CHECK-N64: lw ${{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: func3 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(i) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(i) ; CHECK-N32: lw ${{[0-9]+}}, 0($[[R0]]) %0 = load i32* @i, align 4 %conv = sext i32 %0 to i64 @@ -55,7 +55,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(l) ; CHECK-N64: ld ${{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: func4 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(l) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(l) ; CHECK-N32: ld ${{[0-9]+}}, 0($[[R0]]) %0 = load i64* @l, align 8 ret i64 %0 @@ -67,7 +67,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(uc) ; CHECK-N64: lbu ${{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: ufunc1 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(uc) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(uc) ; CHECK-N32: lbu ${{[0-9]+}}, 0($[[R0]]) %0 = load i8* @uc, align 4 %conv = zext i8 %0 to i64 @@ -80,7 +80,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(us) ; CHECK-N64: lhu ${{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: ufunc2 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(us) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(us) ; CHECK-N32: lhu ${{[0-9]+}}, 0($[[R0]]) %0 = load i16* @us, align 4 %conv = zext i16 %0 to i64 @@ -93,7 +93,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(ui) ; CHECK-N64: lwu ${{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: ufunc3 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(ui) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(ui) ; CHECK-N32: lwu ${{[0-9]+}}, 0($[[R0]]) %0 = load i32* @ui, align 4 %conv = zext i32 %0 to i64 @@ -106,7 +106,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(c) ; CHECK-N64: sb ${{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: sfunc1 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(c) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(c) ; CHECK-N32: sb ${{[0-9]+}}, 0($[[R0]]) %0 = load i64* @l1, align 8 %conv = trunc i64 %0 to i8 @@ -120,7 +120,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(s) ; CHECK-N64: sh ${{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: sfunc2 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(s) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(s) ; CHECK-N32: sh ${{[0-9]+}}, 0($[[R0]]) %0 = load i64* @l1, align 8 %conv = trunc i64 %0 to i16 @@ -134,7 +134,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(i) ; CHECK-N64: sw ${{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: sfunc3 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(i) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(i) ; CHECK-N32: sw ${{[0-9]+}}, 0($[[R0]]) %0 = load i64* @l1, align 8 %conv = trunc i64 %0 to i32 @@ -148,7 +148,7 @@ entry: ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(l) ; CHECK-N64: sd ${{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: sfunc4 -; CHECK-N32: lw $[[R0:[0-9]+]], %got(l) +; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(l) ; CHECK-N32: sd ${{[0-9]+}}, 0($[[R0]]) %0 = load i64* @l1, align 8 store i64 %0, i64* @l, align 8 diff --git a/test/CodeGen/Mips/mips64lea.ll b/test/CodeGen/Mips/mips64lea.ll new file mode 100644 index 000000000000..54d504f92266 --- /dev/null +++ b/test/CodeGen/Mips/mips64lea.ll @@ -0,0 +1,12 @@ +; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s + +define void @foo3() nounwind { +entry: +; CHECK: daddiu ${{[0-9]+}}, $sp + %a = alloca i32, align 4 + call void @foo1(i32* %a) nounwind + ret void +} + +declare void @foo1(i32*) + diff --git a/test/CodeGen/Mips/mips64muldiv.ll b/test/CodeGen/Mips/mips64muldiv.ll new file mode 100644 index 000000000000..fd036a2ca9fb --- /dev/null +++ b/test/CodeGen/Mips/mips64muldiv.ll @@ -0,0 +1,49 @@ +; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s + +define i64 @m0(i64 %a0, i64 %a1) nounwind readnone { +entry: +; CHECK: dmult +; CHECK: mflo + %mul = mul i64 %a1, %a0 + ret i64 %mul +} + +define i64 @m1(i64 %a) nounwind readnone { +entry: +; CHECK: dmult +; CHECK: mfhi + %div = sdiv i64 %a, 3 + ret i64 %div +} + +define i64 @d0(i64 %a0, i64 %a1) nounwind readnone { +entry: +; CHECK: ddivu +; CHECK: mflo + %div = udiv i64 %a0, %a1 + ret i64 %div +} + +define i64 @d1(i64 %a0, i64 %a1) nounwind readnone { +entry: +; CHECK: ddiv +; CHECK: mflo + %div = sdiv i64 %a0, %a1 + ret i64 %div +} + +define i64 @d2(i64 %a0, i64 %a1) nounwind readnone { +entry: +; CHECK: ddivu +; CHECK: mfhi + %rem = urem i64 %a0, %a1 + ret i64 %rem +} + +define i64 @d3(i64 %a0, i64 %a1) nounwind readnone { +entry: +; CHECK: ddiv +; CHECK: mfhi + %rem = srem i64 %a0, %a1 + ret i64 %rem +} diff --git a/test/CodeGen/Mips/mips64shift.ll b/test/CodeGen/Mips/mips64shift.ll index cc5e50856147..45d1c9532276 100644 --- a/test/CodeGen/Mips/mips64shift.ll +++ b/test/CodeGen/Mips/mips64shift.ll @@ -44,21 +44,21 @@ entry: define i64 @f6(i64 %a0) nounwind readnone { entry: -; CHECK: dsll32 ${{[0-9]+}}, ${{[0-9]+}}, 8 +; CHECK: dsll ${{[0-9]+}}, ${{[0-9]+}}, 40 %shl = shl i64 %a0, 40 ret i64 %shl } define i64 @f7(i64 %a0) nounwind readnone { entry: -; CHECK: dsra32 ${{[0-9]+}}, ${{[0-9]+}}, 8 +; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 40 %shr = ashr i64 %a0, 40 ret i64 %shr } define i64 @f8(i64 %a0) nounwind readnone { entry: -; CHECK: dsrl32 ${{[0-9]+}}, ${{[0-9]+}}, 8 +; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 40 %shr = lshr i64 %a0, 40 ret i64 %shr } @@ -94,7 +94,7 @@ entry: define i64 @f12(i64 %a0) nounwind readnone { entry: -; CHECK: drotr32 ${{[0-9]+}}, ${{[0-9]+}}, 22 +; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 54 %shl = shl i64 %a0, 10 %shr = lshr i64 %a0, 54 %or = or i64 %shl, %shr diff --git a/test/CodeGen/Mips/mipslopat.ll b/test/CodeGen/Mips/mipslopat.ll index 02798285b499..1f433b9870ce 100644 --- a/test/CodeGen/Mips/mipslopat.ll +++ b/test/CodeGen/Mips/mipslopat.ll @@ -6,7 +6,7 @@ define void @simple_vol_file() nounwind { entry: - %tmp = volatile load i32** @stat_vol_ptr_int, align 4 + %tmp = load volatile i32** @stat_vol_ptr_int, align 4 %0 = bitcast i32* %tmp to i8* call void @llvm.prefetch(i8* %0, i32 0, i32 0, i32 1) %tmp1 = load i32** @stat_ptr_vol_int, align 4 diff --git a/test/CodeGen/Mips/o32_cc_byval.ll b/test/CodeGen/Mips/o32_cc_byval.ll index e6734808ab77..c5cbc7a66b8c 100644 --- a/test/CodeGen/Mips/o32_cc_byval.ll +++ b/test/CodeGen/Mips/o32_cc_byval.ll @@ -12,20 +12,20 @@ define void @f1() nounwind { entry: ; CHECK: lw $[[R1:[0-9]+]], %got(f1.s1)($gp) ; CHECK: addiu $[[R0:[0-9]+]], $[[R1]], %lo(f1.s1) -; CHECK: lw $[[R2:[0-9]+]], 8($[[R0]]) -; CHECK: lw $[[R7:[0-9]+]], 12($[[R0]]) -; CHECK: lw $[[R3:[0-9]+]], 16($[[R0]]) -; CHECK: lw $[[R4:[0-9]+]], 20($[[R0]]) -; CHECK: lw $[[R5:[0-9]+]], 24($[[R0]]) ; CHECK: lw $[[R6:[0-9]+]], 28($[[R0]]) -; CHECK: sw $[[R2]], 16($sp) -; CHECK: sw $[[R7]], 20($sp) -; CHECK: sw $[[R3]], 24($sp) -; CHECK: sw $[[R4]], 28($sp) -; CHECK: sw $[[R5]], 32($sp) +; CHECK: lw $[[R5:[0-9]+]], 24($[[R0]]) +; CHECK: lw $[[R4:[0-9]+]], 20($[[R0]]) +; CHECK: lw $[[R3:[0-9]+]], 16($[[R0]]) +; CHECK: lw $[[R7:[0-9]+]], 12($[[R0]]) +; CHECK: lw $[[R2:[0-9]+]], 8($[[R0]]) ; CHECK: sw $[[R6]], 36($sp) -; CHECK: lw $6, %lo(f1.s1)($[[R1]]) +; CHECK: sw $[[R5]], 32($sp) +; CHECK: sw $[[R4]], 28($sp) +; CHECK: sw $[[R3]], 24($sp) +; CHECK: sw $[[R7]], 20($sp) +; CHECK: sw $[[R2]], 16($sp) ; CHECK: lw $7, 4($[[R0]]) +; CHECK: lw $6, %lo(f1.s1)($[[R1]]) %agg.tmp10 = alloca %struct.S3, align 4 call void @callee1(float 2.000000e+01, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind call void @callee2(%struct.S2* byval @f1.s2) nounwind @@ -44,20 +44,20 @@ declare void @callee3(float, %struct.S3* byval, %struct.S1* byval) define void @f2(float %f, %struct.S1* nocapture byval %s1) nounwind { entry: ; CHECK: addiu $sp, $sp, -56 -; CHECK: sw $6, 64($sp) ; CHECK: sw $7, 68($sp) +; CHECK: sw $6, 64($sp) +; CHECK: lw $4, 88($sp) ; CHECK: ldc1 $f[[F0:[0-9]+]], 80($sp) +; CHECK: lw $[[R3:[0-9]+]], 72($sp) +; CHECK: lw $[[R4:[0-9]+]], 76($sp) ; CHECK: lw $[[R2:[0-9]+]], 68($sp) ; CHECK: lh $[[R1:[0-9]+]], 66($sp) ; CHECK: lb $[[R0:[0-9]+]], 64($sp) -; CHECK: lw $[[R3:[0-9]+]], 72($sp) -; CHECK: lw $[[R4:[0-9]+]], 76($sp) -; CHECK: lw $4, 88($sp) -; CHECK: sw $[[R3]], 16($sp) -; CHECK: sw $[[R4]], 20($sp) -; CHECK: sw $[[R2]], 24($sp) -; CHECK: sw $[[R1]], 28($sp) ; CHECK: sw $[[R0]], 32($sp) +; CHECK: sw $[[R1]], 28($sp) +; CHECK: sw $[[R2]], 24($sp) +; CHECK: sw $[[R4]], 20($sp) +; CHECK: sw $[[R3]], 16($sp) ; CHECK: mfc1 $6, $f[[F0]] %i2 = getelementptr inbounds %struct.S1* %s1, i32 0, i32 5 @@ -81,12 +81,12 @@ declare void @callee4(i32, double, i64, i32, i16 signext, i8 signext, float) define void @f3(%struct.S2* nocapture byval %s2) nounwind { entry: ; CHECK: addiu $sp, $sp, -56 -; CHECK: sw $4, 56($sp) -; CHECK: sw $5, 60($sp) -; CHECK: sw $6, 64($sp) ; CHECK: sw $7, 68($sp) -; CHECK: lw $[[R0:[0-9]+]], 68($sp) +; CHECK: sw $6, 64($sp) +; CHECK: sw $5, 60($sp) +; CHECK: sw $4, 56($sp) ; CHECK: lw $4, 56($sp) +; CHECK: lw $[[R0:[0-9]+]], 68($sp) ; CHECK: sw $[[R0]], 24($sp) %arrayidx = getelementptr inbounds %struct.S2* %s2, i32 0, i32 0, i32 0 @@ -100,14 +100,14 @@ entry: define void @f4(float %f, %struct.S3* nocapture byval %s3, %struct.S1* nocapture byval %s1) nounwind { entry: ; CHECK: addiu $sp, $sp, -56 -; CHECK: sw $5, 60($sp) -; CHECK: sw $6, 64($sp) ; CHECK: sw $7, 68($sp) +; CHECK: sw $6, 64($sp) +; CHECK: sw $5, 60($sp) +; CHECK: lw $4, 68($sp) ; CHECK: lw $[[R1:[0-9]+]], 88($sp) ; CHECK: lb $[[R0:[0-9]+]], 60($sp) -; CHECK: lw $4, 68($sp) -; CHECK: sw $[[R1]], 24($sp) ; CHECK: sw $[[R0]], 32($sp) +; CHECK: sw $[[R1]], 24($sp) %i = getelementptr inbounds %struct.S1* %s1, i32 0, i32 2 %tmp = load i32* %i, align 4, !tbaa !0 diff --git a/test/CodeGen/Mips/private.ll b/test/CodeGen/Mips/private.ll index 4cc48f098a9e..d1a67fd9f4bf 100644 --- a/test/CodeGen/Mips/private.ll +++ b/test/CodeGen/Mips/private.ll @@ -1,19 +1,20 @@ ; Test to make sure that the 'private' is used correctly. ; -; RUN: llc < %s -march=mips > %t -; RUN: grep \\\$foo: %t -; RUN: grep call.*\\\$foo %t -; RUN: grep \\\$baz: %t -; RUN: grep lw.*\\\$baz %t +; RUN: llc -march=mips < %s | FileCheck %s define private void @foo() { - ret void +; CHECK: foo: + ret void } @baz = private global i32 4 define i32 @bar() { - call void @foo() - %1 = load i32* @baz, align 4 - ret i32 %1 +; CHECK: bar: +; CHECK: call16($foo) +; CHECK: lw $[[R0:[0-9]+]], %got($baz)($ +; CHECK: lw ${{[0-9]+}}, %lo($baz)($[[R0]]) + call void @foo() + %1 = load i32* @baz, align 4 + ret i32 %1 } diff --git a/test/CodeGen/Mips/rotate.ll b/test/CodeGen/Mips/rotate.ll index 8e27f4aad6eb..4f3cfb7df41c 100644 --- a/test/CodeGen/Mips/rotate.ll +++ b/test/CodeGen/Mips/rotate.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s +; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s ; CHECK: rotrv $2, $4 define i32 @rot0(i32 %a, i32 %b) nounwind readnone { diff --git a/test/CodeGen/Mips/swzero.ll b/test/CodeGen/Mips/swzero.ll new file mode 100644 index 000000000000..da1e036eb997 --- /dev/null +++ b/test/CodeGen/Mips/swzero.ll @@ -0,0 +1,19 @@ +; RUN: llc -march=mipsel < %s | FileCheck %s + +%struct.unaligned = type <{ i32 }> + +define void @zero_u(%struct.unaligned* nocapture %p) nounwind { +entry: +; CHECK: usw $zero + %x = getelementptr inbounds %struct.unaligned* %p, i32 0, i32 0 + store i32 0, i32* %x, align 1 + ret void +} + +define void @zero_a(i32* nocapture %p) nounwind { +entry: +; CHECK: sw $zero + store i32 0, i32* %p, align 4 + ret void +} + diff --git a/test/CodeGen/Mips/tls.ll b/test/CodeGen/Mips/tls.ll index b0474b4c4434..a3c4768bb4b5 100644 --- a/test/CodeGen/Mips/tls.ll +++ b/test/CodeGen/Mips/tls.ll @@ -1,7 +1,8 @@ ; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=PIC ; RUN: llc -march=mipsel -relocation-model=static < %s \ ; RUN: | FileCheck %s -check-prefix=STATIC - +; RUN: llc -march=mipsel -relocation-model=static < %s \ +; RUN: -mips-fix-global-base-reg=false | FileCheck %s -check-prefix=STATICGP @t1 = thread_local global i32 0, align 4 @@ -39,8 +40,32 @@ entry: ; PIC: jalr $25 ; PIC: lw $2, 0($2) +; STATICGP: lui $[[R0:[0-9]+]], %hi(__gnu_local_gp) +; STATICGP: addiu $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp) +; STATICGP: lw ${{[0-9]+}}, %gottprel(t2)($[[GP]]) +; STATIC: lui $gp, %hi(__gnu_local_gp) +; STATIC: addiu $gp, $gp, %lo(__gnu_local_gp) ; STATIC: rdhwr $3, $29 ; STATIC: lw $[[R0:[0-9]+]], %gottprel(t2)($gp) ; STATIC: addu $[[R1:[0-9]+]], $3, $[[R0]] ; STATIC: lw $2, 0($[[R1]]) } + +@f3.i = internal thread_local unnamed_addr global i32 1, align 4 + +define i32 @f3() nounwind { +entry: +; CHECK: f3: + +; PIC: addiu $4, $gp, %tlsldm(f3.i) +; PIC: jalr $25 +; PIC: lui $[[R0:[0-9]+]], %dtprel_hi(f3.i) +; PIC: addu $[[R1:[0-9]+]], $[[R0]], $2 +; PIC: lw ${{[0-9]+}}, %dtprel_lo(f3.i)($[[R1]]) + + %0 = load i32* @f3.i, align 4 + %inc = add nsw i32 %0, 1 + store i32 %inc, i32* @f3.i, align 4 + ret i32 %inc +} + diff --git a/test/CodeGen/Mips/unalignedload.ll b/test/CodeGen/Mips/unalignedload.ll index 433e896d194b..6a087ba46e64 100644 --- a/test/CodeGen/Mips/unalignedload.ll +++ b/test/CodeGen/Mips/unalignedload.ll @@ -9,27 +9,27 @@ define void @foo1() nounwind { entry: -; CHECK-EL: lw $25, %call16(foo2) ; CHECK-EL: ulhu $4, 2 +; CHECK-EL: lw $25, %call16(foo2) ; CHECK-EL: lw $[[R0:[0-9]+]], %got(s4) ; CHECK-EL: lbu $[[R1:[0-9]+]], 6($[[R0]]) -; CHECK-EL: ulhu $[[R2:[0-9]+]], 4($[[R0]]) ; CHECK-EL: sll $[[R3:[0-9]+]], $[[R1]], 16 +; CHECK-EL: ulhu $[[R2:[0-9]+]], 4($[[R0]]) +; CHECK-EL: or $5, $[[R2]], $[[R3]] ; CHECK-EL: ulw $4, 0($[[R0]]) ; CHECK-EL: lw $25, %call16(foo4) -; CHECK-EL: or $5, $[[R2]], $[[R3]] ; CHECK-EB: ulhu $[[R0:[0-9]+]], 2 -; CHECK-EB: lw $25, %call16(foo2) ; CHECK-EB: sll $4, $[[R0]], 16 +; CHECK-EB: lw $25, %call16(foo2) ; CHECK-EB: lw $[[R1:[0-9]+]], %got(s4) -; CHECK-EB: ulhu $[[R2:[0-9]+]], 4($[[R1]]) ; CHECK-EB: lbu $[[R3:[0-9]+]], 6($[[R1]]) -; CHECK-EB: sll $[[R4:[0-9]+]], $[[R2]], 16 ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R3]], 8 +; CHECK-EB: ulhu $[[R2:[0-9]+]], 4($[[R1]]) +; CHECK-EB: sll $[[R4:[0-9]+]], $[[R2]], 16 +; CHECK-EB: or $5, $[[R4]], $[[R5]] ; CHECK-EB: ulw $4, 0($[[R1]]) ; CHECK-EB: lw $25, %call16(foo4) -; CHECK-EB: or $5, $[[R4]], $[[R5]] tail call void @foo2(%struct.S1* byval getelementptr inbounds (%struct.S2* @s2, i32 0, i32 1)) nounwind tail call void @foo4(%struct.S4* byval @s4) nounwind diff --git a/test/CodeGen/Mips/zeroreg.ll b/test/CodeGen/Mips/zeroreg.ll new file mode 100644 index 000000000000..b890e1dba9fc --- /dev/null +++ b/test/CodeGen/Mips/zeroreg.ll @@ -0,0 +1,27 @@ +; RUN: llc < %s -march=mipsel | FileCheck %s + +@g1 = external global i32 + +define i32 @foo0(i32 %s) nounwind readonly { +entry: +; CHECK-NOT: addiu +; CHECK: movn + %tobool = icmp ne i32 %s, 0 + %0 = load i32* @g1, align 4, !tbaa !0 + %cond = select i1 %tobool, i32 0, i32 %0 + ret i32 %cond +} + +define i32 @foo1(i32 %s) nounwind readonly { +entry: +; CHECK-NOT: addiu +; CHECK: movz + %tobool = icmp ne i32 %s, 0 + %0 = load i32* @g1, align 4, !tbaa !0 + %cond = select i1 %tobool, i32 %0, i32 0 + ret i32 %cond +} + +!0 = metadata !{metadata !"int", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA", null} |